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GET /api/patches/812961/?format=api
{ "id": 812961, "url": "http://patchwork.ozlabs.org/api/patches/812961/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-11-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-11-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:07", "name": "[v2,10/16] tcg/aarch64: Fully convert tcg_target_op_def", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "78e97d3a3ab478f897fc478c792fbe34b7a94ea5", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-11-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812961/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812961/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"jayI5f04\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9M65sRPz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:32:50 +1000 (AEST)", "from localhost ([::1]:36914 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro7E-0008Qr-SJ\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:32:48 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38081)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0D-0001ok-EQ\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:35 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0B-00076n-Ar\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:33 -0400", "from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:36711)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro0B-00075S-0P\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:31 -0400", "by mail-pf0-x22e.google.com with SMTP id e199so19405543pfh.3\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:30 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.28\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:28 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=T3cqAUA9w3Delh5SFcIZqMIelJzHo2BSO6oOYIwjG9o=;\n\tb=jayI5f04TV+1Cs+pR9L18GeTbRAWCXwM2NAh7JF2ljJFUFGklWdffp148993n89ZZD\n\ttVxbgSbNRuLDd9c+82WFIK4eqa1mwqYR2WCanQ16wMcLEm51X+/1G92xtczRrIfpj9/e\n\t9jKlQEFfzSQYXrUme1jXFkxJXc0Xg/Z0RajdY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=T3cqAUA9w3Delh5SFcIZqMIelJzHo2BSO6oOYIwjG9o=;\n\tb=RBgcad6rRDPoEs7g61ywws7uWo9sZj2efuNTmV2PBx5NTSkOeYCroLVlMTao0B7LcJ\n\t81wl3SmyAK6J3FfU/tdp+HDcMEQGcgyaNChvCesHSbCeCiyEBjTcvykf7/11eon1cudR\n\tR8F+hMnoFuqO3wSMQjS59IL5zj180Ac9HxMTY6Rw7/x9QD6NMZX6VAwg1bBOB8hrc54A\n\t4E735lK0Hf/GSPaJ/xza0KBY/r6hp+VCerUa06vmwnNLc2Cor9i2+zIUs7L74UVrYK5E\n\t+xB6TXzDtHFy94MPIdbsbEibRlJgjSEpJ6j0IqeBoX2bV8XtDpGAOL7MbCsbEI2k2ev2\n\tBCLw==", "X-Gm-Message-State": "AHPjjUg/RvNxKh6nbbQjgNdt/kXdLd+RKtuaArE2sOdUkNX/8WgJvj0Z\n\tAJk17AfXYjCQUG4rDvfiJg==", "X-Google-Smtp-Source": "ADKCNb6h5BOsaNQndR6NWomGKY0QrzkmeCq2WfJRDFVTjcWmOMcvWfh3pk9Fx+LQOzF1WHCLGzl/Ag==", "X-Received": "by 10.98.86.216 with SMTP id h85mr15854684pfj.88.1505233529748; \n\tTue, 12 Sep 2017 09:25:29 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:07 -0700", "Message-Id": "<20170912162513.21694-11-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22e", "Subject": "[Qemu-devel] [PATCH v2 10/16] tcg/aarch64: Fully convert\n\ttcg_target_op_def", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/aarch64/tcg-target.inc.c | 282 +++++++++++++++++++++++--------------------\n 1 file changed, 151 insertions(+), 131 deletions(-)", "diff": "diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c\nindex c2f3812214..1ff32e43f5 100644\n--- a/tcg/aarch64/tcg-target.inc.c\n+++ b/tcg/aarch64/tcg-target.inc.c\n@@ -1786,141 +1786,161 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,\n #undef REG0\n }\n \n-static const TCGTargetOpDef aarch64_op_defs[] = {\n- { INDEX_op_exit_tb, { } },\n- { INDEX_op_goto_tb, { } },\n- { INDEX_op_br, { } },\n- { INDEX_op_goto_ptr, { \"r\" } },\n-\n- { INDEX_op_ld8u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld8s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld16u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld16s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld8u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld8s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld16u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld16s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld32u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld32s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_st8_i32, { \"rZ\", \"r\" } },\n- { INDEX_op_st16_i32, { \"rZ\", \"r\" } },\n- { INDEX_op_st_i32, { \"rZ\", \"r\" } },\n- { INDEX_op_st8_i64, { \"rZ\", \"r\" } },\n- { INDEX_op_st16_i64, { \"rZ\", \"r\" } },\n- { INDEX_op_st32_i64, { \"rZ\", \"r\" } },\n- { INDEX_op_st_i64, { \"rZ\", \"r\" } },\n-\n- { INDEX_op_add_i32, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_add_i64, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_sub_i32, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_sub_i64, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_mul_i32, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_mul_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_div_i32, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_div_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_divu_i32, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_divu_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_rem_i32, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_rem_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_remu_i32, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_remu_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_and_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_and_i64, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_or_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_or_i64, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_xor_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_xor_i64, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_andc_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_andc_i64, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_orc_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_orc_i64, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_eqv_i32, { \"r\", \"r\", \"rL\" } },\n- { INDEX_op_eqv_i64, { \"r\", \"r\", \"rL\" } },\n-\n- { INDEX_op_neg_i32, { \"r\", \"r\" } },\n- { INDEX_op_neg_i64, { \"r\", \"r\" } },\n- { INDEX_op_not_i32, { \"r\", \"r\" } },\n- { INDEX_op_not_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_shl_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_shr_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_sar_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotl_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotr_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_clz_i32, { \"r\", \"r\", \"rAL\" } },\n- { INDEX_op_ctz_i32, { \"r\", \"r\", \"rAL\" } },\n- { INDEX_op_shl_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_shr_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_sar_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotl_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotr_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_clz_i64, { \"r\", \"r\", \"rAL\" } },\n- { INDEX_op_ctz_i64, { \"r\", \"r\", \"rAL\" } },\n-\n- { INDEX_op_brcond_i32, { \"r\", \"rA\" } },\n- { INDEX_op_brcond_i64, { \"r\", \"rA\" } },\n- { INDEX_op_setcond_i32, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_setcond_i64, { \"r\", \"r\", \"rA\" } },\n- { INDEX_op_movcond_i32, { \"r\", \"r\", \"rA\", \"rZ\", \"rZ\" } },\n- { INDEX_op_movcond_i64, { \"r\", \"r\", \"rA\", \"rZ\", \"rZ\" } },\n-\n- { INDEX_op_qemu_ld_i32, { \"r\", \"l\" } },\n- { INDEX_op_qemu_ld_i64, { \"r\", \"l\" } },\n- { INDEX_op_qemu_st_i32, { \"lZ\", \"l\" } },\n- { INDEX_op_qemu_st_i64, { \"lZ\", \"l\" } },\n-\n- { INDEX_op_bswap16_i32, { \"r\", \"r\" } },\n- { INDEX_op_bswap32_i32, { \"r\", \"r\" } },\n- { INDEX_op_bswap16_i64, { \"r\", \"r\" } },\n- { INDEX_op_bswap32_i64, { \"r\", \"r\" } },\n- { INDEX_op_bswap64_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_ext8s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext16s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext8u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext16u_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_ext8s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext16s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext32s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext8u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext16u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext32u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext_i32_i64, { \"r\", \"r\" } },\n- { INDEX_op_extu_i32_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_deposit_i32, { \"r\", \"0\", \"rZ\" } },\n- { INDEX_op_deposit_i64, { \"r\", \"0\", \"rZ\" } },\n- { INDEX_op_extract_i32, { \"r\", \"r\" } },\n- { INDEX_op_extract_i64, { \"r\", \"r\" } },\n- { INDEX_op_sextract_i32, { \"r\", \"r\" } },\n- { INDEX_op_sextract_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_add2_i32, { \"r\", \"r\", \"rZ\", \"rZ\", \"rA\", \"rMZ\" } },\n- { INDEX_op_add2_i64, { \"r\", \"r\", \"rZ\", \"rZ\", \"rA\", \"rMZ\" } },\n- { INDEX_op_sub2_i32, { \"r\", \"r\", \"rZ\", \"rZ\", \"rA\", \"rMZ\" } },\n- { INDEX_op_sub2_i64, { \"r\", \"r\", \"rZ\", \"rZ\", \"rA\", \"rMZ\" } },\n-\n- { INDEX_op_muluh_i64, { \"r\", \"r\", \"r\" } },\n- { INDEX_op_mulsh_i64, { \"r\", \"r\", \"r\" } },\n-\n- { INDEX_op_mb, { } },\n- { -1 },\n-};\n-\n static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n {\n- int i, n = ARRAY_SIZE(aarch64_op_defs);\n+ static const TCGTargetOpDef r = { .args_ct_str = { \"r\" } };\n+ static const TCGTargetOpDef r_r = { .args_ct_str = { \"r\", \"r\" } };\n+ static const TCGTargetOpDef r_l = { .args_ct_str = { \"r\", \"l\" } };\n+ static const TCGTargetOpDef r_rA = { .args_ct_str = { \"r\", \"rA\" } };\n+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { \"rZ\", \"r\" } };\n+ static const TCGTargetOpDef lZ_l = { .args_ct_str = { \"lZ\", \"l\" } };\n+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { \"r\", \"r\", \"r\" } };\n+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_r_rA = { .args_ct_str = { \"r\", \"r\", \"rA\" } };\n+ static const TCGTargetOpDef r_r_rL = { .args_ct_str = { \"r\", \"r\", \"rL\" } };\n+ static const TCGTargetOpDef r_r_rAL\n+ = { .args_ct_str = { \"r\", \"r\", \"rAL\" } };\n+ static const TCGTargetOpDef dep\n+ = { .args_ct_str = { \"r\", \"0\", \"rZ\" } };\n+ static const TCGTargetOpDef movc\n+ = { .args_ct_str = { \"r\", \"r\", \"rA\", \"rZ\", \"rZ\" } };\n+ static const TCGTargetOpDef add2\n+ = { .args_ct_str = { \"r\", \"r\", \"rZ\", \"rZ\", \"rA\", \"rMZ\" } };\n+\n+ switch (op) {\n+ case INDEX_op_goto_ptr:\n+ return &r;\n \n- for (i = 0; i < n; ++i) {\n- if (aarch64_op_defs[i].op == op) {\n- return &aarch64_op_defs[i];\n- }\n+ case INDEX_op_ld8u_i32:\n+ case INDEX_op_ld8s_i32:\n+ case INDEX_op_ld16u_i32:\n+ case INDEX_op_ld16s_i32:\n+ case INDEX_op_ld_i32:\n+ case INDEX_op_ld8u_i64:\n+ case INDEX_op_ld8s_i64:\n+ case INDEX_op_ld16u_i64:\n+ case INDEX_op_ld16s_i64:\n+ case INDEX_op_ld32u_i64:\n+ case INDEX_op_ld32s_i64:\n+ case INDEX_op_ld_i64:\n+ case INDEX_op_neg_i32:\n+ case INDEX_op_neg_i64:\n+ case INDEX_op_not_i32:\n+ case INDEX_op_not_i64:\n+ case INDEX_op_bswap16_i32:\n+ case INDEX_op_bswap32_i32:\n+ case INDEX_op_bswap16_i64:\n+ case INDEX_op_bswap32_i64:\n+ case INDEX_op_bswap64_i64:\n+ case INDEX_op_ext8s_i32:\n+ case INDEX_op_ext16s_i32:\n+ case INDEX_op_ext8u_i32:\n+ case INDEX_op_ext16u_i32:\n+ case INDEX_op_ext8s_i64:\n+ case INDEX_op_ext16s_i64:\n+ case INDEX_op_ext32s_i64:\n+ case INDEX_op_ext8u_i64:\n+ case INDEX_op_ext16u_i64:\n+ case INDEX_op_ext32u_i64:\n+ case INDEX_op_ext_i32_i64:\n+ case INDEX_op_extu_i32_i64:\n+ case INDEX_op_extract_i32:\n+ case INDEX_op_extract_i64:\n+ case INDEX_op_sextract_i32:\n+ case INDEX_op_sextract_i64:\n+ return &r_r;\n+\n+ case INDEX_op_st8_i32:\n+ case INDEX_op_st16_i32:\n+ case INDEX_op_st_i32:\n+ case INDEX_op_st8_i64:\n+ case INDEX_op_st16_i64:\n+ case INDEX_op_st32_i64:\n+ case INDEX_op_st_i64:\n+ return &rZ_r;\n+\n+ case INDEX_op_add_i32:\n+ case INDEX_op_add_i64:\n+ case INDEX_op_sub_i32:\n+ case INDEX_op_sub_i64:\n+ case INDEX_op_setcond_i32:\n+ case INDEX_op_setcond_i64:\n+ return &r_r_rA;\n+\n+ case INDEX_op_mul_i32:\n+ case INDEX_op_mul_i64:\n+ case INDEX_op_div_i32:\n+ case INDEX_op_div_i64:\n+ case INDEX_op_divu_i32:\n+ case INDEX_op_divu_i64:\n+ case INDEX_op_rem_i32:\n+ case INDEX_op_rem_i64:\n+ case INDEX_op_remu_i32:\n+ case INDEX_op_remu_i64:\n+ case INDEX_op_muluh_i64:\n+ case INDEX_op_mulsh_i64:\n+ return &r_r_r;\n+\n+ case INDEX_op_and_i32:\n+ case INDEX_op_and_i64:\n+ case INDEX_op_or_i32:\n+ case INDEX_op_or_i64:\n+ case INDEX_op_xor_i32:\n+ case INDEX_op_xor_i64:\n+ case INDEX_op_andc_i32:\n+ case INDEX_op_andc_i64:\n+ case INDEX_op_orc_i32:\n+ case INDEX_op_orc_i64:\n+ case INDEX_op_eqv_i32:\n+ case INDEX_op_eqv_i64:\n+ return &r_r_rL;\n+\n+ case INDEX_op_shl_i32:\n+ case INDEX_op_shr_i32:\n+ case INDEX_op_sar_i32:\n+ case INDEX_op_rotl_i32:\n+ case INDEX_op_rotr_i32:\n+ case INDEX_op_shl_i64:\n+ case INDEX_op_shr_i64:\n+ case INDEX_op_sar_i64:\n+ case INDEX_op_rotl_i64:\n+ case INDEX_op_rotr_i64:\n+ return &r_r_ri;\n+\n+ case INDEX_op_clz_i32:\n+ case INDEX_op_ctz_i32:\n+ case INDEX_op_clz_i64:\n+ case INDEX_op_ctz_i64:\n+ return &r_r_rAL;\n+\n+ case INDEX_op_brcond_i32:\n+ case INDEX_op_brcond_i64:\n+ return &r_rA;\n+\n+ case INDEX_op_movcond_i32:\n+ case INDEX_op_movcond_i64:\n+ return &movc;\n+\n+ case INDEX_op_qemu_ld_i32:\n+ case INDEX_op_qemu_ld_i64:\n+ return &r_l;\n+ case INDEX_op_qemu_st_i32:\n+ case INDEX_op_qemu_st_i64:\n+ return &lZ_l;\n+\n+ case INDEX_op_deposit_i32:\n+ case INDEX_op_deposit_i64:\n+ return &dep;\n+\n+ case INDEX_op_add2_i32:\n+ case INDEX_op_add2_i64:\n+ case INDEX_op_sub2_i32:\n+ case INDEX_op_sub2_i64:\n+ return &add2;\n+\n+ default:\n+ return NULL;\n }\n- return NULL;\n }\n \n static void tcg_target_init(TCGContext *s)\n", "prefixes": [ "v2", "10/16" ] }