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GET /api/patches/812960/?format=api
{ "id": 812960, "url": "http://patchwork.ozlabs.org/api/patches/812960/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-9-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-9-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:05", "name": "[v2,08/16] target/arm: Use vector infrastructure for aa64 add/sub/logic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0a5ff456c54d77fb33bf7b2de54abce92f1223a3", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-9-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812960/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812960/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"JjckUlqU\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9Ly4rKmz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:32:42 +1000 (AEST)", "from localhost ([::1]:36913 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro76-0008IM-NQ\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:32:40 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38057)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro0C-0001nm-Hf\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:34 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro08-00073U-67\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:32 -0400", "from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:35938)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro07-000738-Th\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:28 -0400", "by mail-pg0-x234.google.com with SMTP id i130so14869833pgc.3\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:27 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.25\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=ByRv4yStlmXXTgaHEqSXUghKE6M2Phz6mSRs5MIlqMI=;\n\tb=JjckUlqUa3Dm5sgp5Kl3HgfPDimwFR8OkZXk+WPTz94ChclLftuiIizhJHm7crQ3zl\n\thCrcvifmmZ6XtpU+9BsUDLhOUh3/081WYpw4CMHx8HzF4xQloQ3anWe09NTMUnsh1eky\n\twEcqYY41M1jk879/Q2Q8Ejgf0Fky9KM68M9kA=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ByRv4yStlmXXTgaHEqSXUghKE6M2Phz6mSRs5MIlqMI=;\n\tb=XyAU5GNWX8kwSdniLYsXEimNP+x066IILIQgJbLhKKnzrVDV7kXFW/MnGE9Sayf8WC\n\tSVAs+UXrbj7rPqShE7RrVlXoRN+yDsIQ9Mu3U4++fXuXbQwIdVVLrBsvkQ+T1O2HqmU1\n\tlkECZ7ITZp3FPHjJy0SQvKTMVTiGIKiztWQBL2aauLRFKwJrZ0/G0fk2UYba9+YykmWr\n\tzu8m8mNLV8cXSaS98KlFWWusFLEC6hGhrxkDO+y+DN7kHE7SSYfzuAMKrCpox1W0nA4Z\n\tHUZwxbB1zCsAsRKipbH7U4z0E0SO382DwujrB8Mks2E9jAIk4YpjMrJPX9+bhY2vDH8S\n\tzzMA==", "X-Gm-Message-State": "AHPjjUhuNP3DC7lkAgx/l3U/uukAX+C0isgaleJt4ol8D9xtbVz6wk18\n\trkxG6v7Jh1TRASdam7onHA==", "X-Google-Smtp-Source": "ADKCNb7kgCtZdLA5dBfqVxOr1McilTdyDslPlLZ5b8DP7yErMBioWS9tgOc0kgmZiHTA2zfnIHcx1g==", "X-Received": "by 10.98.211.72 with SMTP id q69mr15458989pfg.308.1505233526743; \n\tTue, 12 Sep 2017 09:25:26 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:05 -0700", "Message-Id": "<20170912162513.21694-9-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::234", "Subject": "[Qemu-devel] [PATCH v2 08/16] target/arm: Use vector infrastructure\n\tfor aa64 add/sub/logic", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/translate-a64.c | 137 ++++++++++++++++++++++++++++-----------------\n 1 file changed, 87 insertions(+), 50 deletions(-)", "diff": "diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex 9017e30510..d01a180fba 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -21,6 +21,7 @@\n #include \"cpu.h\"\n #include \"exec/exec-all.h\"\n #include \"tcg-op.h\"\n+#include \"tcg-op-gvec.h\"\n #include \"qemu/log.h\"\n #include \"arm_ldst.h\"\n #include \"translate.h\"\n@@ -82,6 +83,7 @@ typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);\n typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);\n typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);\n typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);\n+typedef void GVecGenTwoFn(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);\n \n /* initialize TCG globals. */\n void a64_translate_init(void)\n@@ -537,6 +539,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno,\n return offs;\n }\n \n+/* Return the offset info CPUARMState of the \"whole\" vector register Qn. */\n+static inline int vec_full_reg_offset(DisasContext *s, int regno)\n+{\n+ assert_fp_access_checked(s);\n+ return offsetof(CPUARMState, vfp.regs[regno * 2]);\n+}\n+\n+/* Return the byte size of the \"whole\" vector register, VL / 8. */\n+static inline int vec_full_reg_size(DisasContext *s)\n+{\n+ /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.\n+ In the meantime this is just the AdvSIMD length of 128. */\n+ return 128 / 8;\n+}\n+\n /* Return the offset into CPUARMState of a slice (from\n * the least significant end) of FP register Qn (ie\n * Dn, Sn, Hn or Bn).\n@@ -9047,11 +9064,38 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)\n bool is_q = extract32(insn, 30, 1);\n TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];\n int pass;\n+ GVecGenTwoFn *gvec_op;\n \n if (!fp_access_check(s)) {\n return;\n }\n \n+ switch (size + 4 * is_u) {\n+ case 0: /* AND */\n+ gvec_op = tcg_gen_gvec_and;\n+ goto do_gvec;\n+ case 1: /* BIC */\n+ gvec_op = tcg_gen_gvec_andc;\n+ goto do_gvec;\n+ case 2: /* ORR */\n+ gvec_op = tcg_gen_gvec_or;\n+ goto do_gvec;\n+ case 3: /* ORN */\n+ gvec_op = tcg_gen_gvec_orc;\n+ goto do_gvec;\n+ case 4: /* EOR */\n+ gvec_op = tcg_gen_gvec_xor;\n+ goto do_gvec;\n+ do_gvec:\n+ gvec_op(vec_full_reg_offset(s, rd),\n+ vec_full_reg_offset(s, rn),\n+ vec_full_reg_offset(s, rm),\n+ is_q ? 16 : 8, vec_full_reg_size(s));\n+ return;\n+ }\n+\n+ /* Note that we've now eliminated all !is_u. */\n+\n tcg_op1 = tcg_temp_new_i64();\n tcg_op2 = tcg_temp_new_i64();\n tcg_res[0] = tcg_temp_new_i64();\n@@ -9061,47 +9105,27 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)\n read_vec_element(s, tcg_op1, rn, pass, MO_64);\n read_vec_element(s, tcg_op2, rm, pass, MO_64);\n \n- if (!is_u) {\n- switch (size) {\n- case 0: /* AND */\n- tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);\n- break;\n- case 1: /* BIC */\n- tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2);\n- break;\n- case 2: /* ORR */\n- tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);\n- break;\n- case 3: /* ORN */\n- tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2);\n- break;\n- }\n- } else {\n- if (size != 0) {\n- /* B* ops need res loaded to operate on */\n- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);\n- }\n+ /* B* ops need res loaded to operate on */\n+ read_vec_element(s, tcg_res[pass], rd, pass, MO_64);\n \n- switch (size) {\n- case 0: /* EOR */\n- tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);\n- break;\n- case 1: /* BSL bitwise select */\n- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);\n- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n- tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);\n- break;\n- case 2: /* BIT, bitwise insert if true */\n- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);\n- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);\n- break;\n- case 3: /* BIF, bitwise insert if false */\n- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n- tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);\n- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);\n- break;\n- }\n+ switch (size) {\n+ case 1: /* BSL bitwise select */\n+ tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);\n+ tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n+ tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);\n+ break;\n+ case 2: /* BIT, bitwise insert if true */\n+ tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n+ tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);\n+ tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);\n+ break;\n+ case 3: /* BIF, bitwise insert if false */\n+ tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);\n+ tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);\n+ tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);\n+ break;\n+ default:\n+ g_assert_not_reached();\n }\n }\n \n@@ -9375,6 +9399,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)\n int rn = extract32(insn, 5, 5);\n int rd = extract32(insn, 0, 5);\n int pass;\n+ GVecGenTwoFn *gvec_op;\n \n switch (opcode) {\n case 0x13: /* MUL, PMUL */\n@@ -9414,6 +9439,28 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)\n return;\n }\n \n+ switch (opcode) {\n+ case 0x10: /* ADD, SUB */\n+ {\n+ static GVecGenTwoFn * const fns[4][2] = {\n+ { tcg_gen_gvec_add8, tcg_gen_gvec_sub8 },\n+ { tcg_gen_gvec_add16, tcg_gen_gvec_sub16 },\n+ { tcg_gen_gvec_add32, tcg_gen_gvec_sub32 },\n+ { tcg_gen_gvec_add64, tcg_gen_gvec_sub64 },\n+ };\n+ gvec_op = fns[size][u];\n+ goto do_gvec;\n+ }\n+ break;\n+\n+ do_gvec:\n+ gvec_op(vec_full_reg_offset(s, rd),\n+ vec_full_reg_offset(s, rn),\n+ vec_full_reg_offset(s, rm),\n+ is_q ? 16 : 8, vec_full_reg_size(s));\n+ return;\n+ }\n+\n if (size == 3) {\n assert(is_q);\n for (pass = 0; pass < 2; pass++) {\n@@ -9586,16 +9633,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)\n genfn = fns[size][u];\n break;\n }\n- case 0x10: /* ADD, SUB */\n- {\n- static NeonGenTwoOpFn * const fns[3][2] = {\n- { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },\n- { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },\n- { tcg_gen_add_i32, tcg_gen_sub_i32 },\n- };\n- genfn = fns[size][u];\n- break;\n- }\n case 0x11: /* CMTST, CMEQ */\n {\n static NeonGenTwoOpFn * const fns[3][2] = {\n", "prefixes": [ "v2", "08/16" ] }