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GET /api/patches/812954/?format=api
{ "id": 812954, "url": "http://patchwork.ozlabs.org/api/patches/812954/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-2-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-2-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:24:58", "name": "[v2,01/16] tcg: Add expanders for out-of-line vector helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a959739a69ba3ef519616888d631cbef18a2493c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-2-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812954/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"OGpsMp9z\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9GT17Zfz9s7f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:28:49 +1000 (AEST)", "from localhost ([::1]:36894 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro3L-0004Vw-40\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:28:47 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:37798)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro02-0001dE-3w\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1drnzz-0006xl-2t\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:22 -0400", "from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]:34138)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1drnzy-0006xI-Qa\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:19 -0400", "by mail-pf0-x231.google.com with SMTP id e1so19440042pfk.1\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:18 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.16\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=aQ1XEDQsc9UTqPTlSfnW1xqLW4406WUrga5mz4xOARE=;\n\tb=OGpsMp9zZrAOm6qRqALCWvQyYUZrREH3kRaiCPBEwdY6pdVh4TOM4KXhKY55FVOjH3\n\tpwiCWEcsSCoQDwqiYUsOoGBXFBxRsAlzQNZFlfCEBiE1Zw5GA37kxn2xnnuLSB4WLaJa\n\t4eG4QPwE+Dyj1W0xiM/wDVmsjkwNCEK1xFy+g=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=aQ1XEDQsc9UTqPTlSfnW1xqLW4406WUrga5mz4xOARE=;\n\tb=d1Wrzny1fDiByVbYO5PQ8lK75ocatarw4ElAC5V/Mkkvggny/kglbWUCKwtoBJayz/\n\tKMX+wJh+ubosvAUHbTehXVvV8kt0tvMga7WIzO2Xy/Iv3//RBErQIanPjNPZCwtZ6ALl\n\twJRgeG9i0vxgix/uNLDURQVvcanwGZenyKLQOTd20xzBclD5wyxvAdP4TP2Gk/GhqMpf\n\tiSK0rEFR9f0Hmi7lNrntGgqy/TLOHkSfttUaSeQ8Nn9/LVP0/ONJcQe6xSonivyx2VfK\n\tNm8jqMtmKXgIiFoEh70UK9Y28uO5GSx2zxuTzf7rRxCuWzWe6TkfBWr6tdvCNQgc7+j/\n\tBlow==", "X-Gm-Message-State": "AHPjjUgbFtMvp03+BbYLL+gkXc7IWGqKtE7r0QNRzmHPW4xLFbKdUfc9\n\tfp/fhVVPXHiiGGNgogr9hw==", "X-Google-Smtp-Source": "ADKCNb7My5r3x2nfMYppPtOPr/uqcwQIFa4KSdg6+3a26uqkgB0Jq2j3wYk38NFH7M2NTrsqmkqVkA==", "X-Received": "by 10.99.62.142 with SMTP id l136mr15273941pga.130.1505233517540;\n\tTue, 12 Sep 2017 09:25:17 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:24:58 -0700", "Message-Id": "<20170912162513.21694-2-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::231", "Subject": "[Qemu-devel] [PATCH v2 01/16] tcg: Add expanders for out-of-line\n\tvector helpers", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This is a minimum extraction from a full generic vector patchset\nin order to support simultaneous development in target/arm.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n Makefile.target | 5 +--\n tcg/tcg-gvec-desc.h | 49 ++++++++++++++++++++++++++++\n tcg/tcg-op-gvec.h | 43 +++++++++++++++++++++++++\n tcg/tcg-op-gvec.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 188 insertions(+), 2 deletions(-)\n create mode 100644 tcg/tcg-gvec-desc.h\n create mode 100644 tcg/tcg-op-gvec.h\n create mode 100644 tcg/tcg-op-gvec.c", "diff": "diff --git a/Makefile.target b/Makefile.target\nindex 7f42c45db8..e647b6e2cb 100644\n--- a/Makefile.target\n+++ b/Makefile.target\n@@ -93,8 +93,9 @@ all: $(PROGS) stap\n # cpu emulator library\n obj-y += exec.o\n obj-y += accel/\n-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o\n-obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/tcg-runtime.o\n+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-gvec.o\n+obj-$(CONFIG_TCG) += tcg/optimize.o tcg/tcg-common.o\n+obj-$(CONFIG_TCG) += tcg/tcg-runtime.o\n obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o\n obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o\n obj-y += fpu/softfloat.o\ndiff --git a/tcg/tcg-gvec-desc.h b/tcg/tcg-gvec-desc.h\nnew file mode 100644\nindex 0000000000..8ba9a8168d\n--- /dev/null\n+++ b/tcg/tcg-gvec-desc.h\n@@ -0,0 +1,49 @@\n+/*\n+ * Generic vector operation descriptor\n+ *\n+ * Copyright (c) 2017 Linaro\n+ *\n+ * This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU Lesser General Public\n+ * License as published by the Free Software Foundation; either\n+ * version 2 of the License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public\n+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */\n+#define SIMD_OPRSZ_SHIFT 0\n+#define SIMD_OPRSZ_BITS 5\n+\n+#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)\n+#define SIMD_MAXSZ_BITS 5\n+\n+#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)\n+#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)\n+\n+/* Create a descriptor from components. */\n+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);\n+\n+/* Extract the operation size from a descriptor. */\n+static inline intptr_t simd_oprsz(uint32_t desc)\n+{\n+ return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;\n+}\n+\n+/* Extract the max vector size from a descriptor. */\n+static inline intptr_t simd_maxsz(uint32_t desc)\n+{\n+ return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;\n+}\n+\n+/* Extract the operation-specific data from a descriptor. */\n+static inline int32_t simd_data(uint32_t desc)\n+{\n+ return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);\n+}\ndiff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h\nnew file mode 100644\nindex 0000000000..affb7c2e89\n--- /dev/null\n+++ b/tcg/tcg-op-gvec.h\n@@ -0,0 +1,43 @@\n+/*\n+ * Generic vector operation expansion\n+ *\n+ * Copyright (c) 2017 Linaro\n+ *\n+ * This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU Lesser General Public\n+ * License as published by the Free Software Foundation; either\n+ * version 2 of the License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public\n+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+/*\n+ * \"Generic\" vectors. All operands are given as offsets from ENV,\n+ * and therefore cannot also be allocated via tcg_global_mem_new_*.\n+ * OPRSZ is the byte size of the vector upon which the operation is performed.\n+ * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.\n+ *\n+ * All sizes must be 8 or any multiple of 16.\n+ * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.\n+ * Operands may completely, but not partially, overlap.\n+ */\n+\n+/* Expand a call to a gvec-stype helper, with pointers to three vector\n+ operands, and a descriptor (see tcg-gvec-desc.h). */\n+typedef void (gen_helper_gvec_3)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);\n+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,\n+ uint32_t oprsz, uint32_t maxsz, uint32_t data,\n+ gen_helper_gvec_3 *fn);\n+\n+/* Similarly, passing an extra pointer (e.g. env or float_status). */\n+typedef void (gen_helper_gvec_3_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr,\n+ TCGv_ptr, TCGv_i32);\n+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,\n+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,\n+ uint32_t data, gen_helper_gvec_3_ptr *fn);\ndiff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c\nnew file mode 100644\nindex 0000000000..f48415020d\n--- /dev/null\n+++ b/tcg/tcg-op-gvec.c\n@@ -0,0 +1,93 @@\n+/*\n+ * Generic vector operation expansion\n+ *\n+ * Copyright (c) 2017 Linaro\n+ *\n+ * This library is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU Lesser General Public\n+ * License as published by the Free Software Foundation; either\n+ * version 2 of the License, or (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public\n+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu-common.h\"\n+#include \"tcg.h\"\n+#include \"tcg-op.h\"\n+#include \"tcg-op-gvec.h\"\n+#include \"tcg-gvec-desc.h\"\n+\n+\n+/* Create a descriptor from components. */\n+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)\n+{\n+ uint32_t desc = 0;\n+\n+ assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));\n+ assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));\n+ assert(data == sextract32(data, 0, SIMD_DATA_BITS));\n+\n+ oprsz = (oprsz / 8) - 1;\n+ maxsz = (maxsz / 8) - 1;\n+ desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);\n+ desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);\n+ desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);\n+\n+ return desc;\n+}\n+\n+/* Generate a call to a gvec-style helper with three vector operands. */\n+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,\n+ uint32_t oprsz, uint32_t maxsz, uint32_t data,\n+ gen_helper_gvec_3 *fn)\n+{\n+ TCGv_ptr a0, a1, a2;\n+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));\n+\n+ a0 = tcg_temp_new_ptr();\n+ a1 = tcg_temp_new_ptr();\n+ a2 = tcg_temp_new_ptr();\n+\n+ tcg_gen_addi_ptr(a0, tcg_ctx.tcg_env, dofs);\n+ tcg_gen_addi_ptr(a1, tcg_ctx.tcg_env, aofs);\n+ tcg_gen_addi_ptr(a2, tcg_ctx.tcg_env, bofs);\n+\n+ fn(a0, a1, a2, desc);\n+\n+ tcg_temp_free_ptr(a0);\n+ tcg_temp_free_ptr(a1);\n+ tcg_temp_free_ptr(a2);\n+ tcg_temp_free_i32(desc);\n+}\n+\n+/* Generate a call to a gvec-style helper with three vector operands\n+ and an extra pointer operand. */\n+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,\n+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,\n+ uint32_t data, gen_helper_gvec_3_ptr *fn)\n+{\n+ TCGv_ptr a0, a1, a2;\n+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));\n+\n+ a0 = tcg_temp_new_ptr();\n+ a1 = tcg_temp_new_ptr();\n+ a2 = tcg_temp_new_ptr();\n+\n+ tcg_gen_addi_ptr(a0, tcg_ctx.tcg_env, dofs);\n+ tcg_gen_addi_ptr(a1, tcg_ctx.tcg_env, aofs);\n+ tcg_gen_addi_ptr(a2, tcg_ctx.tcg_env, bofs);\n+\n+ fn(a0, a1, a2, ptr, desc);\n+\n+ tcg_temp_free_ptr(a0);\n+ tcg_temp_free_ptr(a1);\n+ tcg_temp_free_ptr(a2);\n+ tcg_temp_free_i32(desc);\n+}\n", "prefixes": [ "v2", "01/16" ] }