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GET /api/patches/812952/?format=api
{ "id": 812952, "url": "http://patchwork.ozlabs.org/api/patches/812952/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-4-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-4-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:00", "name": "[v2,03/16] tcg: Add operations for host vectors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "87650de10c3bfcc6f76aece8fda305862cad90b0", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-4-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812952/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812952/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"QmYHnxw2\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9Dg6f7pz9s7f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:27:15 +1000 (AEST)", "from localhost ([::1]:36889 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro1p-0002jo-Ur\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:27:14 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:37841)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro03-0001eZ-GY\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:24 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro01-0006zX-V2\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400", "from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34139)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro01-0006z1-OI\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:21 -0400", "by mail-pf0-x22a.google.com with SMTP id e1so19440286pfk.1\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:21 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.19\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=hFwvwZ150xcNrgqhl2aSty24LcbInIciYUKB6n8yIaE=;\n\tb=QmYHnxw2vKSdBablukeCFek7SOiDjmctIFo/k232MgR2NhNdd1QAtAL+5Fv1Tig3NX\n\tySUFTfffq+yl6kkibDZmF9r1z/j/c9v5FJ47amNQo3R45d4dRK5kmyh1Uhcjla9iKZ9v\n\t+1rCwC5hJXaNTdaNYP/xx97yVh9ZuhQ2em0fw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=hFwvwZ150xcNrgqhl2aSty24LcbInIciYUKB6n8yIaE=;\n\tb=g1WvVTp5pa86E9BgkRVX1EO3XLLLOC6P1TkPei1ifBvYz4OTzkxNljsoV6KhrBTYit\n\t4rW3ilOP6+dxEi+OQPnxL7viKExpsCCt0CcDBp6a8+cNxB/bl7F17wqGbuZ24bTQdG3z\n\tjVRs36Nr2y4aWIM+D/U+90B0Vj9yRryyCJslR/AiqLUfMhL2DCpG6bD3dbB4FC1/iv8R\n\tbiorrKi/abEWkEWQ56pKzY6YAkes7iGMCYlQyTYG6T+iwLESIQC3+E+nl0JMfwGC2kOh\n\trWCph4zXu4e0j9FqEFJwIr+4sZqCwIM9yZN/2Kgem++PePEEnZxw+sHW0xrdO1qSRoG6\n\tD4gw==", "X-Gm-Message-State": "AHPjjUjYUYLvb3xoaquPSFrux4x8hllDYJVWuB6MDyrJJw+RImbXeItZ\n\twKB2D0bkLvSGmIi5VZ6e5Q==", "X-Google-Smtp-Source": "ADKCNb7nTwmhxbdTdyiGRjDEYCkLKggWtUxIRelnNhYGLqu0Qxnf8sTbM3diQRxCwSvBhcFZ6Whl3Q==", "X-Received": "by 10.99.55.92 with SMTP id g28mr15461544pgn.59.1505233520511;\n\tTue, 12 Sep 2017 09:25:20 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:00 -0700", "Message-Id": "<20170912162513.21694-4-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22a", "Subject": "[Qemu-devel] [PATCH v2 03/16] tcg: Add operations for host vectors", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Nothing uses or implements them yet.\n\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/tcg-opc.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n tcg/tcg.h | 24 ++++++++++++++++\n 2 files changed, 113 insertions(+)", "diff": "diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h\nindex 956fb1e9f3..edfdbf8798 100644\n--- a/tcg/tcg-opc.h\n+++ b/tcg/tcg-opc.h\n@@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,\n \n #undef TLADDR_ARGS\n #undef DATA64_ARGS\n+\n+/* Host integer vector operations. */\n+/* These opcodes are required whenever the base vector size is enabled. */\n+\n+DEF(mov_v64, 1, 1, 0, TCG_OPF_NOT_PRESENT)\n+DEF(mov_v128, 1, 1, 0, TCG_OPF_NOT_PRESENT)\n+DEF(mov_v256, 1, 1, 0, TCG_OPF_NOT_PRESENT)\n+\n+DEF(movi_v64, 1, 0, 1, TCG_OPF_NOT_PRESENT)\n+DEF(movi_v128, 1, 0, 1, TCG_OPF_NOT_PRESENT)\n+DEF(movi_v256, 1, 0, 1, TCG_OPF_NOT_PRESENT)\n+\n+DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64))\n+DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128))\n+DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64))\n+DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128))\n+DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+\n+DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+\n+DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+\n+DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64))\n+\n+DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128))\n+\n+DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256))\n+\n+/* These opcodes are optional.\n+ All element counts must be supported if any are. */\n+\n+DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64))\n+DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128))\n+DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256))\n+\n+DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64))\n+DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128))\n+DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256))\n+\n+DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64))\n+DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128))\n+DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256))\n+\n+DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))\n+DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))\n+DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64))\n+\n+DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))\n+DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))\n+DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))\n+DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128))\n+\n+DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))\n+DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))\n+DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))\n+DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256))\n+\n #undef IMPL\n #undef IMPL64\n #undef DEF\ndiff --git a/tcg/tcg.h b/tcg/tcg.h\nindex f56ddac31d..69b1fdf457 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet;\n #define TCG_TARGET_HAS_rem_i64 0\n #endif\n \n+#ifndef TCG_TARGET_HAS_v64\n+#define TCG_TARGET_HAS_v64 0\n+#define TCG_TARGET_HAS_andc_v64 0\n+#define TCG_TARGET_HAS_orc_v64 0\n+#define TCG_TARGET_HAS_not_v64 0\n+#define TCG_TARGET_HAS_neg_v64 0\n+#endif\n+\n+#ifndef TCG_TARGET_HAS_v128\n+#define TCG_TARGET_HAS_v128 0\n+#define TCG_TARGET_HAS_andc_v128 0\n+#define TCG_TARGET_HAS_orc_v128 0\n+#define TCG_TARGET_HAS_not_v128 0\n+#define TCG_TARGET_HAS_neg_v128 0\n+#endif\n+\n+#ifndef TCG_TARGET_HAS_v256\n+#define TCG_TARGET_HAS_v256 0\n+#define TCG_TARGET_HAS_andc_v256 0\n+#define TCG_TARGET_HAS_orc_v256 0\n+#define TCG_TARGET_HAS_not_v256 0\n+#define TCG_TARGET_HAS_neg_v256 0\n+#endif\n+\n /* For 32-bit targets, some sort of unsigned widening multiply is required. */\n #if TCG_TARGET_REG_BITS == 32 \\\n && !(defined(TCG_TARGET_HAS_mulu2_i32) \\\n", "prefixes": [ "v2", "03/16" ] }