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GET /api/patches/812951/?format=api
{ "id": 812951, "url": "http://patchwork.ozlabs.org/api/patches/812951/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-5-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912162513.21694-5-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-12T16:25:01", "name": "[v2,04/16] tcg: Add tcg_op_supported", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "56448678046f56928eac9877984a114d0017a3f1", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170912162513.21694-5-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2737, "url": "http://patchwork.ozlabs.org/api/series/2737/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2737", "date": "2017-09-12T16:24:59", "name": "TCG vectorization and example conversion", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2737/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812951/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"i/Azo3o3\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs9CS4ctcz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:26:12 +1000 (AEST)", "from localhost ([::1]:36888 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dro0o-0001ja-9k\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 12:26:10 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:37874)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro04-0001fZ-UT\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:26 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dro03-00070j-Aw\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:24 -0400", "from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:38130)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dro03-00070N-2L\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400", "by mail-pg0-x234.google.com with SMTP id v66so22136170pgb.5\n\tfor <qemu-devel@nongnu.org>; Tue, 12 Sep 2017 09:25:22 -0700 (PDT)", "from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tb22sm20382140pfh.175.2017.09.12.09.25.20\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 12 Sep 2017 09:25:20 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=PnAT61m2N68XoZU07wnZwsQqcSEtTH2DUqpYvvslqIc=;\n\tb=i/Azo3o33e8UzvtzHuHU/exizqpoB3C6ZDQTupXiMVMmUmmLLql8LP6jL5GCRLmaXq\n\t1ujOKkX/O4gyNRsc3GlKRopYIKE0SRcZfOt+vzffBgPDCcEzgC/dqRrMQYYefMYLgCbQ\n\tickjM61LDcMGMjy3dKkWEQAoILCmh2tNq9rGY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=PnAT61m2N68XoZU07wnZwsQqcSEtTH2DUqpYvvslqIc=;\n\tb=FiZzzi5frXkuOHwPJqJYu7TY/hWoTkcZ9jNhcpX/z26peaiORCLUWG40FTwjc8pcym\n\tIKMRnSDa0A/VQBQjHsI9DzN+hMx/3PimqUAikgYCAYfpfE07eLvNvx70c4iq0r/ZhDce\n\tDHx8tIKm8gdqLYGAddWuVd1VVXroSNRPcqkUy4X8HDQPRNKOXgJ2e47jn6UrJo9Qj+iU\n\txrRM4o/yY58af+tQOkw4z8U4TlWYrNbRznGwLGturVl4P1DyzMDMa5IzjHG/jAyybiEj\n\tGpNYZqd8vpbaKxwv37tuSIik2RmrpNjxlXZjd2V2PTAucuCSclepnrENvnkipv7aCEu0\n\tlMdQ==", "X-Gm-Message-State": "AHPjjUgeLNwq1XcRZZLg+EUIivW5OQK7DwMmAOz6zkBqobngNfHOnQD8\n\tMLhKDQwCiTGZZQVx2xxVxg==", "X-Google-Smtp-Source": "ADKCNb4EyuJirFjpywlDBnlzEKvVCrzAeIvogxcjOHA2zgpv22baCfDMPDVTjDfrixmdUCnwXqhhZw==", "X-Received": "by 10.98.178.133 with SMTP id z5mr15825173pfl.312.1505233521817; \n\tTue, 12 Sep 2017 09:25:21 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 09:25:01 -0700", "Message-Id": "<20170912162513.21694-5-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170912162513.21694-1-richard.henderson@linaro.org>", "References": "<20170912162513.21694-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::234", "Subject": "[Qemu-devel] [PATCH v2 04/16] tcg: Add tcg_op_supported", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "alex.bennee@linaro.org, f4bug@amsat.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/tcg.h | 2 +\n tcg/tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 312 insertions(+)", "diff": "diff --git a/tcg/tcg.h b/tcg/tcg.h\nindex 69b1fdf457..b81c67a754 100644\n--- a/tcg/tcg.h\n+++ b/tcg/tcg.h\n@@ -961,6 +961,8 @@ do {\\\n #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))\n #endif\n \n+bool tcg_op_supported(TCGOpcode op);\n+\n void tcg_gen_callN(TCGContext *s, void *func,\n TCGArg ret, int nargs, TCGArg *args);\n \ndiff --git a/tcg/tcg.c b/tcg/tcg.c\nindex bc65d01618..9aea00d9b4 100644\n--- a/tcg/tcg.c\n+++ b/tcg/tcg.c\n@@ -749,6 +749,316 @@ int tcg_check_temp_count(void)\n }\n #endif\n \n+/* Return true if OP may appear in the opcode stream.\n+ Test the runtime variable that controls each opcode. */\n+bool tcg_op_supported(TCGOpcode op)\n+{\n+ switch (op) {\n+ case INDEX_op_discard:\n+ case INDEX_op_set_label:\n+ case INDEX_op_call:\n+ case INDEX_op_br:\n+ case INDEX_op_mb:\n+ case INDEX_op_insn_start:\n+ case INDEX_op_exit_tb:\n+ case INDEX_op_goto_tb:\n+ case INDEX_op_qemu_ld_i32:\n+ case INDEX_op_qemu_st_i32:\n+ case INDEX_op_qemu_ld_i64:\n+ case INDEX_op_qemu_st_i64:\n+ return true;\n+\n+ case INDEX_op_goto_ptr:\n+ return TCG_TARGET_HAS_goto_ptr;\n+\n+ case INDEX_op_mov_i32:\n+ case INDEX_op_movi_i32:\n+ case INDEX_op_setcond_i32:\n+ case INDEX_op_brcond_i32:\n+ case INDEX_op_ld8u_i32:\n+ case INDEX_op_ld8s_i32:\n+ case INDEX_op_ld16u_i32:\n+ case INDEX_op_ld16s_i32:\n+ case INDEX_op_ld_i32:\n+ case INDEX_op_st8_i32:\n+ case INDEX_op_st16_i32:\n+ case INDEX_op_st_i32:\n+ case INDEX_op_add_i32:\n+ case INDEX_op_sub_i32:\n+ case INDEX_op_mul_i32:\n+ case INDEX_op_and_i32:\n+ case INDEX_op_or_i32:\n+ case INDEX_op_xor_i32:\n+ case INDEX_op_shl_i32:\n+ case INDEX_op_shr_i32:\n+ case INDEX_op_sar_i32:\n+ return true;\n+\n+ case INDEX_op_movcond_i32:\n+ return TCG_TARGET_HAS_movcond_i32;\n+ case INDEX_op_div_i32:\n+ case INDEX_op_divu_i32:\n+ return TCG_TARGET_HAS_div_i32;\n+ case INDEX_op_rem_i32:\n+ case INDEX_op_remu_i32:\n+ return TCG_TARGET_HAS_rem_i32;\n+ case INDEX_op_div2_i32:\n+ case INDEX_op_divu2_i32:\n+ return TCG_TARGET_HAS_div2_i32;\n+ case INDEX_op_rotl_i32:\n+ case INDEX_op_rotr_i32:\n+ return TCG_TARGET_HAS_rot_i32;\n+ case INDEX_op_deposit_i32:\n+ return TCG_TARGET_HAS_deposit_i32;\n+ case INDEX_op_extract_i32:\n+ return TCG_TARGET_HAS_extract_i32;\n+ case INDEX_op_sextract_i32:\n+ return TCG_TARGET_HAS_sextract_i32;\n+ case INDEX_op_add2_i32:\n+ return TCG_TARGET_HAS_add2_i32;\n+ case INDEX_op_sub2_i32:\n+ return TCG_TARGET_HAS_sub2_i32;\n+ case INDEX_op_mulu2_i32:\n+ return TCG_TARGET_HAS_mulu2_i32;\n+ case INDEX_op_muls2_i32:\n+ return TCG_TARGET_HAS_muls2_i32;\n+ case INDEX_op_muluh_i32:\n+ return TCG_TARGET_HAS_muluh_i32;\n+ case INDEX_op_mulsh_i32:\n+ return TCG_TARGET_HAS_mulsh_i32;\n+ case INDEX_op_ext8s_i32:\n+ return TCG_TARGET_HAS_ext8s_i32;\n+ case INDEX_op_ext16s_i32:\n+ return TCG_TARGET_HAS_ext16s_i32;\n+ case INDEX_op_ext8u_i32:\n+ return TCG_TARGET_HAS_ext8u_i32;\n+ case INDEX_op_ext16u_i32:\n+ return TCG_TARGET_HAS_ext16u_i32;\n+ case INDEX_op_bswap16_i32:\n+ return TCG_TARGET_HAS_bswap16_i32;\n+ case INDEX_op_bswap32_i32:\n+ return TCG_TARGET_HAS_bswap32_i32;\n+ case INDEX_op_not_i32:\n+ return TCG_TARGET_HAS_not_i32;\n+ case INDEX_op_neg_i32:\n+ return TCG_TARGET_HAS_neg_i32;\n+ case INDEX_op_andc_i32:\n+ return TCG_TARGET_HAS_andc_i32;\n+ case INDEX_op_orc_i32:\n+ return TCG_TARGET_HAS_orc_i32;\n+ case INDEX_op_eqv_i32:\n+ return TCG_TARGET_HAS_eqv_i32;\n+ case INDEX_op_nand_i32:\n+ return TCG_TARGET_HAS_nand_i32;\n+ case INDEX_op_nor_i32:\n+ return TCG_TARGET_HAS_nor_i32;\n+ case INDEX_op_clz_i32:\n+ return TCG_TARGET_HAS_clz_i32;\n+ case INDEX_op_ctz_i32:\n+ return TCG_TARGET_HAS_ctz_i32;\n+ case INDEX_op_ctpop_i32:\n+ return TCG_TARGET_HAS_ctpop_i32;\n+\n+ case INDEX_op_brcond2_i32:\n+ case INDEX_op_setcond2_i32:\n+ return TCG_TARGET_REG_BITS == 32;\n+\n+ case INDEX_op_mov_i64:\n+ case INDEX_op_movi_i64:\n+ case INDEX_op_setcond_i64:\n+ case INDEX_op_brcond_i64:\n+ case INDEX_op_ld8u_i64:\n+ case INDEX_op_ld8s_i64:\n+ case INDEX_op_ld16u_i64:\n+ case INDEX_op_ld16s_i64:\n+ case INDEX_op_ld32u_i64:\n+ case INDEX_op_ld32s_i64:\n+ case INDEX_op_ld_i64:\n+ case INDEX_op_st8_i64:\n+ case INDEX_op_st16_i64:\n+ case INDEX_op_st32_i64:\n+ case INDEX_op_st_i64:\n+ case INDEX_op_add_i64:\n+ case INDEX_op_sub_i64:\n+ case INDEX_op_mul_i64:\n+ case INDEX_op_and_i64:\n+ case INDEX_op_or_i64:\n+ case INDEX_op_xor_i64:\n+ case INDEX_op_shl_i64:\n+ case INDEX_op_shr_i64:\n+ case INDEX_op_sar_i64:\n+ case INDEX_op_ext_i32_i64:\n+ case INDEX_op_extu_i32_i64:\n+ return TCG_TARGET_REG_BITS == 64;\n+\n+ case INDEX_op_movcond_i64:\n+ return TCG_TARGET_HAS_movcond_i64;\n+ case INDEX_op_div_i64:\n+ case INDEX_op_divu_i64:\n+ return TCG_TARGET_HAS_div_i64;\n+ case INDEX_op_rem_i64:\n+ case INDEX_op_remu_i64:\n+ return TCG_TARGET_HAS_rem_i64;\n+ case INDEX_op_div2_i64:\n+ case INDEX_op_divu2_i64:\n+ return TCG_TARGET_HAS_div2_i64;\n+ case INDEX_op_rotl_i64:\n+ case INDEX_op_rotr_i64:\n+ return TCG_TARGET_HAS_rot_i64;\n+ case INDEX_op_deposit_i64:\n+ return TCG_TARGET_HAS_deposit_i64;\n+ case INDEX_op_extract_i64:\n+ return TCG_TARGET_HAS_extract_i64;\n+ case INDEX_op_sextract_i64:\n+ return TCG_TARGET_HAS_sextract_i64;\n+ case INDEX_op_extrl_i64_i32:\n+ return TCG_TARGET_HAS_extrl_i64_i32;\n+ case INDEX_op_extrh_i64_i32:\n+ return TCG_TARGET_HAS_extrh_i64_i32;\n+ case INDEX_op_ext8s_i64:\n+ return TCG_TARGET_HAS_ext8s_i64;\n+ case INDEX_op_ext16s_i64:\n+ return TCG_TARGET_HAS_ext16s_i64;\n+ case INDEX_op_ext32s_i64:\n+ return TCG_TARGET_HAS_ext32s_i64;\n+ case INDEX_op_ext8u_i64:\n+ return TCG_TARGET_HAS_ext8u_i64;\n+ case INDEX_op_ext16u_i64:\n+ return TCG_TARGET_HAS_ext16u_i64;\n+ case INDEX_op_ext32u_i64:\n+ return TCG_TARGET_HAS_ext32u_i64;\n+ case INDEX_op_bswap16_i64:\n+ return TCG_TARGET_HAS_bswap16_i64;\n+ case INDEX_op_bswap32_i64:\n+ return TCG_TARGET_HAS_bswap32_i64;\n+ case INDEX_op_bswap64_i64:\n+ return TCG_TARGET_HAS_bswap64_i64;\n+ case INDEX_op_not_i64:\n+ return TCG_TARGET_HAS_not_i64;\n+ case INDEX_op_neg_i64:\n+ return TCG_TARGET_HAS_neg_i64;\n+ case INDEX_op_andc_i64:\n+ return TCG_TARGET_HAS_andc_i64;\n+ case INDEX_op_orc_i64:\n+ return TCG_TARGET_HAS_orc_i64;\n+ case INDEX_op_eqv_i64:\n+ return TCG_TARGET_HAS_eqv_i64;\n+ case INDEX_op_nand_i64:\n+ return TCG_TARGET_HAS_nand_i64;\n+ case INDEX_op_nor_i64:\n+ return TCG_TARGET_HAS_nor_i64;\n+ case INDEX_op_clz_i64:\n+ return TCG_TARGET_HAS_clz_i64;\n+ case INDEX_op_ctz_i64:\n+ return TCG_TARGET_HAS_ctz_i64;\n+ case INDEX_op_ctpop_i64:\n+ return TCG_TARGET_HAS_ctpop_i64;\n+ case INDEX_op_add2_i64:\n+ return TCG_TARGET_HAS_add2_i64;\n+ case INDEX_op_sub2_i64:\n+ return TCG_TARGET_HAS_sub2_i64;\n+ case INDEX_op_mulu2_i64:\n+ return TCG_TARGET_HAS_mulu2_i64;\n+ case INDEX_op_muls2_i64:\n+ return TCG_TARGET_HAS_muls2_i64;\n+ case INDEX_op_muluh_i64:\n+ return TCG_TARGET_HAS_muluh_i64;\n+ case INDEX_op_mulsh_i64:\n+ return TCG_TARGET_HAS_mulsh_i64;\n+\n+ case INDEX_op_mov_v64:\n+ case INDEX_op_movi_v64:\n+ case INDEX_op_ld_v64:\n+ case INDEX_op_st_v64:\n+ case INDEX_op_and_v64:\n+ case INDEX_op_or_v64:\n+ case INDEX_op_xor_v64:\n+ case INDEX_op_add8_v64:\n+ case INDEX_op_add16_v64:\n+ case INDEX_op_add32_v64:\n+ case INDEX_op_sub8_v64:\n+ case INDEX_op_sub16_v64:\n+ case INDEX_op_sub32_v64:\n+ return TCG_TARGET_HAS_v64;\n+\n+ case INDEX_op_mov_v128:\n+ case INDEX_op_movi_v128:\n+ case INDEX_op_ld_v128:\n+ case INDEX_op_st_v128:\n+ case INDEX_op_and_v128:\n+ case INDEX_op_or_v128:\n+ case INDEX_op_xor_v128:\n+ case INDEX_op_add8_v128:\n+ case INDEX_op_add16_v128:\n+ case INDEX_op_add32_v128:\n+ case INDEX_op_add64_v128:\n+ case INDEX_op_sub8_v128:\n+ case INDEX_op_sub16_v128:\n+ case INDEX_op_sub32_v128:\n+ case INDEX_op_sub64_v128:\n+ return TCG_TARGET_HAS_v128;\n+\n+ case INDEX_op_mov_v256:\n+ case INDEX_op_movi_v256:\n+ case INDEX_op_ld_v256:\n+ case INDEX_op_st_v256:\n+ case INDEX_op_and_v256:\n+ case INDEX_op_or_v256:\n+ case INDEX_op_xor_v256:\n+ case INDEX_op_add8_v256:\n+ case INDEX_op_add16_v256:\n+ case INDEX_op_add32_v256:\n+ case INDEX_op_add64_v256:\n+ case INDEX_op_sub8_v256:\n+ case INDEX_op_sub16_v256:\n+ case INDEX_op_sub32_v256:\n+ case INDEX_op_sub64_v256:\n+ return TCG_TARGET_HAS_v256;\n+\n+ case INDEX_op_not_v64:\n+ return TCG_TARGET_HAS_not_v64;\n+ case INDEX_op_not_v128:\n+ return TCG_TARGET_HAS_not_v128;\n+ case INDEX_op_not_v256:\n+ return TCG_TARGET_HAS_not_v256;\n+\n+ case INDEX_op_andc_v64:\n+ return TCG_TARGET_HAS_andc_v64;\n+ case INDEX_op_andc_v128:\n+ return TCG_TARGET_HAS_andc_v128;\n+ case INDEX_op_andc_v256:\n+ return TCG_TARGET_HAS_andc_v256;\n+\n+ case INDEX_op_orc_v64:\n+ return TCG_TARGET_HAS_orc_v64;\n+ case INDEX_op_orc_v128:\n+ return TCG_TARGET_HAS_orc_v128;\n+ case INDEX_op_orc_v256:\n+ return TCG_TARGET_HAS_orc_v256;\n+\n+ case INDEX_op_neg8_v64:\n+ case INDEX_op_neg16_v64:\n+ case INDEX_op_neg32_v64:\n+ return TCG_TARGET_HAS_neg_v64;\n+\n+ case INDEX_op_neg8_v128:\n+ case INDEX_op_neg16_v128:\n+ case INDEX_op_neg32_v128:\n+ case INDEX_op_neg64_v128:\n+ return TCG_TARGET_HAS_neg_v128;\n+\n+ case INDEX_op_neg8_v256:\n+ case INDEX_op_neg16_v256:\n+ case INDEX_op_neg32_v256:\n+ case INDEX_op_neg64_v256:\n+ return TCG_TARGET_HAS_neg_v256;\n+\n+ case NB_OPS:\n+ break;\n+ }\n+ g_assert_not_reached();\n+}\n+\n /* Note: we convert the 64 bit args to 32 bit and do some alignment\n and endian swap. Maybe it would be better to do the alignment\n and endian swap in tcg_reg_alloc_call(). */\n", "prefixes": [ "v2", "04/16" ] }