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GET /api/patches/812876/?format=api
{ "id": 812876, "url": "http://patchwork.ozlabs.org/api/patches/812876/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/1505227001.14827.151.camel@brimstone.rchland.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505227001.14827.151.camel@brimstone.rchland.ibm.com>", "list_archive_url": null, "date": "2017-09-12T14:36:41", "name": "[rs6000] testcase coverage for vector load builtins", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "df73681e140d035d7b0180abb0081083e7fb5411", "submitter": { "id": 3241, "url": "http://patchwork.ozlabs.org/api/people/3241/?format=api", "name": "will schmidt", "email": "will_schmidt@vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/1505227001.14827.151.camel@brimstone.rchland.ibm.com/mbox/", "series": [ { "id": 2718, "url": "http://patchwork.ozlabs.org/api/series/2718/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=2718", "date": "2017-09-12T14:36:41", "name": "[rs6000] testcase coverage for vector load builtins", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2718/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812876/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812876/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461934-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461934-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"cjV/vOIx\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs6p13Ggvz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 00:37:28 +1000 (AEST)", "(qmail 100960 invoked by alias); 12 Sep 2017 14:37:20 -0000", "(qmail 100948 invoked by uid 89); 12 Sep 2017 14:37:19 -0000", "from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.158.5) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 12 Sep 2017 14:37:17 +0000", "from pps.filterd (m0098416.ppops.net [127.0.0.1])\tby\n\tmx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8CEbBnZ009823\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 12 Sep 2017 10:37:15 -0400", "from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151])\tby\n\tmx0b-001b2d01.pphosted.com with ESMTP id\n\t2cxgyd24r8-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor <gcc-patches@gcc.gnu.org>;\n\tTue, 12 Sep 2017 10:37:11 -0400", "from localhost\tby e33.co.us.ibm.com with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted\tfor\n\t<gcc-patches@gcc.gnu.org> from <will_schmidt@vnet.ibm.com>;\n\tTue, 12 Sep 2017 08:36:43 -0600", "from b03cxnp07029.gho.boulder.ibm.com (9.17.130.16)\tby\n\te33.co.us.ibm.com (192.168.1.133) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted;\n\tTue, 12 Sep 2017 08:36:42 -0600", "from b03ledav005.gho.boulder.ibm.com\n\t(b03ledav005.gho.boulder.ibm.com [9.17.130.236])\tby\n\tb03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0)\n\twith ESMTP id v8CEagFm7602508; Tue, 12 Sep 2017 07:36:42 -0700", "from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1])\tby\n\tIMSVA (Postfix) with ESMTP id 2D7EEBE039;\n\tTue, 12 Sep 2017 08:36:42 -0600 (MDT)", "from [9.10.86.107] (unknown [9.10.86.107])\tby\n\tb03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP id\n\tC601DBE03A; Tue, 12 Sep 2017 08:36:41 -0600 (MDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:reply-to:to:cc:content-type:date:mime-version\n\t:content-transfer-encoding:message-id; q=dns; s=default; b=QZOGO\n\tkEunSLdCx3GeGSCYpkfxVYPjqvw/hgdXwiWGMl11mFbhUTzdOqs/vQIIJ6Hk1dse\n\tHR1rT2H0Gb+p/pjHfOztptqHtmYHOAS/m/2jpv+fSPIAlMLWkKE+M9MAFg9qzFwY\n\t93lDHFDJ2g8aBrRZFouqLSI+n6WeQMuWvUaFuA=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:reply-to:to:cc:content-type:date:mime-version\n\t:content-transfer-encoding:message-id; s=default; bh=YUovvryQWwx\n\tqJl3vDYsvHdlgV5U=; b=cjV/vOIxlNFzS1Y9Q5AUbX86hcTFki23c9aJihF9tAF\n\tcGrIg8c64BnKJQsWuTom1tUeUvxVaogyguZ1tRiKSDeK/YCRdmQ9d9JR1BSv4gpX\n\t9l4vvF2PTa823NjApSUr2mo3JaVKkpTiu4TmgZVFUI9f7FRTRp/INKs+Bf5VHlnE\n\t=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.5 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_LOW,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "mx0a-001b2d01.pphosted.com", "Subject": "[PATCH, rs6000] testcase coverage for vector load builtins", "From": "Will Schmidt <will_schmidt@vnet.ibm.com>", "Reply-To": "will_schmidt@vnet.ibm.com", "To": "GCC Patches <gcc-patches@gcc.gnu.org>", "Cc": "Segher Boessenkool <segher@kernel.crashing.org>,\n\tBill Schmidt <wschmidt@linux.vnet.ibm.com>,\n\tDavid Edelsohn <dje.gcc@gmail.com>", "Content-Type": "text/plain; charset=\"UTF-8\"", "Date": "Tue, 12 Sep 2017 09:36:41 -0500", "Mime-Version": "1.0", "Content-Transfer-Encoding": "7bit", "X-TM-AS-GCONF": "00", "x-cbid": "17091214-0008-0000-0000-0000088F55B5", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007711; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000227; SDB=6.00915975; UDB=6.00459923;\n\tIPR=6.00696207; BA=6.00005587; NDR=6.00000001; ZLA=6.00000005;\n\tZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000;\n\tZU=6.00000002; MB=3.00017126; XFM=3.00000015;\n\tUTC=2017-09-12 14:36:43", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17091214-0009-0000-0000-000043F162DC", "Message-Id": "<1505227001.14827.151.camel@brimstone.rchland.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-12_04:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0 malwarescore=0 phishscore=0\n\tadultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx\n\tscancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709120204", "X-IsSubscribed": "yes" }, "content": "Hi, \n\n[PATCH, rs6000] testcase coverage for vector load builtins\nAdd testcase coverage for the vec_ld intrinsic builtins.\n\nTested across power platforms (p6 and newer). OK for trunk?\n\nThanks,\n-Will\n\n[gcc/testsuite]\n \n2017-09-12 Will Schmidt <will_schmidt@vnet.ibm.com>\n\n\t* gcc.target/powerpc/fold-vec-ld-char.c: New.\n\t* gcc.target/powerpc/fold-vec-ld-double.c: New.\n\t* gcc.target/powerpc/fold-vec-ld-float.c: New.\n\t* gcc.target/powerpc/fold-vec-ld-int.c: New.\n\t* gcc.target/powerpc/fold-vec-ld-longlong.c: New.\n\t* gcc.target/powerpc/fold-vec-ld-short.c: New.\n\n+", "diff": "diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c\nnew file mode 100644\nindex 0000000..f9ef3e0\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-char.c\n@@ -0,0 +1,71 @@\n+/* Verify that overloaded built-ins for vec_ld* with char\n+ inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_altivec_ok } */\n+/* { dg-options \"-maltivec -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector signed char\n+testld_sc_vsc (long long ll1, vector signed char vsc2)\n+{\n+ return vec_ld (ll1, &vsc2);\n+}\n+\n+vector signed char\n+testld_sc_sc (long long ll1, signed char sc)\n+{\n+ return vec_ld (ll1, &sc);\n+}\n+\n+vector unsigned char\n+testld_uc_vuc (long long ll1, vector unsigned char vuc2)\n+{\n+ return vec_ld (ll1, &vuc2);\n+}\n+\n+vector unsigned char\n+testld_uc_uc (long long ll1, unsigned char uc)\n+{\n+ return vec_ld (ll1, &uc);\n+}\n+\n+vector bool char\n+testld_bc_vbc (long long ll1, vector bool char vbc2)\n+{\n+ return vec_ld (ll1, &vbc2);\n+}\n+\n+vector signed char\n+testld_cst_vsc (vector signed char vsc2)\n+{\n+ return vec_ld (16, &vsc2);\n+}\n+\n+vector signed char\n+testld_cst_sc (signed char sc)\n+{\n+ return vec_ld (32, &sc);\n+}\n+\n+vector unsigned char\n+testld_cst_vuc (vector unsigned char vuc2)\n+{\n+ return vec_ld (48, &vuc2);\n+}\n+\n+vector unsigned char\n+testld_cst_uc (unsigned char uc)\n+{\n+ return vec_ld (64, &uc);\n+}\n+\n+vector bool char\n+testld_cst_vbc (vector bool char vbc2)\n+{\n+ return vec_ld (80, &vbc2);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M|\\mlxvw4x\\M}\n10 } } */\n+\ndiff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c\nnew file mode 100644\nindex 0000000..9c6fbb2\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-double.c\n@@ -0,0 +1,22 @@\n+/* Verify that overloaded built-ins for vec_ld with \n+ double inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_vsx_ok } */\n+/* { dg-options \"-mvsx -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector double\n+testld_ll_vd (long long ll1, vector double vd)\n+{\n+ return vec_ld (ll1, &vd);\n+}\n+\n+vector double\n+testld_cst_vd (long long ll1, vector double vd)\n+{\n+ return vec_ld (16, &vd);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M} 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c\nnew file mode 100644\nindex 0000000..eca847a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-float.c\n@@ -0,0 +1,37 @@\n+/* Verify that overloaded built-ins for vec_ld with float\n+ inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_altivec_ok } */\n+/* { dg-options \"-maltivec -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector float\n+testld_ll_vf (long long ll1, vector float vf2)\n+{\n+ return vec_ld (ll1, &vf2);\n+}\n+\n+vector float\n+testld_ll_f (long long ll1, float f2)\n+{\n+ return vec_ld (ll1, &f2);\n+}\n+\n+vector float\n+testld_cst_vf (vector float vf2)\n+{\n+ return vec_ld (16, &vf2);\n+}\n+\n+vector float\n+testld_cst_f (float f2)\n+{\n+ return vec_ld (16, &f2);\n+}\n+\n+// lvx - generated by ll_vf and ll_f\n+// lxvd2x - generated by cst_vf and cst_f\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M} 4 } } */\n+\ndiff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c\nnew file mode 100644\nindex 0000000..5dc6df6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-int.c\n@@ -0,0 +1,71 @@\n+/* Verify that overloaded built-ins for vec_ld* with int\n+ inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_altivec_ok } */\n+/* { dg-options \"-maltivec -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector signed int\n+testld_vsi_vsi (long long ll1, vector signed int vsi2)\n+{\n+ return vec_ld (ll1, &vsi2);\n+}\n+\n+vector signed int\n+testld_vsi_si (long long ll1, signed int si)\n+{\n+ return vec_ld (ll1, &si);\n+}\n+\n+vector unsigned int\n+testld_vui_vui (long long ll1, vector unsigned int vui2)\n+{\n+ return vec_ld (ll1, &vui2);\n+}\n+\n+vector unsigned int\n+testld_vui_ui (long long ll1, unsigned int ui)\n+{\n+ return vec_ld (ll1, &ui);\n+}\n+\n+vector bool int\n+testld_vbi_vbi (long long ll1, vector bool int vbi2)\n+{\n+ return vec_ld (ll1, &vbi2);\n+}\n+\n+vector signed int\n+testld_cst_vsi (vector signed int vsi2)\n+{\n+ return vec_ld (16, &vsi2);\n+}\n+\n+vector signed int\n+testld_cst_si (signed int si)\n+{\n+ return vec_ld (32, &si);\n+}\n+\n+vector unsigned int\n+testld_cst_vui (vector unsigned int vui2)\n+{\n+ return vec_ld (48, &vui2);\n+}\n+\n+vector unsigned int\n+testld_cst_ui (unsigned int ui)\n+{\n+ return vec_ld (64, &ui);\n+}\n+\n+vector bool int\n+testld_cst_vbi (vector bool int vbi2)\n+{\n+ return vec_ld (80, &vbi2);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M|\\mlxvw4x\\M}\n10 } } */\n+\ndiff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c\nnew file mode 100644\nindex 0000000..37941af\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c\n@@ -0,0 +1,47 @@\n+/* Verify that overloaded built-ins for vec_ld* with long long\n+ inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_p8vector_ok } */\n+/* { dg-options \"-mpower8-vector -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector signed long long\n+testld_vsl_vsl (long long ll1, vector signed long vsl2)\n+{\n+ return vec_ld (ll1, &vsl2);\n+}\n+\n+vector unsigned long long\n+testld_vul_vul (long long ll1, vector unsigned long vul2)\n+{\n+ return vec_ld (ll1, &vul2);\n+}\n+\n+vector bool long long\n+testld_vbl_vbl (long long ll1, vector bool long vbl2)\n+{\n+ return vec_ld (ll1, &vbl2);\n+}\n+\n+vector signed long long\n+testld_cst_vsl (vector signed long vsl2)\n+{\n+ return vec_ld (16, &vsl2);\n+}\n+\n+vector unsigned long long\n+testld_cst_vul (vector unsigned long vul2)\n+{\n+ return vec_ld (32, &vul2);\n+}\n+\n+vector bool long long\n+testld_cst_vbl (vector bool long vbl2)\n+{\n+ return vec_ld (48, &vbl2);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M} 6 } } */\n+\ndiff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c\nb/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c\nnew file mode 100644\nindex 0000000..5e42844\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-short.c\n@@ -0,0 +1,71 @@\n+/* Verify that overloaded built-ins for vec_ld* with short\n+ inputs produce the right code. */\n+\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_altivec_ok } */\n+/* { dg-options \"-maltivec -O2\" } */\n+\n+#include <altivec.h>\n+\n+vector signed short\n+testld_vss_vss (long long ll1, vector signed short vss2)\n+{\n+ return vec_ld (ll1, &vss2);\n+}\n+\n+vector signed short\n+testld_vss_ss (long long ll1, signed short ss)\n+{\n+ return vec_ld (ll1, &ss);\n+}\n+\n+vector unsigned short\n+testld_vus_vus (long long ll1, vector unsigned short vus2)\n+{\n+ return vec_ld (ll1, &vus2);\n+}\n+\n+vector unsigned short\n+testld_vus_us (long long ll1, unsigned short us)\n+{\n+ return vec_ld (ll1, &us);\n+}\n+\n+vector bool short\n+testld_vbs_vbs (long long ll1, vector bool short vbs2)\n+{\n+ return vec_ld (ll1, &vbs2);\n+}\n+\n+vector signed short\n+testld_cst_vss (vector signed short vss2)\n+{\n+ return vec_ld (16, &vss2);\n+}\n+\n+vector signed short\n+testld_cst_ss (signed short ss)\n+{\n+ return vec_ld (32, &ss);\n+}\n+\n+vector unsigned short\n+testld_cst_vus (vector unsigned short vus2)\n+{\n+ return vec_ld (48, &vus2);\n+}\n+\n+vector unsigned short\n+testld_cst_us (unsigned short us)\n+{\n+ return vec_ld (64, &us);\n+}\n+\n+vector bool short\n+testld_cst_vbs (vector bool short vbs2)\n+{\n+ return vec_ld (80, &vbs2);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlvx\\M|\\mlxvd2x\\M|\\mlxvw4x\\M}\n10 } } */\n", "prefixes": [ "rs6000" ] }