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GET /api/patches/812721/?format=api
{ "id": 812721, "url": "http://patchwork.ozlabs.org/api/patches/812721/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-3-git-send-email-charles.baylis@linaro.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505205277-26276-3-git-send-email-charles.baylis@linaro.org>", "list_archive_url": null, "date": "2017-09-12T08:34:36", "name": "[2/3,ARM] Refactor costs calculation for MEM.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "91e0c1f9a03da82700a73c57e7c69c67d4213763", "submitter": { "id": 35578, "url": "http://patchwork.ozlabs.org/api/people/35578/?format=api", "name": "Charles Baylis", "email": "charles.baylis@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/1505205277-26276-3-git-send-email-charles.baylis@linaro.org/mbox/", "series": [ { "id": 2631, "url": "http://patchwork.ozlabs.org/api/series/2631/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=2631", "date": "2017-09-12T08:34:34", "name": "Addressing mode costs v3", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2631/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812721/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812721/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461894-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461894-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"odlYAySN\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrymX10kwz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 18:35:39 +1000 (AEST)", "(qmail 76004 invoked by alias); 12 Sep 2017 08:35:01 -0000", "(qmail 75867 invoked by uid 89); 12 Sep 2017 08:35:01 -0000", "from mail-wr0-f170.google.com (HELO mail-wr0-f170.google.com)\n\t(209.85.128.170) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 12 Sep 2017 08:34:58 +0000", "by mail-wr0-f170.google.com with SMTP id v109so19072088wrc.1 for\n\t<gcc-patches@gcc.gnu.org>; Tue, 12 Sep 2017 01:34:58 -0700 (PDT)", "from localhost.localdomain\n\t(cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net.\n\t[86.26.39.137]) by smtp.gmail.com with ESMTPSA id\n\ts126sm13321227wmd.46.2017.09.12.01.34.55 (version=TLS1_2\n\tcipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 12 Sep 2017 01:34:56 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:cc:subject:date:message-id:in-reply-to:references; q=dns; s=\n\tdefault; b=okvKV9jR3JWdNA+GBNES/r0mRL9rCy6ggvQTcCOldGJ7N77aM87o1\n\tmWUAtPza4pRuqsxQ0/EtRKhc/kdA/f1JYsiQvvQ8lfmWJ3YAogbHTBU4x3b9phIt\n\teUQDESCUn/Xyj8ZryGWJ7cKvdIEuSneQXU4Unfm8m5X9Ve4RcGlvJY=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:cc:subject:date:message-id:in-reply-to:references; s=\n\tdefault; bh=Nr1Wh96q/z7rrs58aXGAYCH2r7s=; b=odlYAySN1xhLdjC9/Ab6\n\t1mWBA8t+E80lJsluIm+LlsVStYG+wIita0xEP0NIFumW5tvGrnUb12AZj03lvJWt\n\ttv9ogKxl1N48VEeafV6nQ2BRZWGoVnhXyjAlilbUhLrCkY5elITcw0CECDZwOoRT\n\tZSw5mN65OsmnkYLWxEZfJw4=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-25.1 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "mail-wr0-f170.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; bh=DQRhajOLkIRNno4LcKAYiHFaexKOXmrd9AacYrbw4zQ=;\n\tb=k3fmNDiQxEOe+R601rMC61elFcY7WZzVD4xIReeNX0vk5Gj/WkfL6mkuh9OShrYajf\n\tNU3G7heYuit3Axhd8JkC37OtBXFH0tGggDH7XkfKrX5BCV9wUiS9qB7u21huFVR0RbjH\n\tCgD+rnfrThF4tGxxzZevVxjqW15x4p9A0WROw/t4rznOaI1trNdQy1CiE1jpJSt4+Xwf\n\tOrU9q7JlrDmi/bCZ/UXFug+UEJ2A0oP46yRVpx4nIK+setxTz0blL3HjCOP9eRdqpKJX\n\t63lvX6h0LMs/6SofmEkIx6pTrsa1SziCxIRekgthrn5s7ZvKqp2pB+3htxYNUPJHuaDs\n\tvdUw==", "X-Gm-Message-State": "AHPjjUg3sauOPXcEeypvicK3d6wvLV/jiS7hoE9+mYL4qxS1Mj4o1wrZ\ttg7UPQJuA29c2E7e", "X-Google-Smtp-Source": "ADKCNb6e1ypQ8yq8YRKhKOSqgyeNA745rluQX7NLHKU4RX10kDEmyWE3PczWg3S1G+jONDVb6wSftg==", "X-Received": "by 10.223.135.97 with SMTP id 30mr9976757wrz.245.1505205296712;\n\tTue, 12 Sep 2017 01:34:56 -0700 (PDT)", "From": "charles.baylis@linaro.org", "To": "rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com,\n\tkyrylo.tkachov@arm.com", "Cc": "gcc-patches@gcc.gnu.org", "Subject": "[PATCH 2/3] [ARM] Refactor costs calculation for MEM.", "Date": "Tue, 12 Sep 2017 09:34:36 +0100", "Message-Id": "<1505205277-26276-3-git-send-email-charles.baylis@linaro.org>", "In-Reply-To": "<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>", "References": "<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>", "X-IsSubscribed": "yes" }, "content": "From: Charles Baylis <charles.baylis@linaro.org>\n\nThis patch moves the calculation of costs for MEM into a\nseparate function, and reforms the calculation into two\nparts. Firstly any additional cost of the addressing mode\nis calculated, and then the cost of the memory access itself\nis added.\n\nIn this patch, the calculation of the cost of the addressing\nmode is left as a placeholder, to be added in a subsequent\npatch.\n\ngcc/ChangeLog:\n\n<date> Charles Baylis <charles.baylis@linaro.org>\n\n\t* config/arm/arm.c (arm_mem_costs): New function.\n\t(arm_rtx_costs_internal): Use arm_mem_costs.\n\ngcc/testsuite/ChangeLog:\n\n<date> Charles Baylis <charles.baylis@linaro.org>\n\n\t* gcc.target/arm/addr-modes-float.c: New test.\n\t* gcc.target/arm/addr-modes-int.c: New test.\n\t* gcc.target/arm/addr-modes.h: New header.\n\nChange-Id: I99e93406ea39ee31f71c7bf428ad3e127b7a618e\n---\n gcc/config/arm/arm.c | 67 ++++++++++++++++---------\n gcc/testsuite/gcc.target/arm/addr-modes-float.c | 42 ++++++++++++++++\n gcc/testsuite/gcc.target/arm/addr-modes-int.c | 46 +++++++++++++++++\n gcc/testsuite/gcc.target/arm/addr-modes.h | 53 +++++++++++++++++++\n 4 files changed, 183 insertions(+), 25 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes-float.c\n create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes-int.c\n create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes.h", "diff": "diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex 32001e5..b8dbed6 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -9228,8 +9228,48 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost)\n \t }\t\t\t\t\t\t\t\t\\\n \twhile (0);\n \n+/* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM,\n+ considering the costs of the addressing mode and memory access\n+ separately. */\n+static bool\n+arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost,\n+\t int *cost, bool speed_p)\n+{\n+ machine_mode mode = GET_MODE (x);\n+ if (flag_pic\n+ && GET_CODE (XEXP (x, 0)) == PLUS\n+ && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))\n+ /* This will be split into two instructions. Add the cost of the\n+ additional instruction here. The cost of the memory access is computed\n+ below. See arm.md:calculate_pic_address. */\n+ *cost = COSTS_N_INSNS (1);\n+ else\n+ *cost = 0;\n+\n+ /* Calculate cost of the addressing mode. */\n+ if (speed_p)\n+ {\n+ /* TODO: Add table-driven costs for addressing modes. (See patch 2) */\n+ }\n+\n+ /* Calculate cost of memory access. */\n+ if (speed_p)\n+ {\n+ /* data transfer is transfer size divided by bus width. */\n+ int bus_width_bytes = current_tune->bus_width / 4;\n+ *cost += CEIL (GET_MODE_SIZE (mode), bus_width_bytes);\n+ *cost += extra_cost->ldst.load;\n+ }\n+ else\n+ {\n+ *cost += COSTS_N_INSNS (1);\n+ }\n+\n+ return true;\n+}\n+\n /* RTX costs. Make an estimate of the cost of executing the operation\n- X, which is contained with an operation with code OUTER_CODE.\n+ X, which is contained within an operation with code OUTER_CODE.\n SPEED_P indicates whether the cost desired is the performance cost,\n or the size cost. The estimate is stored in COST and the return\n value is TRUE if the cost calculation is final, or FALSE if the\n@@ -9308,30 +9348,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,\n return false;\n \n case MEM:\n- /* A memory access costs 1 insn if the mode is small, or the address is\n-\t a single register, otherwise it costs one insn per word. */\n- if (REG_P (XEXP (x, 0)))\n-\t*cost = COSTS_N_INSNS (1);\n- else if (flag_pic\n-\t && GET_CODE (XEXP (x, 0)) == PLUS\n-\t && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))\n-\t/* This will be split into two instructions.\n-\t See arm.md:calculate_pic_address. */\n-\t*cost = COSTS_N_INSNS (2);\n- else\n-\t*cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));\n-\n- /* For speed optimizations, add the costs of the address and\n-\t accessing memory. */\n- if (speed_p)\n-#ifdef NOT_YET\n-\t*cost += (extra_cost->ldst.load\n-\t\t + arm_address_cost (XEXP (x, 0), mode,\n-\t\t\t\t ADDR_SPACE_GENERIC, speed_p));\n-#else\n- *cost += extra_cost->ldst.load;\n-#endif\n- return true;\n+ return arm_mem_costs (x, extra_cost, cost, speed_p);\n \n case PARALLEL:\n {\ndiff --git a/gcc/testsuite/gcc.target/arm/addr-modes-float.c b/gcc/testsuite/gcc.target/arm/addr-modes-float.c\nnew file mode 100644\nindex 0000000..3b4235c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/addr-modes-float.c\n@@ -0,0 +1,42 @@\n+/* { dg-options \"-O2\" } */\n+/* { dg-add-options arm_neon } */\n+/* { dg-require-effective-target arm_neon_ok } */\n+/* { dg-do compile } */\n+\n+#include <arm_neon.h>\n+\n+#include \"addr-modes.h\"\n+\n+POST_STORE(float)\n+/* { dg-final { scan-assembler \"vstmia.32\" } } */\n+POST_STORE(double)\n+/* { dg-final { scan-assembler \"vstmia.64\" } } */\n+\n+POST_LOAD(float)\n+/* { dg-final { scan-assembler \"vldmia.32\" } } */\n+POST_LOAD(double)\n+/* { dg-final { scan-assembler \"vldmia.64\" } } */\n+\n+POST_STORE_VEC (int8_t, int8x8_t, vst1_s8)\n+/* { dg-final { scan-assembler \"vst1.8\\t\\{.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8)\n+/* { dg-final { scan-assembler \"vst1.8\\t\\{.*\\[-,\\]d.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+\n+POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8)\n+/* { dg-final { scan-assembler \"vst2.8\\t\\{.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8)\n+/* { dg-final { scan-assembler \"vst2.8\\t\\{.*-d.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+\n+POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8)\n+/* { dg-final { scan-assembler \"vst3.8\\t\\{.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8)\n+/* { dg-final { scan-assembler \"vst3.8\\t\\{d\\[02468\\], d\\[02468\\], d\\[02468\\]\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+/* { dg-final { scan-assembler \"vst3.8\\t\\{d\\[13579\\], d\\[13579\\], d\\[13579\\]\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" { xfail *-*-* } } } */\n+\n+POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8)\n+/* { dg-final { scan-assembler \"vst4.8\\t\\{.*\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8)\n+/* { dg-final { scan-assembler \"vst4.8\\t\\{d\\[02468\\], d\\[02468\\], d\\[02468\\], d\\[02468\\]\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" } } */\n+/* { dg-final { scan-assembler \"vst4.8\\t\\{d\\[13579\\], d\\[13579\\], d\\[13579\\], d\\[13579\\]\\}, \\\\\\[r\\[0-9\\]+\\\\\\]!\" { xfail *-*-* } } } */\n+\n+/* { dg-final { scan-assembler-not \"add\" { xfail *-*-* } } } */\ndiff --git a/gcc/testsuite/gcc.target/arm/addr-modes-int.c b/gcc/testsuite/gcc.target/arm/addr-modes-int.c\nnew file mode 100644\nindex 0000000..e3e1e6a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/addr-modes-int.c\n@@ -0,0 +1,46 @@\n+/* { dg-options \"-O2 -march=armv7-a\" } */\n+/* { dg-add-options arm_neon } */\n+/* { dg-require-effective-target arm_neon_ok } */\n+/* { dg-do compile } */\n+\n+#include \"addr-modes.h\"\n+\n+typedef long long ll;\n+\n+PRE_STORE(char)\n+/* { dg-final { scan-assembler \"strb.*#1]!\" } } */\n+PRE_STORE(short)\n+/* { dg-final { scan-assembler \"strh.*#2]!\" } } */\n+PRE_STORE(int)\n+/* { dg-final { scan-assembler \"str.*#4]!\" } } */\n+PRE_STORE(ll)\n+/* { dg-final { scan-assembler \"strd.*#8]!\" } } */\n+\n+POST_STORE(char)\n+/* { dg-final { scan-assembler \"strb.*], #1\" } } */\n+POST_STORE(short)\n+/* { dg-final { scan-assembler \"strh.*], #2\" } } */\n+POST_STORE(int)\n+/* { dg-final { scan-assembler \"str.*], #4\" } } */\n+POST_STORE(ll)\n+/* { dg-final { scan-assembler \"strd.*], #8\" } } */\n+\n+PRE_LOAD(char)\n+/* { dg-final { scan-assembler \"ldrb.*#1]!\" } } */\n+PRE_LOAD(short)\n+/* { dg-final { scan-assembler \"ldrsh.*#2]!\" } } */\n+PRE_LOAD(int)\n+/* { dg-final { scan-assembler \"ldr.*#4]!\" } } */\n+PRE_LOAD(ll)\n+/* { dg-final { scan-assembler \"ldrd.*#8]!\" } } */\n+\n+POST_LOAD(char)\n+/* { dg-final { scan-assembler \"ldrb.*], #1\" } } */\n+POST_LOAD(short)\n+/* { dg-final { scan-assembler \"ldrsh.*], #2\" } } */\n+POST_LOAD(int)\n+/* { dg-final { scan-assembler \"ldr.*], #4\" } } */\n+POST_LOAD(ll)\n+/* { dg-final { scan-assembler \"ldrd.*], #8\" } } */\n+\n+/* { dg-final { scan-assembler-not \"\\tadd\" } } */\ndiff --git a/gcc/testsuite/gcc.target/arm/addr-modes.h b/gcc/testsuite/gcc.target/arm/addr-modes.h\nnew file mode 100644\nindex 0000000..eac4678\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/arm/addr-modes.h\n@@ -0,0 +1,53 @@\n+\n+#define PRE_STORE(T)\t\t\t\\\n+ T *\t\t\t\t\t\\\n+ T ## _pre_store (T *p, T v)\t\t\\\n+ {\t\t\t\t\t\\\n+ *++p = v;\t\t\t\t\\\n+ return p;\t\t\t\t\\\n+ }\t\t\t\t\t\\\n+\n+#define POST_STORE(T)\t\t\t\\\n+ T *\t\t\t\t\t\\\n+ T ## _post_store (T *p, T v)\t\t\\\n+ {\t\t\t\t\t\\\n+ *p++ = v;\t\t\t\t\\\n+ return p;\t\t\t\t\\\n+ }\n+\n+#define POST_STORE_VEC(T, VT, OP)\t\\\n+ T *\t\t\t\t\t\\\n+ VT ## _post_store (T * p, VT v)\t\\\n+ {\t\t\t\t\t\\\n+ OP (p, v);\t\t\t\t\\\n+ p += sizeof (VT) / sizeof (T);\t\\\n+ return p;\t\t\t\t\\\n+ }\n+\n+#define PRE_LOAD(T)\t\t\t\\\n+ void\t\t\t\t\t\\\n+ T ## _pre_load (T *p)\t\t\t\\\n+ {\t\t\t\t\t\\\n+ extern void f ## T (T*,T);\t\t\\\n+ T x = *++p;\t\t\t\t\\\n+ f ## T (p, x);\t\t\t\\\n+ }\n+\n+#define POST_LOAD(T)\t\t\t\\\n+ void\t\t\t\t\t\\\n+ T ## _post_load (T *p)\t\t\\\n+ {\t\t\t\t\t\\\n+ extern void f ## T (T*,T);\t\t\\\n+ T x = *p++;\t\t\t\t\\\n+ f ## T (p, x);\t\t\t\\\n+ }\n+\n+#define POST_LOAD_VEC(T, VT, OP)\t\\\n+ void\t\t\t\t\t\\\n+ VT ## _post_load (T * p)\t\t\\\n+ {\t\t\t\t\t\\\n+ extern void f ## T (T*,T);\t\t\\\n+ VT x = OP (p, v);\t\t\t\\\n+ p += sizeof (VT) / sizeof (T);\t\\\n+ f ## T (p, x);\t\t\t\\\n+ }\n", "prefixes": [ "2/3", "ARM" ] }