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GET /api/patches/812707/?format=api
{ "id": 812707, "url": "http://patchwork.ozlabs.org/api/patches/812707/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505200909-23552-6-git-send-email-weiyi.lu@mediatek.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505200909-23552-6-git-send-email-weiyi.lu@mediatek.com>", "list_archive_url": null, "date": "2017-09-12T07:21:45", "name": "[v3,5/9] dt-bindings: soc: add MT2712 power dt-bindings", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "56b55c75b5072885c0a11edf4612f369cb6f212a", "submitter": { "id": 72166, "url": "http://patchwork.ozlabs.org/api/people/72166/?format=api", "name": "Weiyi Lu", "email": "weiyi.lu@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1505200909-23552-6-git-send-email-weiyi.lu@mediatek.com/mbox/", "series": [ { "id": 2622, "url": "http://patchwork.ozlabs.org/api/series/2622/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=2622", "date": "2017-09-12T07:21:45", "name": "Mediatek MT2712 clock and scpsys support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/2622/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812707/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrx945hMHz9s8J\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 17:23:20 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751028AbdILHWM (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 12 Sep 2017 03:22:12 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:8250 \"EHLO\n\tmailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751144AbdILHWI (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 12 Sep 2017 03:22:08 -0400", "from mtkexhb02.mediatek.inc [(172.21.101.103)] by\n\tmailgw01.mediatek.com (envelope-from <weiyi.lu@mediatek.com>)\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 99043195; Tue, 12 Sep 2017 15:22:02 +0800", "from mtkcas07.mediatek.inc (172.21.101.84) by\n\tmtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Tue, 12 Sep 2017 15:22:01 +0800", "from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas07.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Tue, 12 Sep 2017 15:22:02 +0800" ], "X-UUID": "76f104cd2b294932a4eb8b3adf7553e6-20170912", "From": "Weiyi Lu <weiyi.lu@mediatek.com>", "To": "Matthias Brugger <matthias.bgg@gmail.com>,\n\tStephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh@kernel.org>", "CC": "James Liao <jamesjj.liao@mediatek.com>,\n\tFan Chen <fan.chen@mediatek.com>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,\n\t<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>", "Subject": "[PATCH v3 5/9] dt-bindings: soc: add MT2712 power dt-bindings", "Date": "Tue, 12 Sep 2017 15:21:45 +0800", "Message-ID": "<1505200909-23552-6-git-send-email-weiyi.lu@mediatek.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505200909-23552-1-git-send-email-weiyi.lu@mediatek.com>", "References": "<1505200909-23552-1-git-send-email-weiyi.lu@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add power dt-bindings for MT2712.\n\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Weiyi Lu <weiyi.lu@mediatek.com>\n---\n .../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +++\n include/dt-bindings/power/mt2712-power.h | 26 ++++++++++++++++++++++\n 2 files changed, 29 insertions(+)\n create mode 100644 include/dt-bindings/power/mt2712-power.h", "diff": "diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt\nindex 40056f7..76bf45b 100644\n--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt\n+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt\n@@ -12,11 +12,13 @@ power/power_domain.txt. It provides the power domains defined in\n - include/dt-bindings/power/mt8173-power.h\n - include/dt-bindings/power/mt6797-power.h\n - include/dt-bindings/power/mt2701-power.h\n+- include/dt-bindings/power/mt2712-power.h\n - include/dt-bindings/power/mt7622-power.h\n \n Required properties:\n - compatible: Should be one of:\n \t- \"mediatek,mt2701-scpsys\"\n+\t- \"mediatek,mt2712-scpsys\"\n \t- \"mediatek,mt6797-scpsys\"\n \t- \"mediatek,mt7622-scpsys\"\n \t- \"mediatek,mt8173-scpsys\"\n@@ -27,6 +29,7 @@ Required properties:\n These are clocks which hardware needs to be\n enabled before enabling certain power domains.\n \tRequired clocks for MT2701: \"mm\", \"mfg\", \"ethif\"\n+\tRequired clocks for MT2712: \"mm\", \"mfg\", \"venc\", \"jpgdec\", \"audio\", \"vdec\"\n \tRequired clocks for MT6797: \"mm\", \"mfg\", \"vdec\"\n \tRequired clocks for MT7622: \"hif_sel\"\n \tRequired clocks for MT8173: \"mm\", \"mfg\", \"venc\", \"venc_lt\"\ndiff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h\nnew file mode 100644\nindex 0000000..92b46d7\n--- /dev/null\n+++ b/include/dt-bindings/power/mt2712-power.h\n@@ -0,0 +1,26 @@\n+/*\n+ * Copyright (C) 2017 MediaTek Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.\n+ */\n+\n+#ifndef _DT_BINDINGS_POWER_MT2712_POWER_H\n+#define _DT_BINDINGS_POWER_MT2712_POWER_H\n+\n+#define MT2712_POWER_DOMAIN_MM\t\t0\n+#define MT2712_POWER_DOMAIN_VDEC\t1\n+#define MT2712_POWER_DOMAIN_VENC\t2\n+#define MT2712_POWER_DOMAIN_ISP\t\t3\n+#define MT2712_POWER_DOMAIN_AUDIO\t4\n+#define MT2712_POWER_DOMAIN_USB\t\t5\n+#define MT2712_POWER_DOMAIN_USB2\t6\n+#define MT2712_POWER_DOMAIN_MFG\t\t7\n+\n+#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */\n", "prefixes": [ "v3", "5/9" ] }