Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/812513/?format=api
{ "id": 812513, "url": "http://patchwork.ozlabs.org/api/patches/812513/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-35-eblake@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170911172022.4738-35-eblake@redhat.com>", "list_archive_url": null, "date": "2017-09-11T17:20:18", "name": "[v7,34/38] libqtest: Merge qtest_{read, write}[bwlq]() with {read, write}[bwlq]()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c8a6f931c6b93c1eaecb9a79c8afd73ff15d933f", "submitter": { "id": 6591, "url": "http://patchwork.ozlabs.org/api/people/6591/?format=api", "name": "Eric Blake", "email": "eblake@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-35-eblake@redhat.com/mbox/", "series": [ { "id": 2534, "url": "http://patchwork.ozlabs.org/api/series/2534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2534", "date": "2017-09-11T17:19:47", "name": "Preliminary libqtest cleanups", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/2534/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812513/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812513/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com", "ext-mx04.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=eblake@redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrbGV2vTLz9s83\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 03:56:50 +1000 (AEST)", "from localhost ([::1]:59523 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drSwy-0006hq-Fy\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:56:48 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:39380)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSPk-0000CA-P0\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:22:34 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSPe-0001pd-Lj\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:22:28 -0400", "from mx1.redhat.com ([209.132.183.28]:52910)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <eblake@redhat.com>)\n\tid 1drSPP-0001g9-4D; Mon, 11 Sep 2017 13:22:07 -0400", "from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 3111485543;\n\tMon, 11 Sep 2017 17:22:06 +0000 (UTC)", "from red.redhat.com (ovpn-120-44.rdu2.redhat.com [10.10.120.44])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id B079E18513;\n\tMon, 11 Sep 2017 17:21:55 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mx1.redhat.com 3111485543", "From": "Eric Blake <eblake@redhat.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 11 Sep 2017 12:20:18 -0500", "Message-Id": "<20170911172022.4738-35-eblake@redhat.com>", "In-Reply-To": "<20170911172022.4738-1-eblake@redhat.com>", "References": "<20170911172022.4738-1-eblake@redhat.com>", "X-Scanned-By": "MIMEDefang 2.79 on 10.5.11.14", "X-Greylist": "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.28]);\n\tMon, 11 Sep 2017 17:22:06 +0000 (UTC)", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "209.132.183.28", "Subject": "[Qemu-devel] [PATCH v7 34/38] libqtest: Merge qtest_{read,\n\twrite}[bwlq]() with {read, write}[bwlq]()", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "thuth@redhat.com, \"open list:virtio-blk\" <qemu-block@nongnu.org>,\n\tBen Warren <ben@skyportsystems.com>,\n\t\"Michael S. Tsirkin\" <mst@redhat.com>, armbru@redhat.com,\n\tAlexander Graf <agraf@suse.de>, \"open list:sPAPR\" <qemu-ppc@nongnu.org>, \n\tStefan Hajnoczi <stefanha@redhat.com>,\n\tIgor Mammedov <imammedo@redhat.com>, pbonzini@redhat.com,\n\tDavid Gibson <david@gibson.dropbear.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Maintaining two layers of libqtest APIs, one that takes an explicit\nQTestState object, and the other that uses the implicit global_qtest,\nis annoying. In the interest of getting rid of global implicit\nstate and having less code to maintain, merge:\n qtest_readb()\n qtest_readw()\n qtest_readl()\n qtest_readq()\n qtest_writeb()\n qtest_writew()\n qtest_writel()\n qtest_writeq()\nwith their short counterparts. All callers that previously\nused the short form now make it explicit that they are relying on\nglobal_qtest, and later patches can then clean things up to remove\nthe global variable.\n\nSigned-off-by: Eric Blake <eblake@redhat.com>\n---\n tests/libqtest.h | 132 ++++++---------------------------------------\n tests/acpi-utils.h | 10 ++--\n tests/libqtest.c | 16 +++---\n tests/acpi-utils.c | 2 +-\n tests/bios-tables-test.c | 8 +--\n tests/boot-order-test.c | 6 +--\n tests/boot-sector.c | 4 +-\n tests/endianness-test.c | 12 ++---\n tests/libqos/fw_cfg.c | 4 +-\n tests/libqos/i2c-imx.c | 64 +++++++++++-----------\n tests/libqos/i2c-omap.c | 42 +++++++--------\n tests/libqos/pci-spapr.c | 16 +++---\n tests/libqos/rtas.c | 4 +-\n tests/libqos/virtio-mmio.c | 58 +++++++++-----------\n tests/libqos/virtio-pci.c | 8 +--\n tests/libqos/virtio.c | 73 ++++++++++++-------------\n tests/m25p80-test.c | 80 +++++++++++++--------------\n tests/m48t59-test.c | 4 +-\n tests/pnv-xscom-test.c | 2 +-\n tests/prom-env-test.c | 2 +-\n tests/q35-test.c | 12 ++---\n tests/tco-test.c | 4 +-\n tests/test-arm-mptimer.c | 14 ++---\n tests/vhost-user-test.c | 2 +-\n tests/virtio-blk-test.c | 18 +++----\n tests/virtio-scsi-test.c | 2 +-\n tests/vmgenid-test.c | 2 +-\n 27 files changed, 245 insertions(+), 356 deletions(-)", "diff": "diff --git a/tests/libqtest.h b/tests/libqtest.h\nindex 520f745e7b..d0c487cf79 100644\n--- a/tests/libqtest.h\n+++ b/tests/libqtest.h\n@@ -262,47 +262,47 @@ uint16_t inw(QTestState *s, uint16_t addr);\n uint32_t inl(QTestState *s, uint16_t addr);\n\n /**\n- * qtest_writeb:\n+ * writeb:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to write to.\n * @value: Value being written.\n *\n * Writes an 8-bit value to memory.\n */\n-void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value);\n+void writeb(QTestState *s, uint64_t addr, uint8_t value);\n\n /**\n- * qtest_writew:\n+ * writew:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to write to.\n * @value: Value being written.\n *\n * Writes a 16-bit value to memory.\n */\n-void qtest_writew(QTestState *s, uint64_t addr, uint16_t value);\n+void writew(QTestState *s, uint64_t addr, uint16_t value);\n\n /**\n- * qtest_writel:\n+ * writel:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to write to.\n * @value: Value being written.\n *\n * Writes a 32-bit value to memory.\n */\n-void qtest_writel(QTestState *s, uint64_t addr, uint32_t value);\n+void writel(QTestState *s, uint64_t addr, uint32_t value);\n\n /**\n- * qtest_writeq:\n+ * writeq:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to write to.\n * @value: Value being written.\n *\n * Writes a 64-bit value to memory.\n */\n-void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value);\n+void writeq(QTestState *s, uint64_t addr, uint64_t value);\n\n /**\n- * qtest_readb:\n+ * readb:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to read from.\n *\n@@ -310,10 +310,10 @@ void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value);\n *\n * Returns: Value read.\n */\n-uint8_t qtest_readb(QTestState *s, uint64_t addr);\n+uint8_t readb(QTestState *s, uint64_t addr);\n\n /**\n- * qtest_readw:\n+ * readw:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to read from.\n *\n@@ -321,10 +321,10 @@ uint8_t qtest_readb(QTestState *s, uint64_t addr);\n *\n * Returns: Value read.\n */\n-uint16_t qtest_readw(QTestState *s, uint64_t addr);\n+uint16_t readw(QTestState *s, uint64_t addr);\n\n /**\n- * qtest_readl:\n+ * readl:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to read from.\n *\n@@ -332,10 +332,10 @@ uint16_t qtest_readw(QTestState *s, uint64_t addr);\n *\n * Returns: Value read.\n */\n-uint32_t qtest_readl(QTestState *s, uint64_t addr);\n+uint32_t readl(QTestState *s, uint64_t addr);\n\n /**\n- * qtest_readq:\n+ * readq:\n * @s: #QTestState instance to operate on.\n * @addr: Guest address to read from.\n *\n@@ -343,7 +343,7 @@ uint32_t qtest_readl(QTestState *s, uint64_t addr);\n *\n * Returns: Value read.\n */\n-uint64_t qtest_readq(QTestState *s, uint64_t addr);\n+uint64_t readq(QTestState *s, uint64_t addr);\n\n /**\n * qtest_memread:\n@@ -594,106 +594,6 @@ static inline QDict *qmp_eventwait_ref(const char *event)\n char *hmp(const char *fmt, ...) GCC_FMT_ATTR(1, 2);\n\n /**\n- * writeb:\n- * @addr: Guest address to write to.\n- * @value: Value being written.\n- *\n- * Writes an 8-bit value to guest memory.\n- */\n-static inline void writeb(uint64_t addr, uint8_t value)\n-{\n- qtest_writeb(global_qtest, addr, value);\n-}\n-\n-/**\n- * writew:\n- * @addr: Guest address to write to.\n- * @value: Value being written.\n- *\n- * Writes a 16-bit value to guest memory.\n- */\n-static inline void writew(uint64_t addr, uint16_t value)\n-{\n- qtest_writew(global_qtest, addr, value);\n-}\n-\n-/**\n- * writel:\n- * @addr: Guest address to write to.\n- * @value: Value being written.\n- *\n- * Writes a 32-bit value to guest memory.\n- */\n-static inline void writel(uint64_t addr, uint32_t value)\n-{\n- qtest_writel(global_qtest, addr, value);\n-}\n-\n-/**\n- * writeq:\n- * @addr: Guest address to write to.\n- * @value: Value being written.\n- *\n- * Writes a 64-bit value to guest memory.\n- */\n-static inline void writeq(uint64_t addr, uint64_t value)\n-{\n- qtest_writeq(global_qtest, addr, value);\n-}\n-\n-/**\n- * readb:\n- * @addr: Guest address to read from.\n- *\n- * Reads an 8-bit value from guest memory.\n- *\n- * Returns: Value read.\n- */\n-static inline uint8_t readb(uint64_t addr)\n-{\n- return qtest_readb(global_qtest, addr);\n-}\n-\n-/**\n- * readw:\n- * @addr: Guest address to read from.\n- *\n- * Reads a 16-bit value from guest memory.\n- *\n- * Returns: Value read.\n- */\n-static inline uint16_t readw(uint64_t addr)\n-{\n- return qtest_readw(global_qtest, addr);\n-}\n-\n-/**\n- * readl:\n- * @addr: Guest address to read from.\n- *\n- * Reads a 32-bit value from guest memory.\n- *\n- * Returns: Value read.\n- */\n-static inline uint32_t readl(uint64_t addr)\n-{\n- return qtest_readl(global_qtest, addr);\n-}\n-\n-/**\n- * readq:\n- * @addr: Guest address to read from.\n- *\n- * Reads a 64-bit value from guest memory.\n- *\n- * Returns: Value read.\n- */\n-static inline uint64_t readq(uint64_t addr)\n-{\n- return qtest_readq(global_qtest, addr);\n-}\n-\n-/**\n * memread:\n * @addr: Guest address to read from.\n * @data: Pointer to where memory contents will be stored.\ndiff --git a/tests/acpi-utils.h b/tests/acpi-utils.h\nindex 8ec83f71b1..31eb59837d 100644\n--- a/tests/acpi-utils.h\n+++ b/tests/acpi-utils.h\n@@ -32,21 +32,21 @@ typedef struct {\n do { \\\n switch (sizeof(field)) { \\\n case 1: \\\n- field = qtest_readb(qts, addr); \\\n+ field = readb(qts, addr); \\\n break; \\\n case 2: \\\n- field = qtest_readw(qts, addr); \\\n+ field = readw(qts, addr); \\\n break; \\\n case 4: \\\n- field = qtest_readl(qts, addr); \\\n+ field = readl(qts, addr); \\\n break; \\\n case 8: \\\n- field = qtest_readq(qts, addr); \\\n+ field = readq(qts, addr); \\\n break; \\\n default: \\\n g_assert(false); \\\n } \\\n- addr += sizeof(field); \\\n+ addr += sizeof(field); \\\n } while (0);\n\n #define ACPI_READ_ARRAY_PTR(qts, arr, length, addr) \\\ndiff --git a/tests/libqtest.c b/tests/libqtest.c\nindex 1db86b39f1..d9d0402287 100644\n--- a/tests/libqtest.c\n+++ b/tests/libqtest.c\n@@ -754,22 +754,22 @@ static void qtest_write(QTestState *s, const char *cmd, uint64_t addr,\n qtest_rsp(s, 0);\n }\n\n-void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value)\n+void writeb(QTestState *s, uint64_t addr, uint8_t value)\n {\n qtest_write(s, \"writeb\", addr, value);\n }\n\n-void qtest_writew(QTestState *s, uint64_t addr, uint16_t value)\n+void writew(QTestState *s, uint64_t addr, uint16_t value)\n {\n qtest_write(s, \"writew\", addr, value);\n }\n\n-void qtest_writel(QTestState *s, uint64_t addr, uint32_t value)\n+void writel(QTestState *s, uint64_t addr, uint32_t value)\n {\n qtest_write(s, \"writel\", addr, value);\n }\n\n-void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value)\n+void writeq(QTestState *s, uint64_t addr, uint64_t value)\n {\n qtest_write(s, \"writeq\", addr, value);\n }\n@@ -789,22 +789,22 @@ static uint64_t qtest_read(QTestState *s, const char *cmd, uint64_t addr)\n return value;\n }\n\n-uint8_t qtest_readb(QTestState *s, uint64_t addr)\n+uint8_t readb(QTestState *s, uint64_t addr)\n {\n return qtest_read(s, \"readb\", addr);\n }\n\n-uint16_t qtest_readw(QTestState *s, uint64_t addr)\n+uint16_t readw(QTestState *s, uint64_t addr)\n {\n return qtest_read(s, \"readw\", addr);\n }\n\n-uint32_t qtest_readl(QTestState *s, uint64_t addr)\n+uint32_t readl(QTestState *s, uint64_t addr)\n {\n return qtest_read(s, \"readl\", addr);\n }\n\n-uint64_t qtest_readq(QTestState *s, uint64_t addr)\n+uint64_t readq(QTestState *s, uint64_t addr)\n {\n return qtest_read(s, \"readq\", addr);\n }\ndiff --git a/tests/acpi-utils.c b/tests/acpi-utils.c\nindex 6dc8ca1a8c..e915cc8d57 100644\n--- a/tests/acpi-utils.c\n+++ b/tests/acpi-utils.c\n@@ -42,7 +42,7 @@ uint32_t acpi_find_rsdp_address(QTestState *qts)\n int i;\n\n for (i = 0; i < sizeof sig - 1; ++i) {\n- sig[i] = qtest_readb(qts, off + i);\n+ sig[i] = readb(qts, off + i);\n }\n\n if (!memcmp(sig, \"RSD PTR \", sizeof sig)) {\ndiff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c\nindex c17cd8e1a3..f0a2e94ff1 100644\n--- a/tests/bios-tables-test.c\n+++ b/tests/bios-tables-test.c\n@@ -539,7 +539,7 @@ static void test_smbios_entry_point(test_data *data)\n int i;\n\n for (i = 0; i < sizeof sig - 1; ++i) {\n- sig[i] = qtest_readb(data->qts, off + i);\n+ sig[i] = readb(data->qts, off + i);\n }\n\n if (!memcmp(sig, \"_SM_\", sizeof sig)) {\n@@ -582,9 +582,9 @@ static void test_smbios_structs(test_data *data)\n for (i = 0; i < ep_table->number_of_structures; i++) {\n\n /* grab type and formatted area length from struct header */\n- type = qtest_readb(data->qts, addr);\n+ type = readb(data->qts, addr);\n g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE);\n- len = qtest_readb(data->qts, addr + 1);\n+ len = readb(data->qts, addr + 1);\n\n /* single-instance structs must not have been encountered before */\n if (smbios_single_instance(type)) {\n@@ -596,7 +596,7 @@ static void test_smbios_structs(test_data *data)\n prv = crt = 1;\n while (prv || crt) {\n prv = crt;\n- crt = qtest_readb(data->qts, addr + len);\n+ crt = readb(data->qts, addr + len);\n len++;\n }\n\ndiff --git a/tests/boot-order-test.c b/tests/boot-order-test.c\nindex 177aac95ad..048c8721c6 100644\n--- a/tests/boot-order-test.c\n+++ b/tests/boot-order-test.c\n@@ -108,9 +108,9 @@ static void test_pc_boot_order(void)\n\n static uint8_t read_m48t59(uint64_t addr, uint16_t reg)\n {\n- writeb(addr, reg & 0xff);\n- writeb(addr + 1, reg >> 8);\n- return readb(addr + 3);\n+ writeb(global_qtest, addr, reg & 0xff);\n+ writeb(global_qtest, addr + 1, reg >> 8);\n+ return readb(global_qtest, addr + 3);\n }\n\n static uint64_t read_boot_order_prep(void)\ndiff --git a/tests/boot-sector.c b/tests/boot-sector.c\nindex 8c8ac7f124..7b69e1d706 100644\n--- a/tests/boot-sector.c\n+++ b/tests/boot-sector.c\n@@ -146,8 +146,8 @@ void boot_sector_test(QTestState *qts)\n * instruction.\n */\n for (i = 0; i < TEST_CYCLES; ++i) {\n- signature_low = qtest_readb(qts, SIGNATURE_ADDR);\n- signature_high = qtest_readb(qts, SIGNATURE_ADDR + 1);\n+ signature_low = readb(qts, SIGNATURE_ADDR);\n+ signature_high = readb(qts, SIGNATURE_ADDR + 1);\n signature = (signature_high << 8) | signature_low;\n if (signature == SIGNATURE) {\n break;\ndiff --git a/tests/endianness-test.c b/tests/endianness-test.c\nindex 16b303525e..bb1fb025a6 100644\n--- a/tests/endianness-test.c\n+++ b/tests/endianness-test.c\n@@ -54,7 +54,7 @@ static uint8_t isa_inb(const TestCase *test, uint16_t addr)\n if (test->isa_base == -1) {\n value = inb(global_qtest, addr);\n } else {\n- value = readb(test->isa_base + addr);\n+ value = readb(global_qtest, test->isa_base + addr);\n }\n return value;\n }\n@@ -65,7 +65,7 @@ static uint16_t isa_inw(const TestCase *test, uint16_t addr)\n if (test->isa_base == -1) {\n value = inw(global_qtest, addr);\n } else {\n- value = readw(test->isa_base + addr);\n+ value = readw(global_qtest, test->isa_base + addr);\n }\n return test->bswap ? bswap16(value) : value;\n }\n@@ -76,7 +76,7 @@ static uint32_t isa_inl(const TestCase *test, uint16_t addr)\n if (test->isa_base == -1) {\n value = inl(global_qtest, addr);\n } else {\n- value = readl(test->isa_base + addr);\n+ value = readl(global_qtest, test->isa_base + addr);\n }\n return test->bswap ? bswap32(value) : value;\n }\n@@ -86,7 +86,7 @@ static void isa_outb(const TestCase *test, uint16_t addr, uint8_t value)\n if (test->isa_base == -1) {\n outb(global_qtest, addr, value);\n } else {\n- writeb(test->isa_base + addr, value);\n+ writeb(global_qtest, test->isa_base + addr, value);\n }\n }\n\n@@ -96,7 +96,7 @@ static void isa_outw(const TestCase *test, uint16_t addr, uint16_t value)\n if (test->isa_base == -1) {\n outw(global_qtest, addr, value);\n } else {\n- writew(test->isa_base + addr, value);\n+ writew(global_qtest, test->isa_base + addr, value);\n }\n }\n\n@@ -106,7 +106,7 @@ static void isa_outl(const TestCase *test, uint16_t addr, uint32_t value)\n if (test->isa_base == -1) {\n outl(global_qtest, addr, value);\n } else {\n- writel(test->isa_base + addr, value);\n+ writel(global_qtest, test->isa_base + addr, value);\n }\n }\n\ndiff --git a/tests/libqos/fw_cfg.c b/tests/libqos/fw_cfg.c\nindex 157d5190c6..667e2ee93a 100644\n--- a/tests/libqos/fw_cfg.c\n+++ b/tests/libqos/fw_cfg.c\n@@ -56,7 +56,7 @@ uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)\n\n static void mm_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)\n {\n- qtest_writew(fw_cfg->qts, fw_cfg->base, key);\n+ writew(fw_cfg->qts, fw_cfg->base, key);\n }\n\n static void mm_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)\n@@ -65,7 +65,7 @@ static void mm_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)\n int i;\n\n for (i = 0; i < len; i++) {\n- ptr[i] = qtest_readb(fw_cfg->qts, fw_cfg->base + 2);\n+ ptr[i] = readb(fw_cfg->qts, fw_cfg->base + 2);\n }\n }\n\ndiff --git a/tests/libqos/i2c-imx.c b/tests/libqos/i2c-imx.c\nindex 0945f2ecdc..cb5cce701f 100644\n--- a/tests/libqos/i2c-imx.c\n+++ b/tests/libqos/i2c-imx.c\n@@ -40,8 +40,8 @@ typedef struct IMXI2C {\n static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr,\n enum IMXI2CDirection direction)\n {\n- qtest_writeb(s->parent.qts, s->addr + I2DR_ADDR,\n- (addr << 1) | (direction == IMX_I2C_READ ? 1 : 0));\n+ writeb(s->parent.qts, s->addr + I2DR_ADDR,\n+ (addr << 1) | (direction == IMX_I2C_READ ? 1 : 0));\n }\n\n static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n@@ -63,35 +63,35 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n I2CR_MTX |\n I2CR_TXAK;\n\n- qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* set the slave address */\n imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n while (size < len) {\n /* check we are still busy */\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* write the data */\n- qtest_writeb(i2c->qts, s->addr + I2DR_ADDR, buf[size]);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2DR_ADDR, buf[size]);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n size++;\n@@ -99,8 +99,8 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n\n /* release the bus */\n data &= ~(I2CR_MSTA | I2CR_MTX);\n- qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) == 0);\n }\n\n@@ -123,19 +123,19 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n I2CR_MTX |\n I2CR_TXAK;\n\n- qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* set the slave address */\n imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n /* set the bus for read */\n@@ -144,23 +144,23 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n if (len != 1) {\n data &= ~I2CR_TXAK;\n }\n- qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* dummy read */\n- qtest_readb(i2c->qts, s->addr + I2DR_ADDR);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ readb(i2c->qts, s->addr + I2DR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n\n /* ack the interrupt */\n- qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n while (size < len) {\n /* check we are still busy */\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n if (size == (len - 1)) {\n@@ -170,26 +170,26 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n /* ack the data read */\n data |= I2CR_TXAK;\n }\n- qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n\n /* read the data */\n- buf[size] = qtest_readb(i2c->qts, s->addr + I2DR_ADDR);\n+ buf[size] = readb(i2c->qts, s->addr + I2DR_ADDR);\n\n if (size != (len - 1)) {\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n\n /* ack the interrupt */\n- qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n }\n\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n size++;\n }\n\n- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n+ status = readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) == 0);\n }\n\ndiff --git a/tests/libqos/i2c-omap.c b/tests/libqos/i2c-omap.c\nindex 1ef6e7b200..c4fefb64a8 100644\n--- a/tests/libqos/i2c-omap.c\n+++ b/tests/libqos/i2c-omap.c\n@@ -51,8 +51,8 @@ static void omap_i2c_set_slave_addr(OMAPI2C *s, uint8_t addr)\n {\n uint16_t data = addr;\n\n- qtest_writew(s->parent.qts, s->addr + OMAP_I2C_SA, data);\n- data = qtest_readw(s->parent.qts, s->addr + OMAP_I2C_SA);\n+ writew(s->parent.qts, s->addr + OMAP_I2C_SA, data);\n+ data = readw(s->parent.qts, s->addr + OMAP_I2C_SA);\n g_assert_cmphex(data, ==, addr);\n }\n\n@@ -65,38 +65,38 @@ static void omap_i2c_send(I2CAdapter *i2c, uint8_t addr,\n omap_i2c_set_slave_addr(s, addr);\n\n data = len;\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n+ writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n\n data = OMAP_I2C_CON_I2C_EN |\n OMAP_I2C_CON_TRX |\n OMAP_I2C_CON_MST |\n OMAP_I2C_CON_STT |\n OMAP_I2C_CON_STP;\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n+ writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) != 0);\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_NACK) == 0);\n\n while (len > 1) {\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_XRDY) != 0);\n\n data = buf[0] | ((uint16_t)buf[1] << 8);\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n+ writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n buf = (uint8_t *)buf + 2;\n len -= 2;\n }\n if (len == 1) {\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_XRDY) != 0);\n\n data = buf[0];\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n+ writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n }\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n }\n\n@@ -109,30 +109,30 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n omap_i2c_set_slave_addr(s, addr);\n\n data = len;\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n+ writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n\n data = OMAP_I2C_CON_I2C_EN |\n OMAP_I2C_CON_MST |\n OMAP_I2C_CON_STT |\n OMAP_I2C_CON_STP;\n- qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n+ writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_NACK) == 0);\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CNT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_CNT);\n g_assert_cmpuint(data, ==, len);\n\n while (len > 0) {\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_RRDY) != 0);\n g_assert((data & OMAP_I2C_STAT_ROVR) == 0);\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_DATA);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_DATA);\n\n- stat = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n+ stat = readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n\n if (unlikely(len == 1)) {\n g_assert((stat & OMAP_I2C_STAT_SBD) != 0);\n@@ -148,7 +148,7 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n }\n }\n\n- data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n+ data = readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n }\n\n@@ -165,7 +165,7 @@ I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr)\n i2c->qts = qts;\n\n /* verify the mmio address by looking for a known signature */\n- data = qtest_readw(qts, addr + OMAP_I2C_REV);\n+ data = readw(qts, addr + OMAP_I2C_REV);\n g_assert_cmphex(data, ==, 0x34);\n\n return i2c;\ndiff --git a/tests/libqos/pci-spapr.c b/tests/libqos/pci-spapr.c\nindex 4c29889b0b..7bae94e9bd 100644\n--- a/tests/libqos/pci-spapr.c\n+++ b/tests/libqos/pci-spapr.c\n@@ -45,49 +45,49 @@ typedef struct QPCIBusSPAPR {\n static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- return qtest_readb(bus->qts, s->pio_cpu_base + addr);\n+ return readb(bus->qts, s->pio_cpu_base + addr);\n }\n\n static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- qtest_writeb(bus->qts, s->pio_cpu_base + addr, val);\n+ writeb(bus->qts, s->pio_cpu_base + addr, val);\n }\n\n static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- return bswap16(qtest_readw(bus->qts, s->pio_cpu_base + addr));\n+ return bswap16(readw(bus->qts, s->pio_cpu_base + addr));\n }\n\n static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- qtest_writew(bus->qts, s->pio_cpu_base + addr, bswap16(val));\n+ writew(bus->qts, s->pio_cpu_base + addr, bswap16(val));\n }\n\n static uint32_t qpci_spapr_pio_readl(QPCIBus *bus, uint32_t addr)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- return bswap32(qtest_readl(bus->qts, s->pio_cpu_base + addr));\n+ return bswap32(readl(bus->qts, s->pio_cpu_base + addr));\n }\n\n static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- qtest_writel(bus->qts, s->pio_cpu_base + addr, bswap32(val));\n+ writel(bus->qts, s->pio_cpu_base + addr, bswap32(val));\n }\n\n static uint64_t qpci_spapr_pio_readq(QPCIBus *bus, uint32_t addr)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- return bswap64(qtest_readq(bus->qts, s->pio_cpu_base + addr));\n+ return bswap64(readq(bus->qts, s->pio_cpu_base + addr));\n }\n\n static void qpci_spapr_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)\n {\n QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);\n- qtest_writeq(bus->qts, s->pio_cpu_base + addr, bswap64(val));\n+ writeq(bus->qts, s->pio_cpu_base + addr, bswap64(val));\n }\n\n static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr,\ndiff --git a/tests/libqos/rtas.c b/tests/libqos/rtas.c\nindex d81ff4274d..fd5d34364e 100644\n--- a/tests/libqos/rtas.c\n+++ b/tests/libqos/rtas.c\n@@ -13,7 +13,7 @@ static void qrtas_copy_args(QTestState *qts, uint64_t target_args,\n int i;\n\n for (i = 0; i < nargs; i++) {\n- qtest_writel(qts, target_args + i * sizeof(uint32_t), args[i]);\n+ writel(qts, target_args + i * sizeof(uint32_t), args[i]);\n }\n }\n\n@@ -23,7 +23,7 @@ static void qrtas_copy_ret(QTestState *qts, uint64_t target_ret,\n int i;\n\n for (i = 0; i < nret; i++) {\n- ret[i] = qtest_readl(qts, target_ret + i * sizeof(uint32_t));\n+ ret[i] = readl(qts, target_ret + i * sizeof(uint32_t));\n }\n }\n\ndiff --git a/tests/libqos/virtio-mmio.c b/tests/libqos/virtio-mmio.c\nindex 8d256f6ac9..b2a5b63494 100644\n--- a/tests/libqos/virtio-mmio.c\n+++ b/tests/libqos/virtio-mmio.c\n@@ -18,45 +18,40 @@\n static uint8_t qvirtio_mmio_config_readb(QVirtioDevice *d, uint64_t off)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readb(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n+ return readb(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n }\n\n static uint16_t qvirtio_mmio_config_readw(QVirtioDevice *d, uint64_t off)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readw(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n+ return readw(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n }\n\n static uint32_t qvirtio_mmio_config_readl(QVirtioDevice *d, uint64_t off)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readl(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n+ return readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n }\n\n static uint64_t qvirtio_mmio_config_readq(QVirtioDevice *d, uint64_t off)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readq(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n+ return readq(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_SPECIFIC + off);\n }\n\n static uint32_t qvirtio_mmio_get_features(QVirtioDevice *d)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES_SEL, 0);\n- return qtest_readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES_SEL, 0);\n+ return readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES);\n }\n\n static void qvirtio_mmio_set_features(QVirtioDevice *d, uint32_t features)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n dev->features = features;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES_SEL, 0);\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES,\n- features);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES_SEL, 0);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES, features);\n }\n\n static uint32_t qvirtio_mmio_get_guest_features(QVirtioDevice *d)\n@@ -68,13 +63,13 @@ static uint32_t qvirtio_mmio_get_guest_features(QVirtioDevice *d)\n static uint8_t qvirtio_mmio_get_status(QVirtioDevice *d)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS);\n+ return readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS);\n }\n\n static void qvirtio_mmio_set_status(QVirtioDevice *d, uint8_t status)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS, status);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS, status);\n }\n\n static bool qvirtio_mmio_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)\n@@ -82,10 +77,9 @@ static bool qvirtio_mmio_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n uint32_t isr;\n\n- isr = qtest_readl(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1;\n+ isr = readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 1;\n if (isr != 0) {\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 1);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 1);\n return true;\n }\n\n@@ -97,10 +91,9 @@ static bool qvirtio_mmio_get_config_isr_status(QVirtioDevice *d)\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n uint32_t isr;\n\n- isr = qtest_readl(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2;\n+ isr = readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_STATUS) & 2;\n if (isr != 0) {\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 2);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 2);\n return true;\n }\n\n@@ -110,22 +103,22 @@ static bool qvirtio_mmio_get_config_isr_status(QVirtioDevice *d)\n static void qvirtio_mmio_queue_select(QVirtioDevice *d, uint16_t index)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_SEL, index);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_SEL, index);\n\n- g_assert_cmphex(qtest_readl(d->bus->qts,\n- dev->addr + QVIRTIO_MMIO_QUEUE_PFN), ==, 0);\n+ g_assert_cmphex(readl(d->bus->qts,\n+ dev->addr + QVIRTIO_MMIO_QUEUE_PFN), ==, 0);\n }\n\n static uint16_t qvirtio_mmio_get_queue_size(QVirtioDevice *d)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- return qtest_readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM_MAX);\n+ return readl(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM_MAX);\n }\n\n static void qvirtio_mmio_set_queue_address(QVirtioDevice *d, uint32_t pfn)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN, pfn);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_PFN, pfn);\n }\n\n static QVirtQueue *qvirtio_mmio_virtqueue_setup(QVirtioDevice *d,\n@@ -137,8 +130,7 @@ static QVirtQueue *qvirtio_mmio_virtqueue_setup(QVirtioDevice *d,\n\n vq = g_malloc0(sizeof(*vq));\n qvirtio_mmio_queue_select(d, index);\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_ALIGN,\n- dev->page_size);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_ALIGN, dev->page_size);\n\n vq->dev = d;\n vq->index = index;\n@@ -149,7 +141,7 @@ static QVirtQueue *qvirtio_mmio_virtqueue_setup(QVirtioDevice *d,\n vq->indirect = (dev->features & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;\n vq->event = (dev->features & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;\n\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM, vq->size);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NUM, vq->size);\n\n /* Check different than 0 */\n g_assert_cmpint(vq->size, !=, 0);\n@@ -174,7 +166,7 @@ static void qvirtio_mmio_virtqueue_cleanup(QVirtQueue *vq,\n static void qvirtio_mmio_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)\n {\n QVirtioMMIODevice *dev = (QVirtioMMIODevice *)d;\n- qtest_writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NOTIFY, vq->index);\n+ writel(d->bus->qts, dev->addr + QVIRTIO_MMIO_QUEUE_NOTIFY, vq->index);\n }\n\n const QVirtioBus qvirtio_mmio = {\n@@ -204,15 +196,15 @@ QVirtioMMIODevice *qvirtio_mmio_init_device(QTestState *qts, uint64_t addr,\n uint32_t magic;\n dev = g_malloc0(sizeof(*dev));\n\n- magic = qtest_readl(qts, addr + QVIRTIO_MMIO_MAGIC_VALUE);\n+ magic = readl(qts, addr + QVIRTIO_MMIO_MAGIC_VALUE);\n g_assert(magic == ('v' | 'i' << 8 | 'r' << 16 | 't' << 24));\n\n dev->addr = addr;\n dev->page_size = page_size;\n- dev->vdev.device_type = qtest_readl(qts, addr + QVIRTIO_MMIO_DEVICE_ID);\n+ dev->vdev.device_type = readl(qts, addr + QVIRTIO_MMIO_DEVICE_ID);\n dev->vdev.bus = qvirtio_init_bus(qts, &qvirtio_mmio);\n\n- qtest_writel(qts, addr + QVIRTIO_MMIO_GUEST_PAGE_SIZE, page_size);\n+ writel(qts, addr + QVIRTIO_MMIO_GUEST_PAGE_SIZE, page_size);\n\n return dev;\n }\ndiff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c\nindex a7b17b3ba2..ef7d6da153 100644\n--- a/tests/libqos/virtio-pci.c\n+++ b/tests/libqos/virtio-pci.c\n@@ -168,9 +168,9 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)\n /* No ISR checking should be done if masked, but read anyway */\n return qpci_msix_pending(dev->pdev, vqpci->msix_entry);\n } else {\n- data = qtest_readl(d->bus->qts, vqpci->msix_addr);\n+ data = readl(d->bus->qts, vqpci->msix_addr);\n if (data == vqpci->msix_data) {\n- qtest_writel(d->bus->qts, vqpci->msix_addr, 0);\n+ writel(d->bus->qts, vqpci->msix_addr, 0);\n return true;\n } else {\n return false;\n@@ -192,9 +192,9 @@ static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)\n /* No ISR checking should be done if masked, but read anyway */\n return qpci_msix_pending(dev->pdev, dev->config_msix_entry);\n } else {\n- data = qtest_readl(d->bus->qts, dev->config_msix_addr);\n+ data = readl(d->bus->qts, dev->config_msix_addr);\n if (data == dev->config_msix_data) {\n- qtest_writel(d->bus->qts, dev->config_msix_addr, 0);\n+ writel(d->bus->qts, dev->config_msix_addr, 0);\n return true;\n } else {\n return false;\ndiff --git a/tests/libqos/virtio.c b/tests/libqos/virtio.c\nindex 92e47e78f2..e5252052d9 100644\n--- a/tests/libqos/virtio.c\n+++ b/tests/libqos/virtio.c\n@@ -118,7 +118,7 @@ uint8_t qvirtio_wait_status_byte_no_isr(QVirtioDevice *d,\n gint64 start_time = g_get_monotonic_time();\n uint8_t val;\n\n- while ((val = qtest_readb(d->bus->qts, addr)) == 0xff) {\n+ while ((val = readb(d->bus->qts, addr)) == 0xff) {\n clock_step(d->bus->qts, 100);\n g_assert(!d->bus->get_queue_isr_status(d, vq));\n g_assert(g_get_monotonic_time() - start_time <= timeout_us);\n@@ -179,23 +179,23 @@ void qvring_init(const QGuestAllocator *alloc, QVirtQueue *vq, uint64_t addr)\n\n for (i = 0; i < vq->size - 1; i++) {\n /* vq->desc[i].addr */\n- qtest_writeq(vq->dev->bus->qts, vq->desc + (16 * i), 0);\n+ writeq(vq->dev->bus->qts, vq->desc + (16 * i), 0);\n /* vq->desc[i].next */\n- qtest_writew(vq->dev->bus->qts, vq->desc + (16 * i) + 14, i + 1);\n+ writew(vq->dev->bus->qts, vq->desc + (16 * i) + 14, i + 1);\n }\n\n /* vq->avail->flags */\n- qtest_writew(vq->dev->bus->qts, vq->avail, 0);\n+ writew(vq->dev->bus->qts, vq->avail, 0);\n /* vq->avail->idx */\n- qtest_writew(vq->dev->bus->qts, vq->avail + 2, 0);\n+ writew(vq->dev->bus->qts, vq->avail + 2, 0);\n /* vq->avail->used_event */\n- qtest_writew(vq->dev->bus->qts, vq->avail + 4 + (2 * vq->size), 0);\n+ writew(vq->dev->bus->qts, vq->avail + 4 + (2 * vq->size), 0);\n\n /* vq->used->flags */\n- qtest_writew(vq->dev->bus->qts, vq->used, 0);\n+ writew(vq->dev->bus->qts, vq->used, 0);\n /* vq->used->avail_event */\n- qtest_writew(vq->dev->bus->qts,\n- vq->used + 2 + sizeof(struct vring_used_elem) * vq->size, 0);\n+ writew(vq->dev->bus->qts,\n+ vq->used + 2 + sizeof(struct vring_used_elem) * vq->size, 0);\n }\n\n QVRingIndirectDesc *qvring_indirect_desc_setup(QVirtioDevice *d,\n@@ -210,12 +210,11 @@ QVRingIndirectDesc *qvring_indirect_desc_setup(QVirtioDevice *d,\n\n for (i = 0; i < elem - 1; ++i) {\n /* indirect->desc[i].addr */\n- qtest_writeq(d->bus->qts, indirect->desc + (16 * i), 0);\n+ writeq(d->bus->qts, indirect->desc + (16 * i), 0);\n /* indirect->desc[i].flags */\n- qtest_writew(d->bus->qts, indirect->desc + (16 * i) + 12,\n- VRING_DESC_F_NEXT);\n+ writew(d->bus->qts, indirect->desc + (16 * i) + 12, VRING_DESC_F_NEXT);\n /* indirect->desc[i].next */\n- qtest_writew(d->bus->qts, indirect->desc + (16 * i) + 14, i + 1);\n+ writew(d->bus->qts, indirect->desc + (16 * i) + 14, i + 1);\n }\n\n return indirect;\n@@ -228,18 +227,18 @@ void qvring_indirect_desc_add(QTestState *qts, QVRingIndirectDesc *indirect,\n\n g_assert_cmpint(indirect->index, <, indirect->elem);\n\n- flags = qtest_readw(qts, indirect->desc + (16 * indirect->index) + 12);\n+ flags = readw(qts, indirect->desc + (16 * indirect->index) + 12);\n\n if (write) {\n flags |= VRING_DESC_F_WRITE;\n }\n\n /* indirect->desc[indirect->index].addr */\n- qtest_writeq(qts, indirect->desc + (16 * indirect->index), data);\n+ writeq(qts, indirect->desc + (16 * indirect->index), data);\n /* indirect->desc[indirect->index].len */\n- qtest_writel(qts, indirect->desc + (16 * indirect->index) + 8, len);\n+ writel(qts, indirect->desc + (16 * indirect->index) + 8, len);\n /* indirect->desc[indirect->index].flags */\n- qtest_writew(qts, indirect->desc + (16 * indirect->index) + 12, flags);\n+ writew(qts, indirect->desc + (16 * indirect->index) + 12, flags);\n\n indirect->index++;\n }\n@@ -259,12 +258,11 @@ uint32_t qvirtqueue_add(QVirtQueue *vq, uint64_t data, uint32_t len, bool write,\n }\n\n /* vq->desc[vq->free_head].addr */\n- qtest_writeq(vq->dev->bus->qts, vq->desc + (16 * vq->free_head), data);\n+ writeq(vq->dev->bus->qts, vq->desc + (16 * vq->free_head), data);\n /* vq->desc[vq->free_head].len */\n- qtest_writel(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 8, len);\n+ writel(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 8, len);\n /* vq->desc[vq->free_head].flags */\n- qtest_writew(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 12,\n- flags);\n+ writew(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 12, flags);\n\n return vq->free_head++; /* Return and increase, in this order */\n }\n@@ -278,14 +276,13 @@ uint32_t qvirtqueue_add_indirect(QVirtQueue *vq, QVRingIndirectDesc *indirect)\n vq->num_free--;\n\n /* vq->desc[vq->free_head].addr */\n- qtest_writeq(vq->dev->bus->qts, vq->desc + (16 * vq->free_head),\n- indirect->desc);\n+ writeq(vq->dev->bus->qts, vq->desc + (16 * vq->free_head), indirect->desc);\n /* vq->desc[vq->free_head].len */\n- qtest_writel(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 8,\n- sizeof(struct vring_desc) * indirect->elem);\n+ writel(vq->dev->bus->qts, vq->desc + (16 * vq->free_head) + 8,\n+ sizeof(struct vring_desc) * indirect->elem);\n /* vq->desc[vq->free_head].flags */\n- qtest_writew(vq->dev->bus->qts,\n- vq->desc + (16 * vq->free_head) + 12, VRING_DESC_F_INDIRECT);\n+ writew(vq->dev->bus->qts,\n+ vq->desc + (16 * vq->free_head) + 12, VRING_DESC_F_INDIRECT);\n\n return vq->free_head++; /* Return and increase, in this order */\n }\n@@ -293,7 +290,7 @@ uint32_t qvirtqueue_add_indirect(QVirtQueue *vq, QVRingIndirectDesc *indirect)\n void qvirtqueue_kick(QVirtioDevice *d, QVirtQueue *vq, uint32_t free_head)\n {\n /* vq->avail->idx */\n- uint16_t idx = qtest_readw(d->bus->qts, vq->avail + 2);\n+ uint16_t idx = readw(d->bus->qts, vq->avail + 2);\n /* vq->used->flags */\n uint16_t flags;\n /* vq->used->avail_event */\n@@ -302,15 +299,14 @@ void qvirtqueue_kick(QVirtioDevice *d, QVirtQueue *vq, uint32_t free_head)\n assert(vq->dev == d);\n\n /* vq->avail->ring[idx % vq->size] */\n- qtest_writew(d->bus->qts, vq->avail + 4 + (2 * (idx % vq->size)),\n- free_head);\n+ writew(d->bus->qts, vq->avail + 4 + (2 * (idx % vq->size)), free_head);\n /* vq->avail->idx */\n- qtest_writew(d->bus->qts, vq->avail + 2, idx + 1);\n+ writew(d->bus->qts, vq->avail + 2, idx + 1);\n\n /* Must read after idx is updated */\n- flags = qtest_readw(d->bus->qts, vq->avail);\n- avail_event = qtest_readw(d->bus->qts, vq->used + 4 +\n- sizeof(struct vring_used_elem) * vq->size);\n+ flags = readw(d->bus->qts, vq->avail);\n+ avail_event = readw(d->bus->qts, vq->used + 4 +\n+ sizeof(struct vring_used_elem) * vq->size);\n\n /* < 1 because we add elements to avail queue one by one */\n if ((flags & VRING_USED_F_NO_NOTIFY) == 0 &&\n@@ -331,8 +327,7 @@ bool qvirtqueue_get_buf(QVirtQueue *vq, uint32_t *desc_idx)\n {\n uint16_t idx;\n\n- idx = qtest_readw(vq->dev->bus->qts,\n- vq->used + offsetof(struct vring_used, idx));\n+ idx = readw(vq->dev->bus->qts, vq->used + offsetof(struct vring_used, idx));\n if (idx == vq->last_used_idx) {\n return false;\n }\n@@ -344,8 +339,8 @@ bool qvirtqueue_get_buf(QVirtQueue *vq, uint32_t *desc_idx)\n offsetof(struct vring_used, ring) +\n (vq->last_used_idx % vq->size) *\n sizeof(struct vring_used_elem);\n- *desc_idx = qtest_readl(vq->dev->bus->qts, elem_addr +\n- offsetof(struct vring_used_elem, id));\n+ *desc_idx = readl(vq->dev->bus->qts, elem_addr +\n+ offsetof(struct vring_used_elem, id));\n }\n\n vq->last_used_idx++;\n@@ -357,5 +352,5 @@ void qvirtqueue_set_used_event(QVirtQueue *vq, uint16_t idx)\n g_assert(vq->event);\n\n /* vq->avail->used_event */\n- qtest_writew(vq->dev->bus->qts, vq->avail + 4 + (2 * vq->size), idx);\n+ writew(vq->dev->bus->qts, vq->avail + 4 + (2 * vq->size), idx);\n }\ndiff --git a/tests/m25p80-test.c b/tests/m25p80-test.c\nindex c276e738e9..a480776bb5 100644\n--- a/tests/m25p80-test.c\n+++ b/tests/m25p80-test.c\n@@ -75,53 +75,53 @@ static inline uint32_t make_be32(uint32_t data)\n\n static void spi_conf(uint32_t value)\n {\n- uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);\n+ uint32_t conf = readl(global_qtest, ASPEED_FMC_BASE + R_CONF);\n\n conf |= value;\n- writel(ASPEED_FMC_BASE + R_CONF, conf);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CONF, conf);\n }\n\n static void spi_conf_remove(uint32_t value)\n {\n- uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);\n+ uint32_t conf = readl(global_qtest, ASPEED_FMC_BASE + R_CONF);\n\n conf &= ~value;\n- writel(ASPEED_FMC_BASE + R_CONF, conf);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CONF, conf);\n }\n\n static void spi_ce_ctrl(uint32_t value)\n {\n- uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);\n+ uint32_t conf = readl(global_qtest, ASPEED_FMC_BASE + R_CE_CTRL);\n\n conf |= value;\n- writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CE_CTRL, conf);\n }\n\n static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)\n {\n- uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);\n+ uint32_t ctrl = readl(global_qtest, ASPEED_FMC_BASE + R_CTRL0);\n ctrl &= ~(CTRL_USERMODE | 0xff << 16);\n ctrl |= mode | (cmd << 16);\n- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CTRL0, ctrl);\n }\n\n static void spi_ctrl_start_user(void)\n {\n- uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);\n+ uint32_t ctrl = readl(global_qtest, ASPEED_FMC_BASE + R_CTRL0);\n\n ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;\n- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CTRL0, ctrl);\n\n ctrl &= ~CTRL_CE_STOP_ACTIVE;\n- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CTRL0, ctrl);\n }\n\n static void spi_ctrl_stop_user(void)\n {\n- uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);\n+ uint32_t ctrl = readl(global_qtest, ASPEED_FMC_BASE + R_CTRL0);\n\n ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;\n- writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);\n+ writel(global_qtest, ASPEED_FMC_BASE + R_CTRL0, ctrl);\n }\n\n static void flash_reset(void)\n@@ -129,8 +129,8 @@ static void flash_reset(void)\n spi_conf(CONF_ENABLE_W0);\n\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, RESET_ENABLE);\n- writeb(ASPEED_FLASH_BASE, RESET_MEMORY);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, RESET_ENABLE);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, RESET_MEMORY);\n spi_ctrl_stop_user();\n\n spi_conf_remove(CONF_ENABLE_W0);\n@@ -143,10 +143,10 @@ static void test_read_jedec(void)\n spi_conf(CONF_ENABLE_W0);\n\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, JEDEC_READ);\n- jedec |= readb(ASPEED_FLASH_BASE) << 16;\n- jedec |= readb(ASPEED_FLASH_BASE) << 8;\n- jedec |= readb(ASPEED_FLASH_BASE);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, JEDEC_READ);\n+ jedec |= readb(global_qtest, ASPEED_FLASH_BASE) << 16;\n+ jedec |= readb(global_qtest, ASPEED_FLASH_BASE) << 8;\n+ jedec |= readb(global_qtest, ASPEED_FLASH_BASE);\n spi_ctrl_stop_user();\n\n flash_reset();\n@@ -160,13 +160,13 @@ static void read_page(uint32_t addr, uint32_t *page)\n\n spi_ctrl_start_user();\n\n- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n- writeb(ASPEED_FLASH_BASE, READ);\n- writel(ASPEED_FLASH_BASE, make_be32(addr));\n+ writeb(global_qtest, ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, READ);\n+ writel(global_qtest, ASPEED_FLASH_BASE, make_be32(addr));\n\n /* Continuous read are supported */\n for (i = 0; i < PAGE_SIZE / 4; i++) {\n- page[i] = make_be32(readl(ASPEED_FLASH_BASE));\n+ page[i] = make_be32(readl(global_qtest, ASPEED_FLASH_BASE));\n }\n spi_ctrl_stop_user();\n }\n@@ -179,7 +179,8 @@ static void read_page_mem(uint32_t addr, uint32_t *page)\n spi_ctrl_setmode(CTRL_READMODE, READ);\n\n for (i = 0; i < PAGE_SIZE / 4; i++) {\n- page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));\n+ page[i] = make_be32(readl(global_qtest,\n+ ASPEED_FLASH_BASE + addr + i * 4));\n }\n }\n\n@@ -192,10 +193,10 @@ static void test_erase_sector(void)\n spi_conf(CONF_ENABLE_W0);\n\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, WREN);\n- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n- writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);\n- writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));\n+ writeb(global_qtest, ASPEED_FLASH_BASE, WREN);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, ERASE_SECTOR);\n+ writel(global_qtest, ASPEED_FLASH_BASE, make_be32(some_page_addr));\n spi_ctrl_stop_user();\n\n /* Previous page should be full of zeroes as backend is not\n@@ -230,8 +231,8 @@ static void test_erase_all(void)\n }\n\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, WREN);\n- writeb(ASPEED_FLASH_BASE, BULK_ERASE);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, WREN);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, BULK_ERASE);\n spi_ctrl_stop_user();\n\n /* Recheck that some random page */\n@@ -253,14 +254,15 @@ static void test_write_page(void)\n spi_conf(CONF_ENABLE_W0);\n\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n- writeb(ASPEED_FLASH_BASE, WREN);\n- writeb(ASPEED_FLASH_BASE, PP);\n- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));\n+ writeb(global_qtest, ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, WREN);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, PP);\n+ writel(global_qtest, ASPEED_FLASH_BASE, make_be32(my_page_addr));\n\n /* Fill the page with its own addresses */\n for (i = 0; i < PAGE_SIZE / 4; i++) {\n- writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));\n+ writel(global_qtest, ASPEED_FLASH_BASE,\n+ make_be32(my_page_addr + i * 4));\n }\n spi_ctrl_stop_user();\n\n@@ -294,7 +296,7 @@ static void test_read_page_mem(void)\n /* Enable 4BYTE mode for flash. */\n spi_conf(CONF_ENABLE_W0);\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n spi_ctrl_stop_user();\n spi_conf_remove(CONF_ENABLE_W0);\n\n@@ -327,15 +329,15 @@ static void test_write_page_mem(void)\n /* Enable 4BYTE mode for flash. */\n spi_conf(CONF_ENABLE_W0);\n spi_ctrl_start_user();\n- writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n- writeb(ASPEED_FLASH_BASE, WREN);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, EN_4BYTE_ADDR);\n+ writeb(global_qtest, ASPEED_FLASH_BASE, WREN);\n spi_ctrl_stop_user();\n\n /* move out USER mode to use direct writes to the AHB bus */\n spi_ctrl_setmode(CTRL_WRITEMODE, PP);\n\n for (i = 0; i < PAGE_SIZE / 4; i++) {\n- writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,\n+ writel(global_qtest, ASPEED_FLASH_BASE + my_page_addr + i * 4,\n make_be32(my_page_addr + i * 4));\n }\n\ndiff --git a/tests/m48t59-test.c b/tests/m48t59-test.c\nindex 7ef3e2d26a..6218995d62 100644\n--- a/tests/m48t59-test.c\n+++ b/tests/m48t59-test.c\n@@ -32,14 +32,14 @@ static bool use_mmio;\n\n static uint8_t cmos_read_mmio(uint8_t reg)\n {\n- return readb(base + (uint32_t)reg_base + (uint32_t)reg);\n+ return readb(global_qtest, base + (uint32_t)reg_base + (uint32_t)reg);\n }\n\n static void cmos_write_mmio(uint8_t reg, uint8_t val)\n {\n uint8_t data = val;\n\n- writeb(base + (uint32_t)reg_base + (uint32_t)reg, data);\n+ writeb(global_qtest, base + (uint32_t)reg_base + (uint32_t)reg, data);\n }\n\n static uint8_t cmos_read_ioio(uint8_t reg)\ndiff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c\nindex 89fa6282d3..52a2cc2f82 100644\n--- a/tests/pnv-xscom-test.c\n+++ b/tests/pnv-xscom-test.c\n@@ -69,7 +69,7 @@ static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)\n\n static uint64_t pnv_xscom_read(const PnvChip *chip, uint32_t pcba)\n {\n- return readq(pnv_xscom_addr(chip, pcba));\n+ return readq(global_qtest, pnv_xscom_addr(chip, pcba));\n }\n\n static void test_xscom_cfam_id(const PnvChip *chip)\ndiff --git a/tests/prom-env-test.c b/tests/prom-env-test.c\nindex 0f8e6950fd..567d5a241d 100644\n--- a/tests/prom-env-test.c\n+++ b/tests/prom-env-test.c\n@@ -32,7 +32,7 @@ static void check_guest_memory(void)\n\n /* Poll until code has run and modified memory. Wait at most 120 seconds */\n for (i = 0; i < 12000; ++i) {\n- signature = readl(ADDRESS);\n+ signature = readl(global_qtest, ADDRESS);\n if (signature == MAGIC) {\n break;\n }\ndiff --git a/tests/q35-test.c b/tests/q35-test.c\nindex 4d90b9174e..fc2ecd43c9 100644\n--- a/tests/q35-test.c\n+++ b/tests/q35-test.c\n@@ -174,14 +174,14 @@ static void test_tseg_size(const void *data)\n */\n ram_offs = (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mbytes) *\n 1024 * 1024 - 1;\n- g_assert_cmpint(readb(ram_offs), ==, 0);\n- writeb(ram_offs, 1);\n- g_assert_cmpint(readb(ram_offs), ==, 1);\n+ g_assert_cmpint(readb(global_qtest, ram_offs), ==, 0);\n+ writeb(global_qtest, ram_offs, 1);\n+ g_assert_cmpint(readb(global_qtest, ram_offs), ==, 1);\n\n ram_offs++;\n- g_assert_cmpint(readb(ram_offs), ==, 0xff);\n- writeb(ram_offs, 1);\n- g_assert_cmpint(readb(ram_offs), ==, 0xff);\n+ g_assert_cmpint(readb(global_qtest, ram_offs), ==, 0xff);\n+ writeb(global_qtest, ram_offs, 1);\n+ g_assert_cmpint(readb(global_qtest, ram_offs), ==, 0xff);\n\n g_free(pcidev);\n qpci_free_pc(pcibus);\ndiff --git a/tests/tco-test.c b/tests/tco-test.c\nindex c2abbeeaac..1cf7362d83 100644\n--- a/tests/tco-test.c\n+++ b/tests/tco-test.c\n@@ -117,13 +117,13 @@ static void reset_on_second_timeout(bool enable)\n {\n uint32_t val;\n\n- val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);\n+ val = readl(global_qtest, RCBA_BASE_ADDR + ICH9_CC_GCS);\n if (enable) {\n val &= ~ICH9_CC_GCS_NO_REBOOT;\n } else {\n val |= ICH9_CC_GCS_NO_REBOOT;\n }\n- writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);\n+ writel(global_qtest, RCBA_BASE_ADDR + ICH9_CC_GCS, val);\n }\n\n static void test_tco_defaults(void)\ndiff --git a/tests/test-arm-mptimer.c b/tests/test-arm-mptimer.c\nindex 0e6484a4a8..0b6b514271 100644\n--- a/tests/test-arm-mptimer.c\n+++ b/tests/test-arm-mptimer.c\n@@ -38,7 +38,7 @@ static int scaled = 122;\n\n static void timer_load(uint32_t load)\n {\n- writel(TIMER_BASE_PHYS + TIMER_LOAD, load);\n+ writel(global_qtest, TIMER_BASE_PHYS + TIMER_LOAD, load);\n }\n\n static void timer_start(int periodic, uint32_t scale)\n@@ -49,17 +49,17 @@ static void timer_start(int periodic, uint32_t scale)\n ctl |= TIMER_CONTROL_PERIODIC;\n }\n\n- writel(TIMER_BASE_PHYS + TIMER_CONTROL, ctl);\n+ writel(global_qtest, TIMER_BASE_PHYS + TIMER_CONTROL, ctl);\n }\n\n static void timer_stop(void)\n {\n- writel(TIMER_BASE_PHYS + TIMER_CONTROL, 0);\n+ writel(global_qtest, TIMER_BASE_PHYS + TIMER_CONTROL, 0);\n }\n\n static void timer_int_clr(void)\n {\n- writel(TIMER_BASE_PHYS + TIMER_INTSTAT, 1);\n+ writel(global_qtest, TIMER_BASE_PHYS + TIMER_INTSTAT, 1);\n }\n\n static void timer_reset(void)\n@@ -71,7 +71,7 @@ static void timer_reset(void)\n\n static uint32_t timer_get_and_clr_int_sts(void)\n {\n- uint32_t int_sts = readl(TIMER_BASE_PHYS + TIMER_INTSTAT);\n+ uint32_t int_sts = readl(global_qtest, TIMER_BASE_PHYS + TIMER_INTSTAT);\n\n if (int_sts) {\n timer_int_clr();\n@@ -82,12 +82,12 @@ static uint32_t timer_get_and_clr_int_sts(void)\n\n static uint32_t timer_counter(void)\n {\n- return readl(TIMER_BASE_PHYS + TIMER_COUNTER);\n+ return readl(global_qtest, TIMER_BASE_PHYS + TIMER_COUNTER);\n }\n\n static void timer_set_counter(uint32_t value)\n {\n- writel(TIMER_BASE_PHYS + TIMER_COUNTER, value);\n+ writel(global_qtest, TIMER_BASE_PHYS + TIMER_COUNTER, value);\n }\n\n static void test_timer_oneshot(gconstpointer arg)\ndiff --git a/tests/vhost-user-test.c b/tests/vhost-user-test.c\nindex c205a9100a..580ad43fad 100644\n--- a/tests/vhost-user-test.c\n+++ b/tests/vhost-user-test.c\n@@ -241,7 +241,7 @@ static void read_guest_mem(const void *data)\n for (j = 0; j < 256; j++) {\n uint32_t a, b;\n\n- a = qtest_readl(s->qts,\n+ a = readl(s->qts,\n s->memory.regions[i].guest_phys_addr + j * 4);\n b = guest_mem[j];\n\ndiff --git a/tests/virtio-blk-test.c b/tests/virtio-blk-test.c\nindex 9594fbf437..5f8606ea80 100644\n--- a/tests/virtio-blk-test.c\n+++ b/tests/virtio-blk-test.c\n@@ -195,7 +195,7 @@ static void test_basic(QVirtioDevice *dev, QGuestAllocator *alloc,\n qvirtqueue_kick(dev, vq, free_head);\n\n qvirtio_wait_used_elem(dev, vq, free_head, QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n guest_free(alloc, req_addr);\n@@ -217,7 +217,7 @@ static void test_basic(QVirtioDevice *dev, QGuestAllocator *alloc,\n qvirtqueue_kick(dev, vq, free_head);\n\n qvirtio_wait_used_elem(dev, vq, free_head, QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n data = g_malloc0(512);\n@@ -245,7 +245,7 @@ static void test_basic(QVirtioDevice *dev, QGuestAllocator *alloc,\n qvirtqueue_kick(dev, vq, free_head);\n\n qvirtio_wait_used_elem(dev, vq, free_head, QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n guest_free(alloc, req_addr);\n@@ -266,7 +266,7 @@ static void test_basic(QVirtioDevice *dev, QGuestAllocator *alloc,\n qvirtqueue_kick(dev, vq, free_head);\n\n qvirtio_wait_used_elem(dev, vq, free_head, QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n data = g_malloc0(512);\n@@ -350,7 +350,7 @@ static void pci_indirect(void)\n\n qvirtio_wait_used_elem(&dev->vdev, &vqpci->vq, free_head,\n QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n g_free(indirect);\n@@ -376,7 +376,7 @@ static void pci_indirect(void)\n\n qvirtio_wait_used_elem(&dev->vdev, &vqpci->vq, free_head,\n QVIRTIO_BLK_TIMEOUT_US);\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n data = g_malloc0(512);\n@@ -488,7 +488,7 @@ static void pci_msix(void)\n qvirtio_wait_used_elem(&dev->vdev, &vqpci->vq, free_head,\n QVIRTIO_BLK_TIMEOUT_US);\n\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n guest_free(qs->alloc, req_addr);\n@@ -513,7 +513,7 @@ static void pci_msix(void)\n qvirtio_wait_used_elem(&dev->vdev, &vqpci->vq, free_head,\n QVIRTIO_BLK_TIMEOUT_US);\n\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n data = g_malloc0(512);\n@@ -636,7 +636,7 @@ static void pci_idx(void)\n g_assert(qvirtqueue_get_buf(&vqpci->vq, &desc_idx));\n g_assert_cmpint(desc_idx, ==, free_head);\n\n- status = readb(req_addr + 528);\n+ status = readb(global_qtest, req_addr + 528);\n g_assert_cmpint(status, ==, 0);\n\n data = g_malloc0(512);\ndiff --git a/tests/virtio-scsi-test.c b/tests/virtio-scsi-test.c\nindex 4d544ddbc3..30a341df2f 100644\n--- a/tests/virtio-scsi-test.c\n+++ b/tests/virtio-scsi-test.c\n@@ -125,7 +125,7 @@ static uint8_t virtio_scsi_do_command(QVirtIOSCSI *vs, const uint8_t *cdb,\n qvirtqueue_kick(vs->dev, vq, free_head);\n qvirtio_wait_used_elem(vs->dev, vq, free_head, QVIRTIO_SCSI_TIMEOUT_US);\n\n- response = readb(resp_addr +\n+ response = readb(global_qtest, resp_addr +\n offsetof(struct virtio_scsi_cmd_resp, response));\n\n if (resp_out) {\ndiff --git a/tests/vmgenid-test.c b/tests/vmgenid-test.c\nindex 108a5d9a6e..aab7760bee 100644\n--- a/tests/vmgenid-test.c\n+++ b/tests/vmgenid-test.c\n@@ -105,7 +105,7 @@ static void read_guid_from_memory(QemuUUID *guid)\n\n /* Read the GUID directly from guest memory */\n for (i = 0; i < 16; i++) {\n- guid->data[i] = readb(vmgenid_addr + i);\n+ guid->data[i] = readb(global_qtest, vmgenid_addr + i);\n }\n /* The GUID is in little-endian format in the guest, while QEMU\n * uses big-endian. Swap after reading.\n", "prefixes": [ "v7", "34/38" ] }