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GET /api/patches/812484/?format=api
{ "id": 812484, "url": "http://patchwork.ozlabs.org/api/patches/812484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-16-eblake@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170911172022.4738-16-eblake@redhat.com>", "list_archive_url": null, "date": "2017-09-11T17:19:59", "name": "[v7,15/38] libqos: Use explicit QTestState for i2c operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b2e92a7695c69db9fd8a67eeb142434df6a78e43", "submitter": { "id": 6591, "url": "http://patchwork.ozlabs.org/api/people/6591/?format=api", "name": "Eric Blake", "email": "eblake@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-16-eblake@redhat.com/mbox/", "series": [ { "id": 2534, "url": "http://patchwork.ozlabs.org/api/series/2534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2534", "date": "2017-09-11T17:19:47", "name": "Preliminary libqtest cleanups", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/2534/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812484/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812484/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com", "ext-mx03.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=eblake@redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZmn6RRSz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 03:34:33 +1000 (AEST)", "from localhost ([::1]:59386 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drSbP-0002v4-Td\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:34:31 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38432)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSOK-0007Gk-2r\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:21:05 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSOI-0001BY-75\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:21:00 -0400", "from mx1.redhat.com ([209.132.183.28]:55102)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <eblake@redhat.com>) id 1drSOH-0001BB-VU\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:20:58 -0400", "from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 1827C11A28D\n\tfor <qemu-devel@nongnu.org>; Mon, 11 Sep 2017 17:20:57 +0000 (UTC)", "from red.redhat.com (ovpn-120-44.rdu2.redhat.com [10.10.120.44])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 420F45D9CA;\n\tMon, 11 Sep 2017 17:20:56 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mx1.redhat.com 1827C11A28D", "From": "Eric Blake <eblake@redhat.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 11 Sep 2017 12:19:59 -0500", "Message-Id": "<20170911172022.4738-16-eblake@redhat.com>", "In-Reply-To": "<20170911172022.4738-1-eblake@redhat.com>", "References": "<20170911172022.4738-1-eblake@redhat.com>", "X-Scanned-By": "MIMEDefang 2.79 on 10.5.11.14", "X-Greylist": "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.27]);\n\tMon, 11 Sep 2017 17:20:57 +0000 (UTC)", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "209.132.183.28", "Subject": "[Qemu-devel] [PATCH v7 15/38] libqos: Use explicit QTestState for\n\ti2c operations", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "pbonzini@redhat.com, thuth@redhat.com, armbru@redhat.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Drop one more client of global_qtest by teaching all i2c test\nfunctionality to pass in an explicit QTestState, adjusting all\ncallers.\n\nSigned-off-by: Eric Blake <eblake@redhat.com>\n---\n tests/libqos/i2c.h | 7 ++++--\n tests/ds1338-test.c | 6 ++---\n tests/libqos/i2c-imx.c | 67 +++++++++++++++++++++++++------------------------\n tests/libqos/i2c-omap.c | 45 +++++++++++++++++----------------\n tests/tmp105-test.c | 6 ++---\n 5 files changed, 66 insertions(+), 65 deletions(-)", "diff": "diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h\nindex 6e648f922a..eb40b808bd 100644\n--- a/tests/libqos/i2c.h\n+++ b/tests/libqos/i2c.h\n@@ -9,6 +9,7 @@\n #ifndef LIBQOS_I2C_H\n #define LIBQOS_I2C_H\n\n+#include \"libqtest.h\"\n\n typedef struct I2CAdapter I2CAdapter;\n struct I2CAdapter {\n@@ -16,6 +17,8 @@ struct I2CAdapter {\n const uint8_t *buf, uint16_t len);\n void (*recv)(I2CAdapter *adapter, uint8_t addr,\n uint8_t *buf, uint16_t len);\n+\n+ QTestState *qts;\n };\n\n void i2c_send(I2CAdapter *i2c, uint8_t addr,\n@@ -24,9 +27,9 @@ void i2c_recv(I2CAdapter *i2c, uint8_t addr,\n uint8_t *buf, uint16_t len);\n\n /* libi2c-omap.c */\n-I2CAdapter *omap_i2c_create(uint64_t addr);\n+I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr);\n\n /* libi2c-imx.c */\n-I2CAdapter *imx_i2c_create(uint64_t addr);\n+I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr);\n\n #endif\ndiff --git a/tests/ds1338-test.c b/tests/ds1338-test.c\nindex 26968bc82a..742dad9113 100644\n--- a/tests/ds1338-test.c\n+++ b/tests/ds1338-test.c\n@@ -61,16 +61,14 @@ int main(int argc, char **argv)\n g_test_init(&argc, &argv, NULL);\n\n s = qtest_start(\"-display none -machine imx25-pdk\");\n- i2c = imx_i2c_create(IMX25_I2C_0_BASE);\n+ i2c = imx_i2c_create(s, IMX25_I2C_0_BASE);\n addr = DS1338_ADDR;\n\n qtest_add_func(\"/ds1338/tx-rx\", send_and_receive);\n\n ret = g_test_run();\n\n- if (s) {\n- qtest_quit(s);\n- }\n+ qtest_quit(s);\n g_free(i2c);\n\n return ret;\ndiff --git a/tests/libqos/i2c-imx.c b/tests/libqos/i2c-imx.c\nindex 1c4b4314ba..0945f2ecdc 100644\n--- a/tests/libqos/i2c-imx.c\n+++ b/tests/libqos/i2c-imx.c\n@@ -40,8 +40,8 @@ typedef struct IMXI2C {\n static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr,\n enum IMXI2CDirection direction)\n {\n- writeb(s->addr + I2DR_ADDR, (addr << 1) |\n- (direction == IMX_I2C_READ ? 1 : 0));\n+ qtest_writeb(s->parent.qts, s->addr + I2DR_ADDR,\n+ (addr << 1) | (direction == IMX_I2C_READ ? 1 : 0));\n }\n\n static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n@@ -63,35 +63,35 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n I2CR_MTX |\n I2CR_TXAK;\n\n- writeb(s->addr + I2CR_ADDR, data);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* set the slave address */\n imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE);\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- writeb(s->addr + I2SR_ADDR, 0);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n while (size < len) {\n /* check we are still busy */\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* write the data */\n- writeb(s->addr + I2DR_ADDR, buf[size]);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2DR_ADDR, buf[size]);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- writeb(s->addr + I2SR_ADDR, 0);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n size++;\n@@ -99,8 +99,8 @@ static void imx_i2c_send(I2CAdapter *i2c, uint8_t addr,\n\n /* release the bus */\n data &= ~(I2CR_MSTA | I2CR_MTX);\n- writeb(s->addr + I2CR_ADDR, data);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) == 0);\n }\n\n@@ -123,19 +123,19 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n I2CR_MTX |\n I2CR_TXAK;\n\n- writeb(s->addr + I2CR_ADDR, data);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* set the slave address */\n imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ);\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n g_assert((status & I2SR_RXAK) == 0);\n\n /* ack the interrupt */\n- writeb(s->addr + I2SR_ADDR, 0);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n /* set the bus for read */\n@@ -144,23 +144,23 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n if (len != 1) {\n data &= ~I2CR_TXAK;\n }\n- writeb(s->addr + I2CR_ADDR, data);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n /* dummy read */\n- readb(s->addr + I2DR_ADDR);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_readb(i2c->qts, s->addr + I2DR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n\n /* ack the interrupt */\n- writeb(s->addr + I2SR_ADDR, 0);\n- status = readb(s->addr + I2SR_ADDR);\n+ qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n while (size < len) {\n /* check we are still busy */\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) != 0);\n\n if (size == (len - 1)) {\n@@ -170,30 +170,30 @@ static void imx_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n /* ack the data read */\n data |= I2CR_TXAK;\n }\n- writeb(s->addr + I2CR_ADDR, data);\n+ qtest_writeb(i2c->qts, s->addr + I2CR_ADDR, data);\n\n /* read the data */\n- buf[size] = readb(s->addr + I2DR_ADDR);\n+ buf[size] = qtest_readb(i2c->qts, s->addr + I2DR_ADDR);\n\n if (size != (len - 1)) {\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) != 0);\n\n /* ack the interrupt */\n- writeb(s->addr + I2SR_ADDR, 0);\n+ qtest_writeb(i2c->qts, s->addr + I2SR_ADDR, 0);\n }\n\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IIF) == 0);\n\n size++;\n }\n\n- status = readb(s->addr + I2SR_ADDR);\n+ status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);\n g_assert((status & I2SR_IBB) == 0);\n }\n\n-I2CAdapter *imx_i2c_create(uint64_t addr)\n+I2CAdapter *imx_i2c_create(QTestState *qts, uint64_t addr)\n {\n IMXI2C *s = g_malloc0(sizeof(*s));\n I2CAdapter *i2c = (I2CAdapter *)s;\n@@ -202,6 +202,7 @@ I2CAdapter *imx_i2c_create(uint64_t addr)\n\n i2c->send = imx_i2c_send;\n i2c->recv = imx_i2c_recv;\n+ i2c->qts = qts;\n\n return i2c;\n }\ndiff --git a/tests/libqos/i2c-omap.c b/tests/libqos/i2c-omap.c\nindex f603fdf43c..1ef6e7b200 100644\n--- a/tests/libqos/i2c-omap.c\n+++ b/tests/libqos/i2c-omap.c\n@@ -51,8 +51,8 @@ static void omap_i2c_set_slave_addr(OMAPI2C *s, uint8_t addr)\n {\n uint16_t data = addr;\n\n- writew(s->addr + OMAP_I2C_SA, data);\n- data = readw(s->addr + OMAP_I2C_SA);\n+ qtest_writew(s->parent.qts, s->addr + OMAP_I2C_SA, data);\n+ data = qtest_readw(s->parent.qts, s->addr + OMAP_I2C_SA);\n g_assert_cmphex(data, ==, addr);\n }\n\n@@ -65,38 +65,38 @@ static void omap_i2c_send(I2CAdapter *i2c, uint8_t addr,\n omap_i2c_set_slave_addr(s, addr);\n\n data = len;\n- writew(s->addr + OMAP_I2C_CNT, data);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n\n data = OMAP_I2C_CON_I2C_EN |\n OMAP_I2C_CON_TRX |\n OMAP_I2C_CON_MST |\n OMAP_I2C_CON_STT |\n OMAP_I2C_CON_STP;\n- writew(s->addr + OMAP_I2C_CON, data);\n- data = readw(s->addr + OMAP_I2C_CON);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) != 0);\n\n- data = readw(s->addr + OMAP_I2C_STAT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_NACK) == 0);\n\n while (len > 1) {\n- data = readw(s->addr + OMAP_I2C_STAT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_XRDY) != 0);\n\n data = buf[0] | ((uint16_t)buf[1] << 8);\n- writew(s->addr + OMAP_I2C_DATA, data);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n buf = (uint8_t *)buf + 2;\n len -= 2;\n }\n if (len == 1) {\n- data = readw(s->addr + OMAP_I2C_STAT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_XRDY) != 0);\n\n data = buf[0];\n- writew(s->addr + OMAP_I2C_DATA, data);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_DATA, data);\n }\n\n- data = readw(s->addr + OMAP_I2C_CON);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n }\n\n@@ -109,30 +109,30 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n omap_i2c_set_slave_addr(s, addr);\n\n data = len;\n- writew(s->addr + OMAP_I2C_CNT, data);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_CNT, data);\n\n data = OMAP_I2C_CON_I2C_EN |\n OMAP_I2C_CON_MST |\n OMAP_I2C_CON_STT |\n OMAP_I2C_CON_STP;\n- writew(s->addr + OMAP_I2C_CON, data);\n- data = readw(s->addr + OMAP_I2C_CON);\n+ qtest_writew(i2c->qts, s->addr + OMAP_I2C_CON, data);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n\n- data = readw(s->addr + OMAP_I2C_STAT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_NACK) == 0);\n\n- data = readw(s->addr + OMAP_I2C_CNT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CNT);\n g_assert_cmpuint(data, ==, len);\n\n while (len > 0) {\n- data = readw(s->addr + OMAP_I2C_STAT);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n g_assert((data & OMAP_I2C_STAT_RRDY) != 0);\n g_assert((data & OMAP_I2C_STAT_ROVR) == 0);\n\n- data = readw(s->addr + OMAP_I2C_DATA);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_DATA);\n\n- stat = readw(s->addr + OMAP_I2C_STAT);\n+ stat = qtest_readw(i2c->qts, s->addr + OMAP_I2C_STAT);\n\n if (unlikely(len == 1)) {\n g_assert((stat & OMAP_I2C_STAT_SBD) != 0);\n@@ -148,11 +148,11 @@ static void omap_i2c_recv(I2CAdapter *i2c, uint8_t addr,\n }\n }\n\n- data = readw(s->addr + OMAP_I2C_CON);\n+ data = qtest_readw(i2c->qts, s->addr + OMAP_I2C_CON);\n g_assert((data & OMAP_I2C_CON_STP) == 0);\n }\n\n-I2CAdapter *omap_i2c_create(uint64_t addr)\n+I2CAdapter *omap_i2c_create(QTestState *qts, uint64_t addr)\n {\n OMAPI2C *s = g_malloc0(sizeof(*s));\n I2CAdapter *i2c = (I2CAdapter *)s;\n@@ -162,9 +162,10 @@ I2CAdapter *omap_i2c_create(uint64_t addr)\n\n i2c->send = omap_i2c_send;\n i2c->recv = omap_i2c_recv;\n+ i2c->qts = qts;\n\n /* verify the mmio address by looking for a known signature */\n- data = readw(addr + OMAP_I2C_REV);\n+ data = qtest_readw(qts, addr + OMAP_I2C_REV);\n g_assert_cmphex(data, ==, 0x34);\n\n return i2c;\ndiff --git a/tests/tmp105-test.c b/tests/tmp105-test.c\nindex a7940a4639..382f88ba23 100644\n--- a/tests/tmp105-test.c\n+++ b/tests/tmp105-test.c\n@@ -154,15 +154,13 @@ int main(int argc, char **argv)\n s = qtest_start(\"-machine n800 \"\n \"-device tmp105,bus=i2c-bus.0,id=\" TMP105_TEST_ID\n \",address=0x49\");\n- i2c = omap_i2c_create(OMAP2_I2C_1_BASE);\n+ i2c = omap_i2c_create(s, OMAP2_I2C_1_BASE);\n\n qtest_add_func(\"/tmp105/tx-rx\", send_and_receive);\n\n ret = g_test_run();\n\n- if (s) {\n- qtest_quit(s);\n- }\n+ qtest_quit(s);\n g_free(i2c);\n\n return ret;\n", "prefixes": [ "v7", "15/38" ] }