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GET /api/patches/811862/?format=api
{ "id": 811862, "url": "http://patchwork.ozlabs.org/api/patches/811862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-7-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504910713-7094-7-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504910713-7094-7-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-08T22:44:46", "name": "[6/7] powerpc: use helper functions to get and set hash slots", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "02cecde0287c0877f22edb6634082384d03421ed", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-7-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 2303, "url": "http://patchwork.ozlabs.org/api/series/2303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2303", "date": "2017-09-08T22:44:40", "name": "powerpc: Free up RPAGE_RSV bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811862/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpt703V86z9t16\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:59:24 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpt702Fc2zDrZ3\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:59:24 +1000 (AEST)", "from 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helper functions to get and set hash slots", "Date": "Fri, 8 Sep 2017 15:44:46 -0700", "Message-Id": "<1504910713-7094-7-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "References": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "replace redundant code in __hash_page_4K() and flush_hash_page()\nwith helper functions pte_get_hash_gslot() and pte_set_hash_slot()\n\nReviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n arch/powerpc/mm/hash64_4k.c | 14 ++++++--------\n arch/powerpc/mm/hash_utils_64.c | 13 ++++---------\n 2 files changed, 10 insertions(+), 17 deletions(-)", "diff": "diff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c\nindex 6fa450c..a1eebc1 100644\n--- a/arch/powerpc/mm/hash64_4k.c\n+++ b/arch/powerpc/mm/hash64_4k.c\n@@ -20,6 +20,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t pte_t *ptep, unsigned long trap, unsigned long flags,\n \t\t int ssize, int subpg_prot)\n {\n+\treal_pte_t rpte;\n \tunsigned long hpte_group;\n \tunsigned long rflags, pa;\n \tunsigned long old_pte, new_pte;\n@@ -54,6 +55,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t * need to add in 0x1 if it's a read-only user page\n \t */\n \trflags = htab_convert_pte_flags(new_pte);\n+\trpte = __real_pte(__pte(old_pte), ptep);\n \n \tif (cpu_has_feature(CPU_FTR_NOEXECUTE) &&\n \t !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))\n@@ -64,13 +66,10 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t/*\n \t\t * There MIGHT be an HPTE for this pte\n \t\t */\n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n+\t\tunsigned long gslot = pte_get_hash_gslot(vpn, shift,\n+\t\t\t\t\t\tssize, rpte, 0);\n \n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_4K,\n+\t\tif (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, MMU_PAGE_4K,\n \t\t\t\t\t MMU_PAGE_4K, ssize, flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\n \t}\n@@ -118,8 +117,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\treturn -1;\n \t\t}\n \t\tnew_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;\n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n+\t\tnew_pte |= pte_set_hash_slot(ptep, rpte, 0, slot);\n \t}\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\ndiff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\nindex a40c7bc..0dff57b 100644\n--- a/arch/powerpc/mm/hash_utils_64.c\n+++ b/arch/powerpc/mm/hash_utils_64.c\n@@ -1617,23 +1617,18 @@ unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,\n void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,\n \t\t unsigned long flags)\n {\n-\tunsigned long hash, index, shift, hidx, slot;\n+\tunsigned long index, shift, gslot;\n \tint local = flags & HPTE_LOCAL_UPDATE;\n \n \tDBG_LOW(\"flush_hash_page(vpn=%016lx)\\n\", vpn);\n \tpte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {\n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\thidx = __rpte_to_hidx(pte, index);\n-\t\tif (hidx & _PTEIDX_SECONDARY)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += hidx & _PTEIDX_GROUP_IX;\n-\t\tDBG_LOW(\" sub %ld: hash=%lx, hidx=%lx\\n\", index, slot, hidx);\n+\t\tgslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);\n+\t\tDBG_LOW(\" sub %ld: gslot=%lx\\n\", index, gslot);\n \t\t/*\n \t\t * We use same base page size and actual psize, because we don't\n \t\t * use these functions for hugepage\n \t\t */\n-\t\tmmu_hash_ops.hpte_invalidate(slot, vpn, psize, psize,\n+\t\tmmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,\n \t\t\t\t\t ssize, local);\n \t} pte_iterate_hashed_end();\n \n", "prefixes": [ "6/7" ] }