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GET /api/patches/811861/?format=api
{ "id": 811861, "url": "http://patchwork.ozlabs.org/api/patches/811861/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-6-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504910713-7094-6-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504910713-7094-6-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-08T22:44:45", "name": "[5/7] powerpc: Swizzle around 4K PTE bits to free up bit 5 and bit 6", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "67fbad9e81162bd4d4d876d7a66bb9a3bd2f7120", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-6-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 2303, "url": "http://patchwork.ozlabs.org/api/series/2303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2303", "date": "2017-09-08T22:44:40", "name": "powerpc: Free up RPAGE_RSV bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811861/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpt4r4WM3z9s7v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:57:32 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpt4r3GQ5zDqYy\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:57:32 +1000 (AEST)", "from mail-qt0-x242.google.com (mail-qt0-x242.google.com\n\t[IPv6:2607:f8b0:400d:c0d::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpsrF3XSszDrcy\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Sep 2017 08:46:37 +1000 (AEST)", "by mail-qt0-x242.google.com with SMTP id b1so14399qtc.0\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Sep 2017 15:46:37 -0700 (PDT)", "from localhost.localdomain (50-39-103-96.bvtn.or.frontiernet.net.\n\t[50.39.103.96]) by smtp.gmail.com with ESMTPSA id\n\tx124sm2033726qka.85.2017.09.08.15.46.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 15:46:35 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"QOcHXFt/\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"QOcHXFt/\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400d:c0d::242; helo=mail-qt0-x242.google.com;\n\tenvelope-from=ram.n.pai@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"QOcHXFt/\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=YNphfQxTEd8BrOjOvjSAhjWncRhztJRvuULmEp2tduc=;\n\tb=QOcHXFt/0gYRThqAiiVKsJRuuPC8bs3/ANTXWGfn5/IoBv1bgXBHk/ptN8I/6/uF0i\n\trNV7/CAR0N1slZcXWzh5yxi/SenmjHPWvZ/ElV3lJxRkiQYeyFo0qCJAx9d96aOW3Ddb\n\tnO40LNSveolGyAMgjKgiz4uT3ujscyHPxqObNFyByTh49Kx8Z8ITTBNcy6/SQ8IBTGmg\n\tzi3OKyLQ1F8Ga+K5jgkHogcrQOvjnzuddNuLb3Ifd3OH3qwo+MDywK7O0CBzBy835KnK\n\tmTD0J9zpf3t0A+EuzCcd1BGVKmBkDb49wM9s6B+KvqOhzGXCWOF0OGNJ4Bl72b3kYXlv\n\t8W/w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=YNphfQxTEd8BrOjOvjSAhjWncRhztJRvuULmEp2tduc=;\n\tb=uMQvo350l8QC6ZxO8NqgF6B12so2Tg92XLA/WU6PZZMre8SP9xEEh2NdIao1DpDxFo\n\tId4jy/bBoNg94aaoz5SCoy2xqeO3ppV/+A0M8xtKRIyuiRGaV6u5XRESeCXvmUEvOeYg\n\tDWvyLqeqp6YOO5A/6ishyt2KGgnJSTPvgdELlyNSUHjBNS4mchpitYnL89qFu3vGO2Yi\n\tVMya+I306ljgrK87XsjqXWxbukvJ9wPsiYl/IlxCvZvKp4daAre2xZTMI92E9vVqlCe9\n\t0x+/2WO0EDEio94N2/irasyRTF6GxBC0LOhTNgMi+4c65aatvogTXAZ4fJtqgGam9cT1\n\tQaww==", "X-Gm-Message-State": "AHPjjUgZ1+zP1oG6PoQqMHf81NCiC4TBMLJ9cgvhXVxqcNasJYF/CTXv\n\t2EYs6VrbVMDh7mYB", "X-Google-Smtp-Source": "AOwi7QBPqRJS/vIEWDSeq9GDgfAQZURN8Vk8YAXjt+c1XMGCWa3yJA/N9kmqxB/hPo4scSNWeqyBgQ==", "X-Received": "by 10.200.12.68 with SMTP id l4mr6603934qti.340.1504910795553;\n\tFri, 08 Sep 2017 15:46:35 -0700 (PDT)", "From": "Ram Pai <linuxram@us.ibm.com>", "To": "mpe@ellerman.id.au,\n\tlinuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 5/7] powerpc: Swizzle around 4K PTE bits to free up bit 5 and\n\tbit 6", "Date": "Fri, 8 Sep 2017 15:44:45 -0700", "Message-Id": "<1504910713-7094-6-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "References": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "We need PTE bits 3 ,4, 5, 6 and 57 to support protection-keys,\nbecause these are the bits we want to consolidate on across all\nconfiguration to support protection keys.\n\nBit 3,4,5 and 6 are currently used on 4K-pte kernels. But bit 9\nand 10 are available. Hence we use the two available bits and\nfree up bit 5 and 6. We will still not be able to free up bit 3\nand 4. In the absence of any other free bits, we will have to\nstay satisfied with what we have :-(. This means we will not\nbe able to support 32 protection keys, but only 8. The bit\nnumbers are big-endian as defined in the ISA3.0\n\nThis patch does the following change to 4K PTE.\n\nH_PAGE_F_SECOND (S) which occupied bit 4 moves to bit 7.\nH_PAGE_F_GIX (G,I,X) which occupied bit 5, 6 and 7 also moves\nto bit 8,9, 10 respectively.\nH_PAGE_HASHPTE (H) which occupied bit 8 moves to bit 4.\n\nBefore the patch, the 4k PTE format was as follows\n\n 0 1 2 3 4 5 6 7 8 9 10....................57.....63\n : : : : : : : : : : : : :\n v v v v v v v v v v v v v\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x|B|S |G |I |X |H| | |x|x|................| |x|x|x|\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n\nAfter the patch, the 4k PTE format is as follows\n\n 0 1 2 3 4 5 6 7 8 9 10....................57.....63\n : : : : : : : : : : : : :\n v v v v v v v v v v v v v\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x|B|H | | |S |G|I|X|x|x|................| |.|.|.|\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n\nThe patch has no code changes; just swizzles around bits.\n\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/hash-4k.h | 7 ++++---\n arch/powerpc/include/asm/book3s/64/hash-64k.h | 1 +\n arch/powerpc/include/asm/book3s/64/hash.h | 1 -\n 3 files changed, 5 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\nindex dc153c6..5187249 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n@@ -16,10 +16,11 @@\n #define H_PUD_TABLE_SIZE\t(sizeof(pud_t) << H_PUD_INDEX_SIZE)\n #define H_PGD_TABLE_SIZE\t(sizeof(pgd_t) << H_PGD_INDEX_SIZE)\n \n-#define H_PAGE_F_GIX_SHIFT\t56\n-#define H_PAGE_F_SECOND\t_RPAGE_RSV2\t/* HPTE is in 2ndary HPTEG */\n-#define H_PAGE_F_GIX\t(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)\n+#define H_PAGE_F_GIX_SHIFT\t53\n+#define H_PAGE_F_SECOND\t_RPAGE_RPN44\t/* HPTE is in 2ndary HPTEG */\n+#define H_PAGE_F_GIX\t(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)\n #define H_PAGE_BUSY\t_RPAGE_RSV1 /* software: PTE & hash are busy */\n+#define H_PAGE_HASHPTE\t_RPAGE_RSV2 /* software: PTE & hash are busy */\n \n /* PTE flags to conserve for HPTE identification */\n #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \\\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\nindex 89ef5a9..8576060 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n@@ -13,6 +13,7 @@\n #define H_PAGE_COMBO\t_RPAGE_RPN0 /* this is a combo 4k page */\n #define H_PAGE_4K_PFN\t_RPAGE_RPN1 /* PFN is for a single 4k page */\n #define H_PAGE_BUSY\t_RPAGE_RPN44 /* software: PTE & hash are busy */\n+#define H_PAGE_HASHPTE\t_RPAGE_RPN43\t/* PTE has associated HPTE */\n \n /*\n * We need to differentiate between explicit huge page and THP huge\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\nindex 46f3a23..953795e 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash.h\n@@ -8,7 +8,6 @@\n *\n */\n #define H_PTE_NONE_MASK\t\t_PAGE_HPTEFLAGS\n-#define H_PAGE_HASHPTE\t\t_RPAGE_RPN43\t/* PTE has associated HPTE */\n \n #ifdef CONFIG_PPC_64K_PAGES\n #include <asm/book3s/64/hash-64k.h>\n", "prefixes": [ "5/7" ] }