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GET /api/patches/811860/?format=api
{ "id": 811860, "url": "http://patchwork.ozlabs.org/api/patches/811860/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-5-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504910713-7094-5-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504910713-7094-5-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-08T22:44:44", "name": "[4/7] powerpc: Free up four 64K PTE bits in 64K backed HPTE pages", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d0f9b06ebf443bbee04bde5f645ba0918ee560e7", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-5-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 2303, "url": "http://patchwork.ozlabs.org/api/series/2303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2303", "date": "2017-09-08T22:44:40", "name": "powerpc: Free up RPAGE_RSV bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811860/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811860/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpt2N0FPxz9s7v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:55:24 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpt2M5yFqzDqZ7\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:55:23 +1000 (AEST)", "from mail-qt0-x243.google.com (mail-qt0-x243.google.com\n\t[IPv6:2607:f8b0:400d:c0d::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpsrC6ZGTzDrcw\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Sep 2017 08:46:35 +1000 (AEST)", "by mail-qt0-x243.google.com with SMTP id q8so2359726qtb.1\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Sep 2017 15:46:35 -0700 (PDT)", "from localhost.localdomain (50-39-103-96.bvtn.or.frontiernet.net.\n\t[50.39.103.96]) by smtp.gmail.com with ESMTPSA id\n\tx124sm2033726qka.85.2017.09.08.15.46.32\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 15:46:33 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"AGbUKZTc\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"AGbUKZTc\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400d:c0d::243; helo=mail-qt0-x243.google.com;\n\tenvelope-from=ram.n.pai@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"AGbUKZTc\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=+BZigg/SxKt0JwfVoORywRKiRqZ8SOSJrxdMAOxGdig=;\n\tb=AGbUKZTc5Hr1X9LaTNH3kCPS+T0Ybgk3RQ5L0A/QBKRMb151omfVF8zQPuqVOvu8ha\n\tTmIs1HOBW0zsdL8I9fboOzAyR1AVnQ6G+7m4+kq7cxuEfuXltqQ9xt1a6VMp7twNSNoZ\n\tzKCt1fsXe/rIGV4ojtBMcUe4vsm1vRIoFdPBux9BP9ufHQOfDe/jz0iCPssbl7jQ7EiN\n\tBuO845P5Tac0ml58m9WeAxfLP7NPzfd6P4gZO/GbTQ6fuxtJWDjHqt2KKH8/lOwnaDPK\n\twK6eGfczDjPDufYDP7g4gfj0JzvhfIQY+xTMeVSwqHTmlb68omZsyRDx8r6XfsI7TZG0\n\tgX4g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=+BZigg/SxKt0JwfVoORywRKiRqZ8SOSJrxdMAOxGdig=;\n\tb=CsIBZwkufMG+oGSoAfwFdovn8RjD7kc3GoynmhHUV4XQ2hcUeIY15dUkwVUmufPrKP\n\tJGqs008szwRxr1gorEz0lW/3C3F4gOFOkB04mb/q5j1w1sK9OZ/65GAZC0TppKVN7uyt\n\tXOa+1sxyaq97phvveKlbzx136RVW4qdwCLNRv2jH6HqAQ+p5RW0tvlJdqDhVYS8oC+WY\n\txkBABhZREtPXaxOHvI8EInYpDN94qeiUHprlFHuMojNuuPIFo9JYqN4RSn5ohGxUyjb6\n\tYX66cJ5xAm0duHH2xwdMoQecot0qqCCd10Z+IucGwQUFxh2m+rawrfgNYi2SBNrdBiLY\n\tiwcQ==", "X-Gm-Message-State": "AHPjjUjzuLrhLX4kQZH+C7tb+dwTDJI0bTxiqV78zpDc+kotMr6XsJ1p\n\thN2Fb0vYP4G+4g==", "X-Google-Smtp-Source": "AOwi7QDXfoyZdpiHjBhEcPOoYLgIDH3mGKXfyG2lWQ4te42nlpcS3x4itWoxcHUYa5HVJWcAGdGdqw==", "X-Received": "by 10.200.28.123 with SMTP id j56mr6043597qtk.299.1504910793827; \n\tFri, 08 Sep 2017 15:46:33 -0700 (PDT)", "From": "Ram Pai <linuxram@us.ibm.com>", "To": "mpe@ellerman.id.au,\n\tlinuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 4/7] powerpc: Free up four 64K PTE bits in 64K backed HPTE\n\tpages", "Date": "Fri, 8 Sep 2017 15:44:44 -0700", "Message-Id": "<1504910713-7094-5-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "References": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6\nin the 64K backed HPTE pages. This along with the earlier\npatch will entirely free up the four bits from 64K PTE.\nThe bit numbers are big-endian as defined in the ISA3.0\n\nThis patch does the following change to 64K PTE backed\nby 64K HPTE.\n\nH_PAGE_F_SECOND (S) which occupied bit 4 moves to the\n\tsecond part of the pte to bit 60.\nH_PAGE_F_GIX (G,I,X) which occupied bit 5, 6 and 7 also\n\tmoves to the second part of the pte to bit 61,\n \t62, 63, 64 respectively\n\nsince bit 7 is now freed up, we move H_PAGE_BUSY (B) from\nbit 9 to bit 7.\n\nThe second part of the PTE will hold\n(H_PAGE_F_SECOND|H_PAGE_F_GIX) at bit 60,61,62,63.\nNOTE: None of the bits in the secondary PTE were not used\nby 64k-HPTE backed PTE.\n\nBefore the patch, the 64K HPTE backed 64k PTE format was\nas follows\n\n 0 1 2 3 4 5 6 7 8 9 10...........................63\n : : : : : : : : : : : :\n v v v v v v v v v v v v\n\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x| |S |G |I |X |x|B| |x|x|................|x|x|x|x| <- primary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n| | | | | | | | | | | | |..................| | | | | <- secondary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'__________________'_'_'_'_'\n\nAfter the patch, the 64k HPTE backed 64k PTE format is\nas follows\n\n 0 1 2 3 4 5 6 7 8 9 10...........................63\n : : : : : : : : : : : :\n v v v v v v v v v v v v\n\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x| | | | |B |x| | |x|x|................|.|.|.|.| <- primary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n| | | | | | | | | | | | |..................|S|G|I|X| <- secondary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'__________________'_'_'_'_'\n\nThe above PTE changes is applicable to hugetlbpages aswell.\n\nThe patch does the following code changes:\n\na) moves the H_PAGE_F_SECOND and H_PAGE_F_GIX to 4k PTE\n\theader since it is no more needed b the 64k PTEs.\nb) abstracts out __real_pte() and __rpte_to_hidx() so the\n\tcaller need not know the bit location of the slot.\nc) moves the slot bits to the secondary pte.\n\nReviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/hash-4k.h | 3 ++\n arch/powerpc/include/asm/book3s/64/hash-64k.h | 29 +++++++++++-------------\n arch/powerpc/include/asm/book3s/64/hash.h | 3 --\n arch/powerpc/mm/hash64_64k.c | 23 ++++++++-----------\n arch/powerpc/mm/hugetlbpage-hash64.c | 18 ++++++---------\n 5 files changed, 33 insertions(+), 43 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\nindex e66bfeb..dc153c6 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n@@ -16,6 +16,9 @@\n #define H_PUD_TABLE_SIZE\t(sizeof(pud_t) << H_PUD_INDEX_SIZE)\n #define H_PGD_TABLE_SIZE\t(sizeof(pgd_t) << H_PGD_INDEX_SIZE)\n \n+#define H_PAGE_F_GIX_SHIFT\t56\n+#define H_PAGE_F_SECOND\t_RPAGE_RSV2\t/* HPTE is in 2ndary HPTEG */\n+#define H_PAGE_F_GIX\t(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)\n #define H_PAGE_BUSY\t_RPAGE_RSV1 /* software: PTE & hash are busy */\n \n /* PTE flags to conserve for HPTE identification */\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\nindex e038f1c..89ef5a9 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n@@ -12,7 +12,7 @@\n */\n #define H_PAGE_COMBO\t_RPAGE_RPN0 /* this is a combo 4k page */\n #define H_PAGE_4K_PFN\t_RPAGE_RPN1 /* PFN is for a single 4k page */\n-#define H_PAGE_BUSY\t_RPAGE_RPN42 /* software: PTE & hash are busy */\n+#define H_PAGE_BUSY\t_RPAGE_RPN44 /* software: PTE & hash are busy */\n \n /*\n * We need to differentiate between explicit huge page and THP huge\n@@ -21,8 +21,7 @@\n #define H_PAGE_THP_HUGE H_PAGE_4K_PFN\n \n /* PTE flags to conserve for HPTE identification */\n-#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_F_SECOND | \\\n-\t\t\t H_PAGE_F_GIX | H_PAGE_HASHPTE | H_PAGE_COMBO)\n+#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO)\n /*\n * we support 16 fragments per PTE page of 64K size.\n */\n@@ -50,24 +49,22 @@ static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)\n \tunsigned long *hidxp;\n \n \trpte.pte = pte;\n-\trpte.hidx = 0;\n-\tif (pte_val(pte) & H_PAGE_COMBO) {\n-\t\t/*\n-\t\t * Make sure we order the hidx load against the H_PAGE_COMBO\n-\t\t * check. The store side ordering is done in __hash_page_4K\n-\t\t */\n-\t\tsmp_rmb();\n-\t\thidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n-\t\trpte.hidx = *hidxp;\n-\t}\n+\t/*\n+\t * Ensure that we do not read the hidx before we read\n+\t * the pte. Because the writer side is expected\n+\t * to finish writing the hidx first followed by the pte,\n+\t * by using smp_wmb().\n+\t * pte_set_hash_slot() ensures that.\n+\t */\n+\tsmp_rmb();\n+\thidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n+\trpte.hidx = *hidxp;\n \treturn rpte;\n }\n \n static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)\n {\n-\tif ((pte_val(rpte.pte) & H_PAGE_COMBO))\n-\t\treturn (rpte.hidx >> (index<<2)) & 0xf;\n-\treturn (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf;\n+\treturn ((rpte.hidx >> (index<<2)) & 0xfUL);\n }\n \n /*\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\nindex 8ce4112..46f3a23 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash.h\n@@ -8,9 +8,6 @@\n *\n */\n #define H_PTE_NONE_MASK\t\t_PAGE_HPTEFLAGS\n-#define H_PAGE_F_GIX_SHIFT\t56\n-#define H_PAGE_F_SECOND\t\t_RPAGE_RSV2\t/* HPTE is in 2ndary HPTEG */\n-#define H_PAGE_F_GIX\t\t(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)\n #define H_PAGE_HASHPTE\t\t_RPAGE_RPN43\t/* PTE has associated HPTE */\n \n #ifdef CONFIG_PPC_64K_PAGES\ndiff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c\nindex c6c5559..9c63844 100644\n--- a/arch/powerpc/mm/hash64_64k.c\n+++ b/arch/powerpc/mm/hash64_64k.c\n@@ -103,8 +103,8 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t * On hash insert failure we use old pte value and we don't\n \t\t * want slot information there if we have a insert failure.\n \t\t */\n-\t\told_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);\n-\t\tnew_pte &= ~(H_PAGE_HASHPTE | H_PAGE_F_GIX | H_PAGE_F_SECOND);\n+\t\told_pte &= ~H_PAGE_HASHPTE;\n+\t\tnew_pte &= ~H_PAGE_HASHPTE;\n \t\tgoto htab_insert_hpte;\n \t}\n \t/*\n@@ -227,6 +227,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \t\t unsigned long vsid, pte_t *ptep, unsigned long trap,\n \t\t unsigned long flags, int ssize)\n {\n+\treal_pte_t rpte;\n \tunsigned long hpte_group;\n \tunsigned long rflags, pa;\n \tunsigned long old_pte, new_pte;\n@@ -263,6 +264,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \t} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));\n \n \trflags = htab_convert_pte_flags(new_pte);\n+\trpte = __real_pte(__pte(old_pte), ptep);\n \n \tif (cpu_has_feature(CPU_FTR_NOEXECUTE) &&\n \t !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))\n@@ -270,18 +272,13 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \n \tvpn = hpt_vpn(ea, vsid, ssize);\n \tif (unlikely(old_pte & H_PAGE_HASHPTE)) {\n+\t\tunsigned long gslot;\n \t\t/*\n \t\t * There MIGHT be an HPTE for this pte\n \t\t */\n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n-\n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, MMU_PAGE_64K,\n-\t\t\t\t\t MMU_PAGE_64K, ssize,\n-\t\t\t\t\t flags) == -1)\n+\t\tgslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0);\n+\t\tif (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, MMU_PAGE_64K,\n+\t\t\t\tMMU_PAGE_64K, ssize, flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\n \t}\n \n@@ -328,9 +325,9 @@ int __hash_page_64K(unsigned long ea, unsigned long access,\n \t\t\t\t\t MMU_PAGE_64K, MMU_PAGE_64K, old_pte);\n \t\t\treturn -1;\n \t\t}\n+\n \t\tnew_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;\n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n+\t\tnew_pte |= pte_set_hash_slot(ptep, rpte, 0, slot);\n \t}\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\ndiff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c\nindex a84bb44..d52d667 100644\n--- a/arch/powerpc/mm/hugetlbpage-hash64.c\n+++ b/arch/powerpc/mm/hugetlbpage-hash64.c\n@@ -22,6 +22,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t pte_t *ptep, unsigned long trap, unsigned long flags,\n \t\t int ssize, unsigned int shift, unsigned int mmu_psize)\n {\n+\treal_pte_t rpte;\n \tunsigned long vpn;\n \tunsigned long old_pte, new_pte;\n \tunsigned long rflags, pa, sz;\n@@ -61,6 +62,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t} while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));\n \n \trflags = htab_convert_pte_flags(new_pte);\n+\trpte = __real_pte(__pte(old_pte), ptep);\n \n \tsz = ((1UL) << shift);\n \tif (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))\n@@ -71,16 +73,11 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t/* Check if pte already has an hpte (case 2) */\n \tif (unlikely(old_pte & H_PAGE_HASHPTE)) {\n \t\t/* There MIGHT be an HPTE for this pte */\n-\t\tunsigned long hash, slot;\n+\t\tunsigned long gslot;\n \n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\tif (old_pte & H_PAGE_F_SECOND)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += (old_pte & H_PAGE_F_GIX) >> H_PAGE_F_GIX_SHIFT;\n-\n-\t\tif (mmu_hash_ops.hpte_updatepp(slot, rflags, vpn, mmu_psize,\n-\t\t\t\t\t mmu_psize, ssize, flags) == -1)\n+\t\tgslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0);\n+\t\tif (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, mmu_psize,\n+\t\t\t\tmmu_psize, ssize, flags) == -1)\n \t\t\told_pte &= ~_PAGE_HPTEFLAGS;\n \t}\n \n@@ -106,8 +103,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\treturn -1;\n \t\t}\n \n-\t\tnew_pte |= (slot << H_PAGE_F_GIX_SHIFT) &\n-\t\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n+\t\tnew_pte |= pte_set_hash_slot(ptep, rpte, 0, slot);\n \t}\n \n \t/*\n", "prefixes": [ "4/7" ] }