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GET /api/patches/811859/?format=api
{ "id": 811859, "url": "http://patchwork.ozlabs.org/api/patches/811859/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-4-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504910713-7094-4-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504910713-7094-4-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-08T22:44:43", "name": "[3/7] powerpc: Free up four 64K PTE bits in 4K backed HPTE pages", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "ae4112e35a270cce0dd17699f3ccecc78e6c8241", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-4-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 2303, "url": "http://patchwork.ozlabs.org/api/series/2303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2303", "date": "2017-09-08T22:44:40", "name": "powerpc: Free up RPAGE_RSV bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811859/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811859/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpt0B22WHz9s7v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:53:30 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpt093495zDrSN\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:53:29 +1000 (AEST)", "from mail-qt0-x244.google.com (mail-qt0-x244.google.com\n\t[IPv6:2607:f8b0:400d:c0d::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpsrB1tfqzDrcn\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Sep 2017 08:46:34 +1000 (AEST)", "by mail-qt0-x244.google.com with SMTP id p55so2360292qtc.2\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Sep 2017 15:46:34 -0700 (PDT)", "from localhost.localdomain (50-39-103-96.bvtn.or.frontiernet.net.\n\t[50.39.103.96]) by smtp.gmail.com with ESMTPSA id\n\tx124sm2033726qka.85.2017.09.08.15.46.30\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 15:46:31 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KaYLBsrR\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KaYLBsrR\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400d:c0d::244; helo=mail-qt0-x244.google.com;\n\tenvelope-from=ram.n.pai@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KaYLBsrR\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=89SJoLiCMxSYjsbgb585pTf8B2eB4iW44NTJaJzCYuE=;\n\tb=KaYLBsrRvog6zs7chz16kXvkNZon/sKNh6Dos9/jE5IFUDPQD4mOfl1fx14fFFcnzu\n\t7amq9ZpJBLWdO83EGUzFBkPZDWSC+KJLq9VvsTPbTN51GdizaLNRbjHzkdPQsEbvMlhT\n\t5ysikKjrwFviaO0EnKmD3DXW/GY6UcIEltvFLuUS0GbSNra7gl4FmE4aKyt5cCz2b0Mc\n\tcR+8YfPrn9bJ13gYAL0iRNlD5DmpPUVRs87pzD/l8IG36gNh9xSiOw0CZ1V66HiaNu97\n\tEzeZPibNVvltRBe15nHGLnLDhjds5amZ/QG0XgFrOEJlSnnN9r+lWWK87Y9Un28uEaWS\n\tFrQw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=89SJoLiCMxSYjsbgb585pTf8B2eB4iW44NTJaJzCYuE=;\n\tb=H63e3QuWzuCZMmOoYRf6v4kZayOLcAUoOSLniIct5DNv7rBglWpN2cEo4kABxZWnFN\n\tTPQhMmeqhvrA70GhW70EKE4MxF/xFNt2pah/tZEOXSfgM2lWV0XsQeiMOUsp5O+doJ2e\n\t0XCtWpJEis+mYoaT63sVs++CkTCL4wBXfqNdMjfNPro5em1ACgZuYD/SCOkn7HKo/Xi8\n\tHBJjG0kpQ89g52mwQYOi32jJi4sBgIvHWOCkQ9IaqF5l04l6nydZPPViHTwRI9Oqn9Zm\n\tGBQ8MV2deEPCn94tvJWnSOkGAcIHwTU2IgVBxnab7JxLpIlSolCYmWGo6BlIYFtYtB25\n\tqB8Q==", "X-Gm-Message-State": "AHPjjUiMn0GnuKRbR31uGn+jpka66mrFP56IPwKwIwyXqwkCRFXSKXYT\n\toDp0Y22QAzqX5A==", "X-Google-Smtp-Source": "AOwi7QC1tNfPwHYvFSqhKuyfgkLERJbMRA0d357gRVvoX/K1bpuAbcVvlI2/jm6lrDZZ2fyydvgq7A==", "X-Received": "by 10.200.24.146 with SMTP id s18mr6107483qtj.38.1504910792083; \n\tFri, 08 Sep 2017 15:46:32 -0700 (PDT)", "From": "Ram Pai <linuxram@us.ibm.com>", "To": "mpe@ellerman.id.au,\n\tlinuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 3/7] powerpc: Free up four 64K PTE bits in 4K backed HPTE\n\tpages", "Date": "Fri, 8 Sep 2017 15:44:43 -0700", "Message-Id": "<1504910713-7094-4-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "References": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Rearrange 64K PTE bits to free up bits 3, 4, 5 and 6,\nin the 4K backed HPTE pages.These bits continue to be used\nfor 64K backed HPTE pages in this patch, but will be freed\nup in the next patch. The bit numbers are big-endian as\ndefined in the ISA3.0\n\nThe patch does the following change to the 4k htpe backed\n64K PTE's format.\n\nH_PAGE_BUSY moves from bit 3 to bit 9 (B bit in the figure\n\t\tbelow)\nV0 which occupied bit 4 is not used anymore.\nV1 which occupied bit 5 is not used anymore.\nV2 which occupied bit 6 is not used anymore.\nV3 which occupied bit 7 is not used anymore.\n\nBefore the patch, the 4k backed 64k PTE format was as follows\n\n 0 1 2 3 4 5 6 7 8 9 10...........................63\n : : : : : : : : : : : :\n v v v v v v v v v v v v\n\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x|B|V0|V1|V2|V3|x| | |x|x|................|x|x|x|x| <- primary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n|S|G|I|X|S |G |I |X |S|G|I|X|..................|S|G|I|X| <- secondary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'__________________'_'_'_'_'\n\nAfter the patch, the 4k backed 64k PTE format is as follows\n\n 0 1 2 3 4 5 6 7 8 9 10...........................63\n : : : : : : : : : : : :\n v v v v v v v v v v v v\n\n,-,-,-,-,--,--,--,--,-,-,-,-,-,------------------,-,-,-,\n|x|x|x| | | | | |x|B| |x|x|................|.|.|.|.| <- primary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'_'________________'_'_'_'_'\n|S|G|I|X|S |G |I |X |S|G|I|X|..................|S|G|I|X| <- secondary pte\n'_'_'_'_'__'__'__'__'_'_'_'_'__________________'_'_'_'_'\n\nthe four bits S,G,I,X (one quadruplet per 4k HPTE) that\ncache the hash-bucket slot value, is initialized to\n1,1,1,1 indicating -- an invalid slot. If a HPTE gets\ncached in a 1111 slot(i.e 7th slot of secondary hash\nbucket), it is released immediately. In other words,\neven though 1111 is a valid slot value in the hash\nbucket, we consider it invalid and release the slot and\nthe HPTE. This gives us the opportunity to determine\nthe validity of S,G,I,X bits based on its contents and\nnot on any of the bits V0,V1,V2 or V3 in the primary PTE\n\nWhen we release a HPTE cached in the 1111 slot\nwe also release a legitimate slot in the primary\nhash bucket and unmap its corresponding HPTE. This\nis to ensure that we do get a HPTE cached in a slot\nof the primary hash bucket, the next time we retry.\n\nThough treating 1111 slot as invalid, reduces the\nnumber of available slots in the hash bucket and may\nhave an effect on the performance, the probabilty of\nhitting a 1111 slot is extermely low.\n\nCompared to the current scheme, the above scheme\nreduces the number of false hash table updates\nsignificantly and has the added advantage of releasing\nfour valuable PTE bits for other purpose.\n\nNOTE:even though bits 3, 4, 5, 6, 7 are not used when\nthe 64K PTE is backed by 4k HPTE, they continue to be\nused if the PTE gets backed by 64k HPTE. The next\npatch will decouple that aswell, and truely release the\nbits.\n\nThis idea was jointly developed by Paul Mackerras,\nAneesh, Michael Ellermen and myself.\n\n4K PTE format remains unchanged currently.\n\nThe patch does the following code changes\na) PTE flags are split between 64k and 4k header files.\nb) __hash_page_4K() is reimplemented to reflect the\n above logic.\n\nReviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/hash-4k.h | 2 +\n arch/powerpc/include/asm/book3s/64/hash-64k.h | 8 +--\n arch/powerpc/include/asm/book3s/64/hash.h | 1 -\n arch/powerpc/mm/hash64_64k.c | 106 +++++++++++++------------\n arch/powerpc/mm/hash_utils_64.c | 4 +-\n 5 files changed, 63 insertions(+), 58 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\nindex 8909039..e66bfeb 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n@@ -16,6 +16,8 @@\n #define H_PUD_TABLE_SIZE\t(sizeof(pud_t) << H_PUD_INDEX_SIZE)\n #define H_PGD_TABLE_SIZE\t(sizeof(pgd_t) << H_PGD_INDEX_SIZE)\n \n+#define H_PAGE_BUSY\t_RPAGE_RSV1 /* software: PTE & hash are busy */\n+\n /* PTE flags to conserve for HPTE identification */\n #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \\\n \t\t\t H_PAGE_F_SECOND | H_PAGE_F_GIX)\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\nindex 6652669..e038f1c 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n@@ -12,18 +12,14 @@\n */\n #define H_PAGE_COMBO\t_RPAGE_RPN0 /* this is a combo 4k page */\n #define H_PAGE_4K_PFN\t_RPAGE_RPN1 /* PFN is for a single 4k page */\n+#define H_PAGE_BUSY\t_RPAGE_RPN42 /* software: PTE & hash are busy */\n+\n /*\n * We need to differentiate between explicit huge page and THP huge\n * page, since THP huge page also need to track real subpage details\n */\n #define H_PAGE_THP_HUGE H_PAGE_4K_PFN\n \n-/*\n- * Used to track subpage group valid if H_PAGE_COMBO is set\n- * This overloads H_PAGE_F_GIX and H_PAGE_F_SECOND\n- */\n-#define H_PAGE_COMBO_VALID\t(H_PAGE_F_GIX | H_PAGE_F_SECOND)\n-\n /* PTE flags to conserve for HPTE identification */\n #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_F_SECOND | \\\n \t\t\t H_PAGE_F_GIX | H_PAGE_HASHPTE | H_PAGE_COMBO)\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\nindex 060c059..8ce4112 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash.h\n@@ -9,7 +9,6 @@\n */\n #define H_PTE_NONE_MASK\t\t_PAGE_HPTEFLAGS\n #define H_PAGE_F_GIX_SHIFT\t56\n-#define H_PAGE_BUSY\t\t_RPAGE_RSV1 /* software: PTE & hash are busy */\n #define H_PAGE_F_SECOND\t\t_RPAGE_RSV2\t/* HPTE is in 2ndary HPTEG */\n #define H_PAGE_F_GIX\t\t(_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)\n #define H_PAGE_HASHPTE\t\t_RPAGE_RPN43\t/* PTE has associated HPTE */\ndiff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c\nindex 1a68cb1..c6c5559 100644\n--- a/arch/powerpc/mm/hash64_64k.c\n+++ b/arch/powerpc/mm/hash64_64k.c\n@@ -15,34 +15,22 @@\n #include <linux/mm.h>\n #include <asm/machdep.h>\n #include <asm/mmu.h>\n+\n /*\n- * index from 0 - 15\n+ * return true, if the entry has a slot value which\n+ * the software considers as invalid.\n */\n-bool __rpte_sub_valid(real_pte_t rpte, unsigned long index)\n+static inline bool hpte_soft_invalid(unsigned long slot)\n {\n-\tunsigned long g_idx;\n-\tunsigned long ptev = pte_val(rpte.pte);\n-\n-\tg_idx = (ptev & H_PAGE_COMBO_VALID) >> H_PAGE_F_GIX_SHIFT;\n-\tindex = index >> 2;\n-\tif (g_idx & (0x1 << index))\n-\t\treturn true;\n-\telse\n-\t\treturn false;\n+\treturn ((slot & 0xfUL) == 0xfUL);\n }\n+\n /*\n * index from 0 - 15\n */\n-static unsigned long mark_subptegroup_valid(unsigned long ptev, unsigned long index)\n+bool __rpte_sub_valid(real_pte_t rpte, unsigned long index)\n {\n-\tunsigned long g_idx;\n-\n-\tif (!(ptev & H_PAGE_COMBO))\n-\t\treturn ptev;\n-\tindex = index >> 2;\n-\tg_idx = 0x1 << index;\n-\n-\treturn ptev | (g_idx << H_PAGE_F_GIX_SHIFT);\n+\treturn !(hpte_soft_invalid(rpte.hidx >> (index << 2)));\n }\n \n int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n@@ -50,12 +38,11 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t int ssize, int subpg_prot)\n {\n \treal_pte_t rpte;\n-\tunsigned long *hidxp;\n \tunsigned long hpte_group;\n \tunsigned int subpg_index;\n-\tunsigned long rflags, pa, hidx;\n+\tunsigned long rflags, pa;\n \tunsigned long old_pte, new_pte, subpg_pte;\n-\tunsigned long vpn, hash, slot;\n+\tunsigned long vpn, hash, slot, gslot;\n \tunsigned long shift = mmu_psize_defs[MMU_PAGE_4K].shift;\n \n \t/*\n@@ -126,18 +113,13 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \tif (__rpte_sub_valid(rpte, subpg_index)) {\n \t\tint ret;\n \n-\t\thash = hpt_hash(vpn, shift, ssize);\n-\t\thidx = __rpte_to_hidx(rpte, subpg_index);\n-\t\tif (hidx & _PTEIDX_SECONDARY)\n-\t\t\thash = ~hash;\n-\t\tslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n-\t\tslot += hidx & _PTEIDX_GROUP_IX;\n+\t\tgslot = pte_get_hash_gslot(vpn, shift, ssize, rpte,\n+\t\t\t\t\tsubpg_index);\n+\t\tret = mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn,\n+\t\t\tMMU_PAGE_4K, MMU_PAGE_4K, ssize, flags);\n \n-\t\tret = mmu_hash_ops.hpte_updatepp(slot, rflags, vpn,\n-\t\t\t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K,\n-\t\t\t\t\t\t ssize, flags);\n \t\t/*\n-\t\t *if we failed because typically the HPTE wasn't really here\n+\t\t * if we failed because typically the HPTE wasn't really here\n \t\t * we try an insertion.\n \t\t */\n \t\tif (ret == -1)\n@@ -148,6 +130,15 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t}\n \n htab_insert_hpte:\n+\n+\t/*\n+\t * initialize all hidx entries to invalid value,\n+\t * the first time the PTE is about to allocate\n+\t * a 4K hpte\n+\t */\n+\tif (!(old_pte & H_PAGE_COMBO))\n+\t\trpte.hidx = ~0x0UL;\n+\n \t/*\n \t * handle H_PAGE_4K_PFN case\n \t */\n@@ -172,15 +163,41 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t * Primary is full, try the secondary\n \t */\n \tif (unlikely(slot == -1)) {\n+\t\tbool soft_invalid;\n+\n \t\thpte_group = ((~hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;\n \t\tslot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa,\n \t\t\t\t\t\trflags, HPTE_V_SECONDARY,\n \t\t\t\t\t\tMMU_PAGE_4K, MMU_PAGE_4K,\n \t\t\t\t\t\tssize);\n-\t\tif (slot == -1) {\n-\t\t\tif (mftb() & 0x1)\n+\n+\t\tsoft_invalid = hpte_soft_invalid(slot);\n+\t\tif (unlikely(soft_invalid)) {\n+\t\t\t/*\n+\t\t\t * we got a valid slot from a hardware point of view.\n+\t\t\t * but we cannot use it, because we use this special\n+\t\t\t * value; as defined by hpte_soft_invalid(),\n+\t\t\t * to track invalid slots. We cannot use it.\n+\t\t\t * So invalidate it.\n+\t\t\t */\n+\t\t\tgslot = slot & _PTEIDX_GROUP_IX;\n+\t\t\tmmu_hash_ops.hpte_invalidate(hpte_group+gslot, vpn,\n+\t\t\t\tMMU_PAGE_4K, MMU_PAGE_4K,\n+\t\t\t\tssize, 0);\n+\t\t}\n+\n+\t\tif (unlikely(slot == -1 || soft_invalid)) {\n+\t\t\t/*\n+\t\t\t * for soft invalid slot, lets ensure that we\n+\t\t\t * release a slot from the primary, with the\n+\t\t\t * hope that we will acquire that slot next\n+\t\t\t * time we try. This will ensure that we do not\n+\t\t\t * get the same soft-invalid slot.\n+\t\t\t */\n+\t\t\tif (soft_invalid || (mftb() & 0x1))\n \t\t\t\thpte_group = ((hash & htab_hash_mask) *\n \t\t\t\t\t HPTES_PER_GROUP) & ~0x7UL;\n+\n \t\t\tmmu_hash_ops.hpte_remove(hpte_group);\n \t\t\t/*\n \t\t\t * FIXME!! Should be try the group from which we removed ?\n@@ -198,21 +215,10 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,\n \t\t\t\t MMU_PAGE_4K, MMU_PAGE_4K, old_pte);\n \t\treturn -1;\n \t}\n-\t/*\n-\t * Insert slot number & secondary bit in PTE second half,\n-\t * clear H_PAGE_BUSY and set appropriate HPTE slot bit\n-\t * Since we have H_PAGE_BUSY set on ptep, we can be sure\n-\t * nobody is undating hidx.\n-\t */\n-\thidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n-\trpte.hidx &= ~(0xfUL << (subpg_index << 2));\n-\t*hidxp = rpte.hidx | (slot << (subpg_index << 2));\n-\tnew_pte = mark_subptegroup_valid(new_pte, subpg_index);\n-\tnew_pte |= H_PAGE_HASHPTE;\n-\t/*\n-\t * check __real_pte for details on matching smp_rmb()\n-\t */\n-\tsmp_wmb();\n+\n+\tnew_pte |= pte_set_hash_slot(ptep, rpte, subpg_index, slot);\n+\tnew_pte |= H_PAGE_HASHPTE;\n+\n \t*ptep = __pte(new_pte & ~H_PAGE_BUSY);\n \treturn 0;\n }\ndiff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\nindex e68f053..a40c7bc 100644\n--- a/arch/powerpc/mm/hash_utils_64.c\n+++ b/arch/powerpc/mm/hash_utils_64.c\n@@ -978,8 +978,9 @@ void __init hash__early_init_devtree(void)\n \n void __init hash__early_init_mmu(void)\n {\n+#ifndef CONFIG_PPC_64K_PAGES\n \t/*\n-\t * We have code in __hash_page_64K() and elsewhere, which assumes it can\n+\t * We have code in __hash_page_4K() and elsewhere, which assumes it can\n \t * do the following:\n \t * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);\n \t *\n@@ -990,6 +991,7 @@ void __init hash__early_init_mmu(void)\n \t * with a BUILD_BUG_ON().\n \t */\n \tBUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));\n+#endif /* CONFIG_PPC_64K_PAGES */\n \n \thtab_init_page_sizes();\n \n", "prefixes": [ "3/7" ] }