Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/811809/?format=api
{ "id": 811809, "url": "http://patchwork.ozlabs.org/api/patches/811809/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170908190825.21515-2-s-anna@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170908190825.21515-2-s-anna@ti.com>", "list_archive_url": null, "date": "2017-09-08T19:08:24", "name": "[U-Boot,1/2] arm: am57xx: cl-som-am57x: Use new pinctrl macros", "commit_ref": "101d2171e10951d115fd9229c5edc883f1833e96", "pull_url": null, "state": "accepted", "archived": false, "hash": "6548ae11f720d9057048828e363fe945c2685cdc", "submitter": { "id": 24498, "url": "http://patchwork.ozlabs.org/api/people/24498/?format=api", "name": "Suman Anna", "email": "s-anna@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170908190825.21515-2-s-anna@ti.com/mbox/", "series": [ { "id": 2278, "url": "http://patchwork.ozlabs.org/api/series/2278/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2278", "date": "2017-09-08T19:08:23", "name": "Cleanup old DRA7 pinctrl macros", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2278/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811809/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"lR1MZf5O\";\n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpn2s4MyYz9t16\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 9 Sep 2017 05:10:24 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A1EE0C21C60; Fri, 8 Sep 2017 19:10:17 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5F234C21E84;\n\tFri, 8 Sep 2017 19:10:14 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 5B54EC21DC8; Fri, 8 Sep 2017 19:10:01 +0000 (UTC)", "from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80])\n\tby lists.denx.de (Postfix) with ESMTPS id D4F21C21F0E\n\tfor <u-boot@lists.denx.de>; Fri, 8 Sep 2017 19:09:57 +0000 (UTC)", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v88J8aaR009863; \n\tFri, 8 Sep 2017 14:08:36 -0500", "from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ax3023193; \n\tFri, 8 Sep 2017 14:08:36 -0500", "from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com\n\t(157.170.170.24) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tFri, 8 Sep 2017 14:08:36 -0500", "from dflp32.itg.ti.com (10.64.6.15) by DLEE105.ent.ti.com\n\t(157.170.170.35) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Fri, 8 Sep 2017 14:08:36 -0500", "from legion.dal.design.ti.com (legion.dal.design.ti.com\n\t[128.247.22.53])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ac6021719;\n\tFri, 8 Sep 2017 14:08:36 -0500", "from localhost (irmo.dhcp.ti.com [128.247.58.153])\n\tby legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id\n\tv88J8a302538; Fri, 8 Sep 2017 14:08:36 -0500 (CDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.8 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID,\n\tUPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1504897716;\n\tbh=XJZzJXEA/umRuhp/elhW0ZXFmlQGsL4PgVJFdqu0+Ec=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=lR1MZf5ODIAm5VTBkdPF9VMQG9sxBjrOnaHMBR6VI9PvYJkd5xOzQaWLdrw+KJUpq\n\t0zdVtzF2T2VTF8n8QsmGBehXVHzcVyS/lcMDretre5455Mqztl0ddKjToIe366NtgN\n\t1M/TYPfFv0uf51vGQeRNz3Fj6UiLeJBO7XcfvGi4=", "From": "Suman Anna <s-anna@ti.com>", "To": "Uri Mashiach <uri.mashiach@compulab.co.il>", "Date": "Fri, 8 Sep 2017 14:08:24 -0500", "Message-ID": "<20170908190825.21515-2-s-anna@ti.com>", "X-Mailer": "git-send-email 2.13.1", "In-Reply-To": "<20170908190825.21515-1-s-anna@ti.com>", "References": "<20170908190825.21515-1-s-anna@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH 1/2] arm: am57xx: cl-som-am57x: Use new pinctrl\n\tmacros", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Commit 6ae4c3efbd62 (\"ARM: DRA7: Add pinctrl register definitions\")\nhas added new macros for pinmux configuration in line with the\nkernel definitions. Fixup the current pinctrl data for the CompuLab\nCL-SOM-AM57x board to use these new macros to facilitate the removal\nof the old macros.\n\nNOTE:\nThe PEN and PDIS macro values used previously were actually defined\ninversely, a value of 1 in bit position 16 actually means that the\ninternal pullup/pulldown is disabled and not enabled as inferred by\nPEN. So, previous pinmux config data such as (PDIS | PTU) is confusing\nas it actually was meant for enabling internal pullup. The data is\nfixed up only to be equivalent to the previous data.\n\nSigned-off-by: Suman Anna <s-anna@ti.com>\n---\n board/compulab/cl-som-am57x/mux.c | 105 +++++++++++++++++++-------------------\n 1 file changed, 53 insertions(+), 52 deletions(-)", "diff": "diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c\nindex 0db0609727f7..21449ca029b0 100644\n--- a/board/compulab/cl-som-am57x/mux.c\n+++ b/board/compulab/cl-som-am57x/mux.c\n@@ -12,97 +12,98 @@\n \n /* Serial console */\n static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {\n-\t{UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */\n-\t{UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */\n+\t{UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */\n+\t{UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */\n };\n \n /* PMIC I2C */\n static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {\n-\t{MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */\n-\t{MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */\n+\t{MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */\n+\t{MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */\n };\n \n /* Green GPIO led */\n static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {\n-\t{GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */\n+\t{GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */\n };\n \n /* MMC/SD Card */\n static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {\n-\t{MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */\n-\t{MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */\n-\t{MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */\n-\t{MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */\n-\t{MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */\n-\t{MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */\n-\t{MMC1_SDCD, (IEN | PEN |\tM14)}, /* MMC1_SDCD */\n-\t{MMC1_SDWP, (IEN | PEN |\tM14)}, /* MMC1_SDWP */\n+\t{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */\n+\t{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */\n+\t{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */\n+\t{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */\n+\t{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */\n+\t{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */\n+\t{MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */\n+\t{MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */\n };\n \n /* WiFi - must be in the safe mode on boot */\n static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {\n-\t{UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */\n-\t{UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */\n-\t{UART2_RXD, (IEN | M15)}, /* UART2_RXD */\n-\t{UART2_TXD, (IEN | M15)}, /* UART2_TXD */\n-\t{UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */\n-\t{UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */\n+\t{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */\n+\t{UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */\n+\t{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */\n+\t{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */\n+\t{UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */\n+\t{UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */\n };\n \n /* QSPI */\n static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {\n-\t{GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */\n-\t{GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */\n-\t{GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */\n-\t{GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */\n-\t{GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */\n+\t{GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */\n+\t{GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */\n+\t{GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */\n+\t{GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */\n+\t{GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */\n };\n \n /* GPIO Expander I2C */\n static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {\n-\t{MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */\n-\t{MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */\n+\t{MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */\n+\t{MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */\n };\n \n /* eMMC internal storage */\n static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {\n-\t{GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */\n-\t{GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */\n-\t{GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */\n-\t{GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */\n-\t{GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */\n-\t{GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */\n-\t{GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */\n-\t{GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */\n-\t{GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */\n-\t{GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */\n+\t{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */\n+\t{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */\n+\t{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */\n+\t{GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */\n+\t{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */\n+\t{GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */\n+\t{GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */\n+\t{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */\n+\t{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */\n+\t{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */\n };\n \n /* usb1_drvvbus */\n static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {\n-\t{USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */\n+\t/* USB1_DRVVBUS.USB1_DRVVBUS */\n+\t{USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) },\n };\n \n /* Ethernet */\n static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {\n \t/* MDIO bus */\n-\t{VIN2A_D10, (PDIS | PTU |\t M3) }, /* VIN2A_D10.MDIO_MCLK */\n-\t{VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */\n+\t{VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */\n+\t{VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */\n \t/* EMAC Slave 1 at addr 0x1 - Default interface */\n-\t{VIN2A_D12, (IDIS | PEN |\t M3) }, /* VIN2A_D12.RGMII1_TXC */\n-\t{VIN2A_D13, (IDIS | PEN |\t M3) }, /* VIN2A_D13.RGMII1_TXCTL */\n-\t{VIN2A_D14, (IDIS | PEN |\t M3) }, /* VIN2A_D14.RGMII1_TXD3 */\n-\t{VIN2A_D15, (IDIS | PEN |\t M3) }, /* VIN2A_D15.RGMII1_TXD2 */\n-\t{VIN2A_D16, (IDIS | PEN |\t M3) }, /* VIN2A_D16.RGMII1_TXD1 */\n-\t{VIN2A_D17, (IDIS | PEN |\t M3) }, /* VIN2A_D17.RGMII1_TXD0 */\n-\t{VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */\n-\t{VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */\n-\t{VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */\n-\t{VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */\n-\t{VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */\n-\t{VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */\n+\t{VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */\n+\t{VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */\n+\t{VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */\n+\t{VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */\n+\t{VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */\n+\t{VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */\n+\t{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */\n+\t{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */\n+\t{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */\n+\t{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */\n+\t{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */\n+\t{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */\n \t/* Eth PHY1 reset GPIOs*/\n-\t{VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */\n+\t{VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */\n };\n \n #define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \\\n", "prefixes": [ "U-Boot", "1/2" ] }