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GET /api/patches/811556/?format=api
{ "id": 811556, "url": "http://patchwork.ozlabs.org/api/patches/811556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-4-git-send-email-vjonnal@xilinx.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>", "list_archive_url": null, "date": "2017-09-08T12:23:05", "name": "[v2,3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "2fc0d41e5ad518b4f9561bf8fa937e27401e8487", "submitter": { "id": 72127, "url": "http://patchwork.ozlabs.org/api/people/72127/?format=api", "name": "Ravi Shankar Jonnalagadda", "email": "venkata.ravi.jonnalagadda@xilinx.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-4-git-send-email-vjonnal@xilinx.com/mbox/", "series": [ { "id": 2190, "url": "http://patchwork.ozlabs.org/api/series/2190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=2190", "date": "2017-09-08T12:23:04", "name": "dmaengine: ZynqMP PS PCIe DMA driver", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811556/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811556/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=xilinx.onmicrosoft.com\n\theader.i=@xilinx.onmicrosoft.com header.b=\"k7PvXR43\"; \n\tdkim-atps=neutral", "spf=pass (sender IP is 149.199.60.83)\n\tsmtp.mailfrom=xilinx.com; vger.kernel.org;\n\tdkim=none (message not signed)\n\theader.d=none;vger.kernel.org; dmarc=bestguesspass action=none\n\theader.from=xilinx.com;" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpc4t20m8z9t3V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 22:26:37 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755541AbdIHMXs (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 8 Sep 2017 08:23:48 -0400", "from mail-bn3nam01on0040.outbound.protection.outlook.com\n\t([104.47.33.40]:45873\n\t\"EHLO NAM01-BN3-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1754792AbdIHMXb (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tFri, 8 Sep 2017 08:23:31 -0400", "from BLUPR0201CA0011.namprd02.prod.outlook.com (10.163.116.21) by\n\tBN3PR02MB1126.namprd02.prod.outlook.com (10.162.168.144) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.35.12; 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Fri, 08 Sep 2017 05:23:22 -0700", "from xsj-pvapsmtp01 (mailhost.xilinx.com [149.199.38.66])\n\tby xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id\n\tv88CNFKJ013161; Fri, 8 Sep 2017 05:23:15 -0700", "from [172.23.37.80] (helo=xhd-paegbuild40.xilinx.com)\n\tby xsj-pvapsmtp01 with esmtp (Exim 4.63)\n\t(envelope-from <vjonnal@xilinx.com>)\n\tid 1dqIJW-0004Me-SJ; Fri, 08 Sep 2017 05:23:15 -0700", "by xhd-paegbuild40.xilinx.com (Postfix, from userid 12633)\n\tid EEF82B2085B; Fri, 8 Sep 2017 17:53:13 +0530 (IST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=xilinx.onmicrosoft.com; s=selector1-xilinx-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=REsHjY0wWqoyqo0+WWfvBeSWNP3FREMCSiKuPfc+hzE=;\n\tb=k7PvXR43HCnZb+X7bpN92WD6TaOFbLLrTWtAvsieWkqF2QsNK1RmFsyLtfGu+JBlfZc0s7/oMcef8JitvGRINBIGw5d8HRoaI77mvDHAWwVdBDsiM91rjKYt76JpEXdqq1BIUEAMgE0SI4iTTN3x4CI3Gk7ZzoVlQNgZHB0TRX4=", "Received-SPF": "Pass (protection.outlook.com: domain of xilinx.com designates\n\t149.199.60.83 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=149.199.60.83; helo=xsj-pvapsmtpgw01;", "From": "Ravi Shankar Jonnalagadda <venkata.ravi.jonnalagadda@xilinx.com>", "To": "<vinod.koul@intel.com>, <robh+dt@kernel.org>,\n\t<mark.rutland@arm.com>, <michal.simek@xilinx.com>,\n\t<soren.brinkmann@xilinx.com>, <dan.j.williams@intel.com>,\n\t<bhelgaas@google.com>, <vjonnal@xilinx.com>,\n\t<lorenzo.pieralisi@arm.com>, <bharat.kumar.gogada@xilinx.com>,\n\t<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<rgummal@xilinx.com>", "Subject": "[PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver", "Date": "Fri, 8 Sep 2017 17:53:05 +0530", "Message-ID": "<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>", "X-Mailer": "git-send-email 2.1.1", "In-Reply-To": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "References": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "X-RCIS-Action": "ALLOW", "X-TM-AS-Product-Ver": "IMSS-7.1.0.1224-8.1.0.1062-23314.003", "X-TM-AS-User-Approved-Sender": "Yes;Yes", "X-EOPAttributedMessage": "0", "X-MS-Office365-Filtering-HT": "Tenant", "X-Forefront-Antispam-Report": "CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(39860400002)(2980300002)(438002)(189002)(199003)(2906002)(45336002)(90966002)(46386002)(8936002)(50466002)(103686004)(48376002)(52956003)(2201001)(50226002)(478600001)(8676002)(36756003)(81166006)(5660300001)(81156014)(33646002)(36386004)(7416002)(47776003)(106466001)(42186005)(76176999)(356003)(5003940100001)(50986999)(305945005)(189998001)(6636002)(6666003)(2950100002)(63266004)(6266002)(921003)(2004002)(107986001)(1121003)(83996005)(2101003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BN3PR02MB1126;\n\tH:xsj-pvapsmtpgw01; FPR:; SPF:Pass;\n\tPTR:unknown-60-83.xilinx.com; MX:1; A:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "1; SN1NAM02FT017;\n\t1:6IXxzXnypUhxGzXI14DPeGozryEdVOPeHZmb5p0K2qyI90RDCRLQJAWrbGBeel9tFGcg5eDP/mCGRht20rBeTTcpdmd5igJ4IyyquZr4MZ6yi6ZwLnA00+2o7Pl1Fa3D", "1; BN3PR02MB1126;\n\t3:zzwwGfdksLcl5O004DE5GOlG1rh/v1JPv/50aoGagDIPesCk5injoztnhCCFGy+BWP53XaGBfUnC/2eZ390jtgFyvVEMRg8Np7cB3WZKk/X4IWiHG3XRVUqbmqgKC3zcdttkULf24pg0ueJDH586LtrCIOGIDlC/es3ci/xptWxGD9LWx1wSe90a7ZfyQSuMDtQeqzcxoUbNfqXT1NrE6obMg95jaHXGlPJMTVLKQPHnscVgtdU8QC3prjODQc0fBL0mB+Rlx0c3WlyUT33hd7vmXGBAlT9s6ic7nOzScACr0KuRpcrfy4b52LIfH3pNj1hvxfCMYD7BzDRHf2dqOXmvZM9Svn/lnZcjr2inOy4=;\n\t25:VqAh7BtabPTAF09lmr3FO6qI1zqEGOYSb03sjqB+1vnpeGi/r1qn8zmaWKxgLtVZx611J0HgU7ZCXS8AvEyWW2ZCcm/6rAPkTF2uYxG3xVt2icIotYagVgup9hzLWcCOEoDYyo++YrUsFzSWVy98fZyR8slj3oBwOqka3U3cOZ/JkcCu1c2mC/PsSkMkc0/GbBmS9RX1xSwxTqlQKArvNdU6jiyAWgXrXIrgpnmKx2Gdcm2lP0NW2GP7uxfnU0SaT7vkTvBv5fv4lSdANOGul7Ka7WI7RUS1Wv9MwO54T0maCfOwy2lFMoubjlm/7jEhPjpdiQysDFw35xELTl6NhA==", "1; BN3PR02MB1126;\n\t31:IhEB0w99BzHLzVSCPeZtynjZPyhChNwkg9PA0qDfrgBWHszWwfsLuyXfjvNiupwL1Gs8pB0SXG8bfgVKhym6fZwcQqF5ZZbAlnF6tLofGXW04TQvmNf+r/onQGBZ2Me+IbDY2U2iZqQVuo70uyWdLz7LSFjS5i6iqU36RsAQm6+GndagPiSme5g/cNC0hGn8jwJHwzsEeBTHaG9fQ24GzDuWI6DcP2TWXsUxjBpZlDw=;\n\t20:A1aqOYLET052HFbf95SZMZlofr389TAPv+ViDzUP8cIFzdOeLCya6DV8+PCgaLofTUkSf2IYSzvc2gx2AX6L+m1B5Q8T040FdJMaEhaNeb25iiHdfIOwgWBnzZuX+Y9k8JzP3X349S0VEG8H3WyOMHkRB8QsyUKf3XK8vNm8qfrZE8Iujc6nuYGT9pOMsxdpXCtCwcvhhH8OWmWCBFClioBJWMziln596uts+y/msu8tct5GyP8NkAhS2m6okXs2MJcXvcqPPm2H4xk42GKVk3BtW5uWlCoLiwbG3aDdKtS6y4gwGqoZ43fqXtewIhrkE+EuJfomnr7ZhsRr0/rLYwM1qCI/ctWc9SpQu3NptElYDt0lFShfhdEMZ6+Q0lj20lh8aLlrxWiYo3CPnchCFs+8OarOq6RQnc8lS6auO5EyWvz9qrwndcsKVmqJZO0zAipDgdEcDZwqUPxwkEZ8Ok/I6Ddg6Q9N3BuTtBLquAW2bb1ohWcpbJGsWclGFtdP", "1; BN3PR02MB1126;\n\t4:kwvKrxgrsdOOsheQhEx7GXG3TEJ03IOGH6saLOQf/Qzpof7tZ3T5LGwuGi84axb4vmsKg+MoGR+3uac1BpOyqfroClz4oZoXQcxqS2Dj2BXNHdnC2onUj8ZPkhGiovFfQkIJqXU1OX7CZ4dDOahb7YIU7hB0rPUJuahkmGnuqyUxmgJambBnob1rPWpJ7/LC4uyGY/8u80uzsKzsK42hi7cTmZJwNu8U/i4VZLQmGwZ++y4oU9ClNrW3v461l3Ad3wCIWvT55Jcr2nXy4BDpeMvXZJ0oC4fD6vAw2iFQvyM=", "1; BN3PR02MB1126;\n\t23:1AX49Rp+EgSwoBrCMOLgC/l/ksC11lWyHfs6GIx+yLvyARlxA5/YS1aZ3nU2+ATZvoB7enAdvk837yMDHiioLIMPB8c9d2WBYZrcjV9HcS0z3caY5oGRu79/aVVYZBJdME1Er0J56KRXPJo0y52UHVBPM8G1y0TzbKfpLAGlmfgwkH/4MyBDbMG0auL5OmDabMHpNKHt5xeDe1Tdbc2SntnfBk/rLAv1bNUg9VAqXMBCO+BsjDKzqMQkznROQSKOt28EIZJnYCPfhvdPqwtGf19JaPZmZgXiKuV5oB0/AI/ytKlxu88BhQmde1kugcltIILAHTG4mXaBsAMBEl16XLLXaPUZpu/4hAe+Rs5oafakMchGG2IS5CfoX28/IvUMB1Wjis6QTfKNYzN6vBKdDS8l5GBJCP0wqtCKf9w1s2Da0k7LRql9Ph0Gxewb2lgWBvYudH325UT4375r2lxSqtjqj7/DehZaajrAgDwxbdgD2I5CmM+pENIZaKiUDNPTz3bSommF8EDZD82scI1cfFgR/fcnTN0LeT1lDKRTbtquDTRt553Y0m2I9uPZSvsbOy1ump0j6SGRQMnR97OvSLa6AVjQTxLoojDvA8ksHq9jTapt035ISxkE1CdDEtAAAns7WgqLDX2c4W8NNpRfAjS03Zea1yTScdkK6GCnmNaHOUTnlSdLsXb52tpQa4clx0g2Zfs4lxIznORXU6i8fSGlGpVrFhSu0u0g+WP+QjUeLneCFL2wE90XUHdojxTV09WIfEdRdUNc/61Ukf0kUnOGxwyXF14sZvB8gRCWpLKGCdsuY1aKBTygOOR8Yc233HfjJkWxuu4JpEhMWCrnFawlh8ARe/E10CxixAB9YiS9ISJjUCGORG9Lb24J1oqE8ytFX6TwZC4v07SaDSE3VdbUzWUQlZ3eYBtxUKsLMtyxea5Wx6OoQZoRV8VqBQHVujFOX/vgSetPvyLH90TrRi8DNe21mXfTPvXqnlMCM1rNv/v9qK2w96PD0gU8J2Ci+X6d5aDtcI72YMe62rtExLr7fsp/F79P6Iz8GacGUwj7UWG714/JS9LDozj61tlFQIRJzu9LrRbD66XLZonNJg==", "1; BN3PR02MB1126;\n\t6:HHlZtyP26Afy477Iq9Yo4bM/wnTY81t+XIywftTP5MCgHm501m8CTHtCWO1PoFGZHQw3+5VYeZprdibH3/WsyIHicu9BSK8XjVazDeYFP9e9VQcsKmZIk5UzppvaUXpae04dODEYnuAAamCnwLhPuwmnrNCMBIdnDDwDevSY5NCAxwqCH0FGX70aY8vNhkFmobJyZNomYBHRhTZKFG//MAP7kmAoDn/r585tV6Ult89fbNTaziICBXfGXquCZebPi0rd49R1l51AYsYgiGXZd1utOO8JLwsJXEeuhWHNEHDfKAt5E/fqkhjehimMhQmg/BIipEia5xBYk69qm0S6NQ==;\n\t5:TDRSK1H34pxuVUKIRTDkwgPCUm6sat863oxiz1P5H/ZOuyZ49A/n912xN/Iq9DC/1HAtKTbmBeRkqmprtAugqi3E2ZwV3SxnIkjmUP/z86zw1o1SsBur0FyR6VFBaGQlLz+D2du27Va7G5KgkI8ObQ==;\n\t24:MoqecuZZH/4YUj/6Hh+92xmZG+pqjKRZoYBW1SQd7WgAuUv8OXoInAj1AJGfxfDAkKvS+Oyf7j8/BU5SQawNGEN9xGiwuQ0k2G0G/2rm6Ew=;\n\t7:s81Mj6ifjViKDnvrz2whLz8Re4rdCX0gk340MKAM5H9vM02ng1U3BTdezwY/RgfwXH79tqf4dA3+dqM/U2XAw7p9tluRd2cz0iiEAWSSh0jOsmYvnOxpcwnumaZG+CcRhqQkz444fvJF5ivsg4xu5c0ffjZhngGUGKJIiYfJ8Vp1VigYW7ncWpRLvMuqr1rOLOEDM48AoILDXGwleIBueGuwzJMDihzbY3c4tcLurMw=" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "7faaf42b-f6be-4624-73e6-08d4f6b46889", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(8251501002)(300000503095)(300135400095)(2017052603199)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:BN3PR02MB1126; ", "X-MS-TrafficTypeDiagnostic": "BN3PR02MB1126:", "X-LD-Processed": "657af505-d5df-48d0-8300-c31994686c5c,ExtAddr", "X-Exchange-Antispam-Report-Test": "UriScan:(192813158149592);", "X-Microsoft-Antispam-PRVS": "<BN3PR02MB11266DDE77DBFB8FE639DC92C9950@BN3PR02MB1126.namprd02.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(93006095)(93004095)(100000703101)(100105400095)(10201501046)(3002001)(6055026)(6041248)(20161123564025)(20161123560025)(20161123562025)(20161123558100)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:BN3PR02MB1126; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN3PR02MB1126; ", "X-Forefront-PRVS": "04244E0DC5", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "xilinx.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2017 12:23:23.2904\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "657af505-d5df-48d0-8300-c31994686c5c", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=657af505-d5df-48d0-8300-c31994686c5c;\n\tIp=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR02MB1126", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Adding support for ZynqmMP PS PCIe EP driver.\nAdding support for ZynqmMP PS PCIe Root DMA driver.\nModifying Kconfig and Makefile to add the support.\n\nSigned-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com>\nSigned-off-by: RaviKiran Gummaluri <rgummal@xilinx.com>\n---\n drivers/dma/Kconfig | 12 +++\n drivers/dma/xilinx/Makefile | 2 +\n drivers/dma/xilinx/ps_pcie.h | 44 +++++++++\n drivers/dma/xilinx/ps_pcie_main.c | 200 ++++++++++++++++++++++++++++++++++++++\n include/linux/dma/ps_pcie_dma.h | 69 +++++++++++++\n 5 files changed, 327 insertions(+)\n create mode 100644 drivers/dma/xilinx/ps_pcie.h\n create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n create mode 100644 include/linux/dma/ps_pcie_dma.h", "diff": "diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\nindex fa8f9c0..e2fe4e5 100644\n--- a/drivers/dma/Kconfig\n+++ b/drivers/dma/Kconfig\n@@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA\n \thelp\n \t Enable support for Xilinx ZynqMP DMA controller.\n \n+config XILINX_PS_PCIE_DMA\n+\ttristate \"Xilinx PS PCIe DMA support\"\n+\tdepends on (PCI && X86_64 || ARM64)\n+\tselect DMA_ENGINE\n+\thelp\n+\t Enable support for the Xilinx PS PCIe DMA engine present\n+\t in recent Xilinx ZynqMP chipsets.\n+\n+\t Say Y here if you have such a chipset.\n+\n+\t If unsure, say N.\n+\n config ZX_DMA\n \ttristate \"ZTE ZX DMA support\"\n \tdepends on ARCH_ZX || COMPILE_TEST\ndiff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile\nindex 9e91f8f..04f6f99 100644\n--- a/drivers/dma/xilinx/Makefile\n+++ b/drivers/dma/xilinx/Makefile\n@@ -1,2 +1,4 @@\n obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o\n obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o\n+ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o\n+obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o\ndiff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h\nnew file mode 100644\nindex 0000000..351f051\n--- /dev/null\n+++ b/drivers/dma/xilinx/ps_pcie.h\n@@ -0,0 +1,44 @@\n+/*\n+ * Xilinx PS PCIe DMA Engine platform header file\n+ *\n+ * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.\n+ *\n+ * This program is free software: you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation\n+ */\n+\n+#ifndef __XILINX_PS_PCIE_H\n+#define __XILINX_PS_PCIE_H\n+\n+#include <linux/delay.h>\n+#include <linux/dma-direction.h>\n+#include <linux/dmaengine.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/interrupt.h>\n+#include <linux/ioport.h>\n+#include <linux/irqreturn.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/mempool.h>\n+#include <linux/of.h>\n+#include <linux/pci.h>\n+#include <linux/property.h>\n+#include <linux/platform_device.h>\n+#include <linux/timer.h>\n+#include <linux/dma/ps_pcie_dma.h>\n+\n+/**\n+ * dma_platform_driver_register - This will be invoked by module init\n+ *\n+ * Return: returns status of platform_driver_register\n+ */\n+int dma_platform_driver_register(void);\n+/**\n+ * dma_platform_driver_unregister - This will be invoked by module exit\n+ *\n+ * Return: returns void after unregustering platform driver\n+ */\n+void dma_platform_driver_unregister(void);\n+\n+#endif\ndiff --git a/drivers/dma/xilinx/ps_pcie_main.c b/drivers/dma/xilinx/ps_pcie_main.c\nnew file mode 100644\nindex 0000000..4ccd8ef\n--- /dev/null\n+++ b/drivers/dma/xilinx/ps_pcie_main.c\n@@ -0,0 +1,200 @@\n+/*\n+ * XILINX PS PCIe driver\n+ *\n+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n+ *\n+ * Description\n+ * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers\n+ * on ZynqMP UltraScale+ Devices.\n+ * This PCIe driver creates a platform device with specific platform\n+ * info enabling creation of DMA device corresponding to the channel\n+ * information provided in the properties\n+ *\n+ * This program is free software: you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation\n+ */\n+\n+#include \"ps_pcie.h\"\n+#include \"../dmaengine.h\"\n+\n+#define DRV_MODULE_NAME\t\t \"ps_pcie_dma\"\n+\n+static int ps_pcie_dma_probe(struct pci_dev *pdev,\n+\t\t\t const struct pci_device_id *ent);\n+static void ps_pcie_dma_remove(struct pci_dev *pdev);\n+\n+static u32 channel_properties_pcie_axi[] = {\n+\t(u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n+\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n+\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n+\n+static u32 channel_properties_axi_pcie[] = {\n+\t(u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n+\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n+\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n+\n+static struct property_entry generic_pcie_ep_property[] = {\n+\tPROPERTY_ENTRY_U32(\"numchannels\", (u32)MAX_NUMBER_OF_CHANNELS),\n+\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel0\",\n+\t\t\t\t channel_properties_pcie_axi),\n+\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel1\",\n+\t\t\t\t channel_properties_axi_pcie),\n+\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel2\",\n+\t\t\t\t channel_properties_pcie_axi),\n+\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel3\",\n+\t\t\t\t channel_properties_axi_pcie),\n+\t{ },\n+};\n+\n+static const struct platform_device_info xlnx_std_platform_dev_info = {\n+\t.name = XLNX_PLATFORM_DRIVER_NAME,\n+\t.properties = generic_pcie_ep_property,\n+};\n+\n+/**\n+ * ps_pcie_dma_probe - Driver probe function\n+ * @pdev: Pointer to the pci_dev structure\n+ * @ent: pci device id\n+ *\n+ * Return: '0' on success and failure value on error\n+ */\n+static int ps_pcie_dma_probe(struct pci_dev *pdev,\n+\t\t\t const struct pci_device_id *ent)\n+{\n+\tint err;\n+\tstruct platform_device *platform_dev;\n+\tstruct platform_device_info platform_dev_info;\n+\n+\tdev_info(&pdev->dev, \"PS PCIe DMA Driver probe\\n\");\n+\n+\terr = pcim_enable_device(pdev);\n+\tif (err) {\n+\t\tdev_err(&pdev->dev, \"Cannot enable PCI device, aborting\\n\");\n+\t\treturn err;\n+\t}\n+\n+\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));\n+\tif (err) {\n+\t\tdev_info(&pdev->dev, \"Cannot set 64 bit DMA mask\\n\");\n+\t\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));\n+\t\tif (err) {\n+\t\t\tdev_err(&pdev->dev, \"DMA mask set error\\n\");\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n+\tif (err) {\n+\t\tdev_info(&pdev->dev, \"Cannot set 64 bit consistent DMA mask\\n\");\n+\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n+\t\tif (err) {\n+\t\t\tdev_err(&pdev->dev, \"Cannot set consistent DMA mask\\n\");\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\tpci_set_master(pdev);\n+\n+\t/* For Root DMA platform device will be created through device tree */\n+\tif (pdev->vendor == PCI_VENDOR_ID_XILINX &&\n+\t pdev->device == ZYNQMP_RC_DMA_DEVID)\n+\t\treturn 0;\n+\n+\tmemcpy(&platform_dev_info, &xlnx_std_platform_dev_info,\n+\t sizeof(xlnx_std_platform_dev_info));\n+\n+\t/* Do device specific channel configuration changes to\n+\t * platform_dev_info.properties if required\n+\t * More information on channel properties can be found\n+\t * at Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n+\t */\n+\n+\tplatform_dev_info.parent = &pdev->dev;\n+\tplatform_dev_info.data = &pdev;\n+\tplatform_dev_info.size_data = sizeof(struct pci_dev **);\n+\n+\tplatform_dev = platform_device_register_full(&platform_dev_info);\n+\tif (IS_ERR(platform_dev)) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"Cannot create platform device, aborting\\n\");\n+\t\treturn PTR_ERR(platform_dev);\n+\t}\n+\n+\tpci_set_drvdata(pdev, platform_dev);\n+\n+\tdev_info(&pdev->dev, \"PS PCIe DMA driver successfully probed\\n\");\n+\n+\treturn 0;\n+}\n+\n+static struct pci_device_id ps_pcie_dma_tbl[] = {\n+\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_DMA_DEVID) },\n+\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_RC_DMA_DEVID) },\n+\t{ }\n+};\n+\n+static struct pci_driver ps_pcie_dma_driver = {\n+\t.name = DRV_MODULE_NAME,\n+\t.id_table = ps_pcie_dma_tbl,\n+\t.probe = ps_pcie_dma_probe,\n+\t.remove = ps_pcie_dma_remove,\n+};\n+\n+/**\n+ * ps_pcie_init - Driver init function\n+ *\n+ * Return: 0 on success. Non zero on failure\n+ */\n+static int __init ps_pcie_init(void)\n+{\n+\tint ret;\n+\n+\tpr_info(\"%s init()\\n\", DRV_MODULE_NAME);\n+\n+\tret = pci_register_driver(&ps_pcie_dma_driver);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dma_platform_driver_register();\n+\tif (ret)\n+\t\tpci_unregister_driver(&ps_pcie_dma_driver);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * ps_pcie_dma_remove - Driver remove function\n+ * @pdev: Pointer to the pci_dev structure\n+ *\n+ * Return: void\n+ */\n+static void ps_pcie_dma_remove(struct pci_dev *pdev)\n+{\n+\tstruct platform_device *platform_dev;\n+\n+\tplatform_dev = (struct platform_device *)pci_get_drvdata(pdev);\n+\n+\tif (platform_dev)\n+\t\tplatform_device_unregister(platform_dev);\n+}\n+\n+/**\n+ * ps_pcie_exit - Driver exit function\n+ *\n+ * Return: void\n+ */\n+static void __exit ps_pcie_exit(void)\n+{\n+\tpr_info(\"%s exit()\\n\", DRV_MODULE_NAME);\n+\n+\tdma_platform_driver_unregister();\n+\tpci_unregister_driver(&ps_pcie_dma_driver);\n+}\n+\n+module_init(ps_pcie_init);\n+module_exit(ps_pcie_exit);\n+\n+MODULE_AUTHOR(\"Xilinx Inc\");\n+MODULE_DESCRIPTION(\"Xilinx PS PCIe DMA Driver\");\n+MODULE_LICENSE(\"GPL v2\");\ndiff --git a/include/linux/dma/ps_pcie_dma.h b/include/linux/dma/ps_pcie_dma.h\nnew file mode 100644\nindex 0000000..d11323a\n--- /dev/null\n+++ b/include/linux/dma/ps_pcie_dma.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Xilinx PS PCIe DMA Engine support header file\n+ *\n+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n+ *\n+ * This program is free software: you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation\n+ */\n+\n+#ifndef __DMA_XILINX_PS_PCIE_H\n+#define __DMA_XILINX_PS_PCIE_H\n+\n+#include <linux/dma-mapping.h>\n+#include <linux/dmaengine.h>\n+\n+#define XLNX_PLATFORM_DRIVER_NAME \"xlnx-platform-dma-driver\"\n+\n+#define ZYNQMP_DMA_DEVID\t(0xD024)\n+#define ZYNQMP_RC_DMA_DEVID\t(0xD021)\n+\n+#define MAX_ALLOWED_CHANNELS_IN_HW\t4\n+\n+#define MAX_NUMBER_OF_CHANNELS\tMAX_ALLOWED_CHANNELS_IN_HW\n+\n+#define DEFAULT_DMA_QUEUES\t4\n+#define TWO_DMA_QUEUES\t\t2\n+\n+#define NUMBER_OF_BUFFER_DESCRIPTORS\t1999\n+#define MAX_DESCRIPTORS\t\t\t65536\n+\n+#define CHANNEL_COAELSE_COUNT\t\t0\n+\n+#define CHANNEL_POLL_TIMER_FREQUENCY\t1000 /* in milli seconds */\n+\n+#define PCIE_AXI_DIRECTION\tDMA_TO_DEVICE\n+#define AXI_PCIE_DIRECTION\tDMA_FROM_DEVICE\n+\n+/**\n+ * struct BAR_PARAMS - PCIe Bar Parameters\n+ * @BAR_PHYS_ADDR: PCIe BAR Physical address\n+ * @BAR_LENGTH: Length of PCIe BAR\n+ * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR\n+ */\n+struct BAR_PARAMS {\n+\tdma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */\n+\tunsigned long BAR_LENGTH; /**< Length of BAR memory window */\n+\tvoid *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */\n+};\n+\n+/**\n+ * struct ps_pcie_dma_channel_match - Match structure for dma clients\n+ * @pci_vendorid: PCIe Vendor id of PS PCIe DMA device\n+ * @pci_deviceid: PCIe Device id of PS PCIe DMA device\n+ * @board_number: Unique id to identify individual device in a system\n+ * @channel_number: Unique channel number of the device\n+ * @direction: DMA channel direction\n+ * @bar_params: Pointer to BAR_PARAMS for accessing application specific data\n+ */\n+struct ps_pcie_dma_channel_match {\n+\tu16 pci_vendorid;\n+\tu16 pci_deviceid;\n+\tu16 board_number;\n+\tu16 channel_number;\n+\tenum dma_data_direction direction;\n+\tstruct BAR_PARAMS *bar_params;\n+};\n+\n+#endif\n", "prefixes": [ "v2", "3/5" ] }