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GET /api/patches/811533/?format=api
{ "id": 811533, "url": "http://patchwork.ozlabs.org/api/patches/811533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-23-david@gibson.dropbear.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170908103558.31632-23-david@gibson.dropbear.id.au>", "list_archive_url": null, "date": "2017-09-08T10:35:40", "name": "[PULL,22/40] ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e3ffaf4bcf64fc16117027cbb926c062e6ee6c9", "submitter": { "id": 47, "url": "http://patchwork.ozlabs.org/api/people/47/?format=api", "name": "David Gibson", "email": "david@gibson.dropbear.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-23-david@gibson.dropbear.id.au/mbox/", "series": [ { "id": 2179, "url": "http://patchwork.ozlabs.org/api/series/2179/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179", "date": "2017-09-08T10:35:20", "name": "[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2179/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811533/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"EvG8dNXh\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpZHR2TnCz9s83\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 21:05:39 +1000 (AEST)", "from localhost ([::1]:44595 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dqH6P-0002LC-Ey\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 07:05:37 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:58892)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1dqGeE-0002GX-L9\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:42 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1dqGe5-0003LW-WD\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:30 -0400", "from ozlabs.org ([103.22.144.67]:56449)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <dgibson@ozlabs.org>)\n\tid 1dqGe5-0003HN-CU; Fri, 08 Sep 2017 06:36:21 -0400", "by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdP4hl2z9t63; Fri, 8 Sep 2017 20:36:05 +1000 (AEST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866969;\n\tbh=E2bOTgGCqLgrbSoHKnzxueM5iFk3BTQ1lNoVW9vMH6s=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=EvG8dNXh+REtgEIEEEnj4kqniynrv9lnQsM2hzc6gOOIYZwI2kJOsj/ighDUwkSt/\n\tToQhT5BGqr1cd8hol0Gcp4u8+eyeXAjwIdg+aivCj1KQwuG4oEVGEhQrsNVTKx9Iuo\n\tHOi9/oXjIpcS3Vi1N3Lr9DnMOYLZUpRYTaqarjag=", "From": "David Gibson <david@gibson.dropbear.id.au>", "To": "peter.maydell@linaro.org", "Date": "Fri, 8 Sep 2017 20:35:40 +1000", "Message-Id": "<20170908103558.31632-23-david@gibson.dropbear.id.au>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170908103558.31632-1-david@gibson.dropbear.id.au>", "References": "<20170908103558.31632-1-david@gibson.dropbear.id.au>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "103.22.144.67", "Subject": "[Qemu-devel] [PULL 22/40] ppc4xx: Move MAL from ppc405_uc to\n\tppc4xx_devs", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org,\n\timammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson <david@gibson.dropbear.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: BALATON Zoltan <balaton@eik.bme.hu>\n\nThis device appears in other SoCs as well not just in 405 ones\n\nSigned-off-by: BALATON Zoltan <balaton@eik.bme.hu>\nReviewed-by: David Gibson <david@gibson.dropbear.id.au>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n---\n hw/ppc/ppc405_uc.c | 263 -----------------------------------------------\n hw/ppc/ppc4xx_devs.c | 264 ++++++++++++++++++++++++++++++++++++++++++++++++\n include/hw/ppc/ppc4xx.h | 2 +\n 3 files changed, 266 insertions(+), 263 deletions(-)", "diff": "diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c\nindex f6fe3e6f5e..3c744021d6 100644\n--- a/hw/ppc/ppc405_uc.c\n+++ b/hw/ppc/ppc405_uc.c\n@@ -42,7 +42,6 @@\n //#define DEBUG_OCM\n //#define DEBUG_I2C\n //#define DEBUG_GPT\n-//#define DEBUG_MAL\n //#define DEBUG_CLOCKS\n //#define DEBUG_CLOCKS_LL\n \n@@ -1513,268 +1512,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])\n }\n \n /*****************************************************************************/\n-/* MAL */\n-enum {\n- MAL0_CFG = 0x180,\n- MAL0_ESR = 0x181,\n- MAL0_IER = 0x182,\n- MAL0_TXCASR = 0x184,\n- MAL0_TXCARR = 0x185,\n- MAL0_TXEOBISR = 0x186,\n- MAL0_TXDEIR = 0x187,\n- MAL0_RXCASR = 0x190,\n- MAL0_RXCARR = 0x191,\n- MAL0_RXEOBISR = 0x192,\n- MAL0_RXDEIR = 0x193,\n- MAL0_TXCTP0R = 0x1A0,\n- MAL0_TXCTP1R = 0x1A1,\n- MAL0_TXCTP2R = 0x1A2,\n- MAL0_TXCTP3R = 0x1A3,\n- MAL0_RXCTP0R = 0x1C0,\n- MAL0_RXCTP1R = 0x1C1,\n- MAL0_RCBS0 = 0x1E0,\n- MAL0_RCBS1 = 0x1E1,\n-};\n-\n-typedef struct ppc40x_mal_t ppc40x_mal_t;\n-struct ppc40x_mal_t {\n- qemu_irq irqs[4];\n- uint32_t cfg;\n- uint32_t esr;\n- uint32_t ier;\n- uint32_t txcasr;\n- uint32_t txcarr;\n- uint32_t txeobisr;\n- uint32_t txdeir;\n- uint32_t rxcasr;\n- uint32_t rxcarr;\n- uint32_t rxeobisr;\n- uint32_t rxdeir;\n- uint32_t txctpr[4];\n- uint32_t rxctpr[2];\n- uint32_t rcbs[2];\n-};\n-\n-static void ppc40x_mal_reset (void *opaque);\n-\n-static uint32_t dcr_read_mal (void *opaque, int dcrn)\n-{\n- ppc40x_mal_t *mal;\n- uint32_t ret;\n-\n- mal = opaque;\n- switch (dcrn) {\n- case MAL0_CFG:\n- ret = mal->cfg;\n- break;\n- case MAL0_ESR:\n- ret = mal->esr;\n- break;\n- case MAL0_IER:\n- ret = mal->ier;\n- break;\n- case MAL0_TXCASR:\n- ret = mal->txcasr;\n- break;\n- case MAL0_TXCARR:\n- ret = mal->txcarr;\n- break;\n- case MAL0_TXEOBISR:\n- ret = mal->txeobisr;\n- break;\n- case MAL0_TXDEIR:\n- ret = mal->txdeir;\n- break;\n- case MAL0_RXCASR:\n- ret = mal->rxcasr;\n- break;\n- case MAL0_RXCARR:\n- ret = mal->rxcarr;\n- break;\n- case MAL0_RXEOBISR:\n- ret = mal->rxeobisr;\n- break;\n- case MAL0_RXDEIR:\n- ret = mal->rxdeir;\n- break;\n- case MAL0_TXCTP0R:\n- ret = mal->txctpr[0];\n- break;\n- case MAL0_TXCTP1R:\n- ret = mal->txctpr[1];\n- break;\n- case MAL0_TXCTP2R:\n- ret = mal->txctpr[2];\n- break;\n- case MAL0_TXCTP3R:\n- ret = mal->txctpr[3];\n- break;\n- case MAL0_RXCTP0R:\n- ret = mal->rxctpr[0];\n- break;\n- case MAL0_RXCTP1R:\n- ret = mal->rxctpr[1];\n- break;\n- case MAL0_RCBS0:\n- ret = mal->rcbs[0];\n- break;\n- case MAL0_RCBS1:\n- ret = mal->rcbs[1];\n- break;\n- default:\n- ret = 0;\n- break;\n- }\n-\n- return ret;\n-}\n-\n-static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)\n-{\n- ppc40x_mal_t *mal;\n- int idx;\n-\n- mal = opaque;\n- switch (dcrn) {\n- case MAL0_CFG:\n- if (val & 0x80000000)\n- ppc40x_mal_reset(mal);\n- mal->cfg = val & 0x00FFC087;\n- break;\n- case MAL0_ESR:\n- /* Read/clear */\n- mal->esr &= ~val;\n- break;\n- case MAL0_IER:\n- mal->ier = val & 0x0000001F;\n- break;\n- case MAL0_TXCASR:\n- mal->txcasr = val & 0xF0000000;\n- break;\n- case MAL0_TXCARR:\n- mal->txcarr = val & 0xF0000000;\n- break;\n- case MAL0_TXEOBISR:\n- /* Read/clear */\n- mal->txeobisr &= ~val;\n- break;\n- case MAL0_TXDEIR:\n- /* Read/clear */\n- mal->txdeir &= ~val;\n- break;\n- case MAL0_RXCASR:\n- mal->rxcasr = val & 0xC0000000;\n- break;\n- case MAL0_RXCARR:\n- mal->rxcarr = val & 0xC0000000;\n- break;\n- case MAL0_RXEOBISR:\n- /* Read/clear */\n- mal->rxeobisr &= ~val;\n- break;\n- case MAL0_RXDEIR:\n- /* Read/clear */\n- mal->rxdeir &= ~val;\n- break;\n- case MAL0_TXCTP0R:\n- idx = 0;\n- goto update_tx_ptr;\n- case MAL0_TXCTP1R:\n- idx = 1;\n- goto update_tx_ptr;\n- case MAL0_TXCTP2R:\n- idx = 2;\n- goto update_tx_ptr;\n- case MAL0_TXCTP3R:\n- idx = 3;\n- update_tx_ptr:\n- mal->txctpr[idx] = val;\n- break;\n- case MAL0_RXCTP0R:\n- idx = 0;\n- goto update_rx_ptr;\n- case MAL0_RXCTP1R:\n- idx = 1;\n- update_rx_ptr:\n- mal->rxctpr[idx] = val;\n- break;\n- case MAL0_RCBS0:\n- idx = 0;\n- goto update_rx_size;\n- case MAL0_RCBS1:\n- idx = 1;\n- update_rx_size:\n- mal->rcbs[idx] = val & 0x000000FF;\n- break;\n- }\n-}\n-\n-static void ppc40x_mal_reset (void *opaque)\n-{\n- ppc40x_mal_t *mal;\n-\n- mal = opaque;\n- mal->cfg = 0x0007C000;\n- mal->esr = 0x00000000;\n- mal->ier = 0x00000000;\n- mal->rxcasr = 0x00000000;\n- mal->rxdeir = 0x00000000;\n- mal->rxeobisr = 0x00000000;\n- mal->txcasr = 0x00000000;\n- mal->txdeir = 0x00000000;\n- mal->txeobisr = 0x00000000;\n-}\n-\n-static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])\n-{\n- ppc40x_mal_t *mal;\n- int i;\n-\n- mal = g_malloc0(sizeof(ppc40x_mal_t));\n- for (i = 0; i < 4; i++)\n- mal->irqs[i] = irqs[i];\n- qemu_register_reset(&ppc40x_mal_reset, mal);\n- ppc_dcr_register(env, MAL0_CFG,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_ESR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_IER,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCASR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCARR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXEOBISR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXDEIR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCASR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCARR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXEOBISR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXDEIR,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP0R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP1R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP2R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP3R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCTP0R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCTP1R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RCBS0,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RCBS1,\n- mal, &dcr_read_mal, &dcr_write_mal);\n-}\n-\n-/*****************************************************************************/\n /* SPR */\n void ppc40x_core_reset(PowerPCCPU *cpu)\n {\ndiff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c\nindex 6b38ed7bc7..b296ea66c2 100644\n--- a/hw/ppc/ppc4xx_devs.c\n+++ b/hw/ppc/ppc4xx_devs.c\n@@ -734,3 +734,267 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,\n \n return ram_size;\n }\n+\n+/*****************************************************************************/\n+/* MAL */\n+enum {\n+ MAL0_CFG = 0x180,\n+ MAL0_ESR = 0x181,\n+ MAL0_IER = 0x182,\n+ MAL0_TXCASR = 0x184,\n+ MAL0_TXCARR = 0x185,\n+ MAL0_TXEOBISR = 0x186,\n+ MAL0_TXDEIR = 0x187,\n+ MAL0_RXCASR = 0x190,\n+ MAL0_RXCARR = 0x191,\n+ MAL0_RXEOBISR = 0x192,\n+ MAL0_RXDEIR = 0x193,\n+ MAL0_TXCTP0R = 0x1A0,\n+ MAL0_TXCTP1R = 0x1A1,\n+ MAL0_TXCTP2R = 0x1A2,\n+ MAL0_TXCTP3R = 0x1A3,\n+ MAL0_RXCTP0R = 0x1C0,\n+ MAL0_RXCTP1R = 0x1C1,\n+ MAL0_RCBS0 = 0x1E0,\n+ MAL0_RCBS1 = 0x1E1,\n+};\n+\n+typedef struct ppc40x_mal_t ppc40x_mal_t;\n+struct ppc40x_mal_t {\n+ qemu_irq irqs[4];\n+ uint32_t cfg;\n+ uint32_t esr;\n+ uint32_t ier;\n+ uint32_t txcasr;\n+ uint32_t txcarr;\n+ uint32_t txeobisr;\n+ uint32_t txdeir;\n+ uint32_t rxcasr;\n+ uint32_t rxcarr;\n+ uint32_t rxeobisr;\n+ uint32_t rxdeir;\n+ uint32_t txctpr[4];\n+ uint32_t rxctpr[2];\n+ uint32_t rcbs[2];\n+};\n+\n+static void ppc40x_mal_reset(void *opaque);\n+\n+static uint32_t dcr_read_mal(void *opaque, int dcrn)\n+{\n+ ppc40x_mal_t *mal;\n+ uint32_t ret;\n+\n+ mal = opaque;\n+ switch (dcrn) {\n+ case MAL0_CFG:\n+ ret = mal->cfg;\n+ break;\n+ case MAL0_ESR:\n+ ret = mal->esr;\n+ break;\n+ case MAL0_IER:\n+ ret = mal->ier;\n+ break;\n+ case MAL0_TXCASR:\n+ ret = mal->txcasr;\n+ break;\n+ case MAL0_TXCARR:\n+ ret = mal->txcarr;\n+ break;\n+ case MAL0_TXEOBISR:\n+ ret = mal->txeobisr;\n+ break;\n+ case MAL0_TXDEIR:\n+ ret = mal->txdeir;\n+ break;\n+ case MAL0_RXCASR:\n+ ret = mal->rxcasr;\n+ break;\n+ case MAL0_RXCARR:\n+ ret = mal->rxcarr;\n+ break;\n+ case MAL0_RXEOBISR:\n+ ret = mal->rxeobisr;\n+ break;\n+ case MAL0_RXDEIR:\n+ ret = mal->rxdeir;\n+ break;\n+ case MAL0_TXCTP0R:\n+ ret = mal->txctpr[0];\n+ break;\n+ case MAL0_TXCTP1R:\n+ ret = mal->txctpr[1];\n+ break;\n+ case MAL0_TXCTP2R:\n+ ret = mal->txctpr[2];\n+ break;\n+ case MAL0_TXCTP3R:\n+ ret = mal->txctpr[3];\n+ break;\n+ case MAL0_RXCTP0R:\n+ ret = mal->rxctpr[0];\n+ break;\n+ case MAL0_RXCTP1R:\n+ ret = mal->rxctpr[1];\n+ break;\n+ case MAL0_RCBS0:\n+ ret = mal->rcbs[0];\n+ break;\n+ case MAL0_RCBS1:\n+ ret = mal->rcbs[1];\n+ break;\n+ default:\n+ ret = 0;\n+ break;\n+ }\n+\n+ return ret;\n+}\n+\n+static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)\n+{\n+ ppc40x_mal_t *mal;\n+ int idx;\n+\n+ mal = opaque;\n+ switch (dcrn) {\n+ case MAL0_CFG:\n+ if (val & 0x80000000) {\n+ ppc40x_mal_reset(mal);\n+ }\n+ mal->cfg = val & 0x00FFC087;\n+ break;\n+ case MAL0_ESR:\n+ /* Read/clear */\n+ mal->esr &= ~val;\n+ break;\n+ case MAL0_IER:\n+ mal->ier = val & 0x0000001F;\n+ break;\n+ case MAL0_TXCASR:\n+ mal->txcasr = val & 0xF0000000;\n+ break;\n+ case MAL0_TXCARR:\n+ mal->txcarr = val & 0xF0000000;\n+ break;\n+ case MAL0_TXEOBISR:\n+ /* Read/clear */\n+ mal->txeobisr &= ~val;\n+ break;\n+ case MAL0_TXDEIR:\n+ /* Read/clear */\n+ mal->txdeir &= ~val;\n+ break;\n+ case MAL0_RXCASR:\n+ mal->rxcasr = val & 0xC0000000;\n+ break;\n+ case MAL0_RXCARR:\n+ mal->rxcarr = val & 0xC0000000;\n+ break;\n+ case MAL0_RXEOBISR:\n+ /* Read/clear */\n+ mal->rxeobisr &= ~val;\n+ break;\n+ case MAL0_RXDEIR:\n+ /* Read/clear */\n+ mal->rxdeir &= ~val;\n+ break;\n+ case MAL0_TXCTP0R:\n+ idx = 0;\n+ goto update_tx_ptr;\n+ case MAL0_TXCTP1R:\n+ idx = 1;\n+ goto update_tx_ptr;\n+ case MAL0_TXCTP2R:\n+ idx = 2;\n+ goto update_tx_ptr;\n+ case MAL0_TXCTP3R:\n+ idx = 3;\n+ update_tx_ptr:\n+ mal->txctpr[idx] = val;\n+ break;\n+ case MAL0_RXCTP0R:\n+ idx = 0;\n+ goto update_rx_ptr;\n+ case MAL0_RXCTP1R:\n+ idx = 1;\n+ update_rx_ptr:\n+ mal->rxctpr[idx] = val;\n+ break;\n+ case MAL0_RCBS0:\n+ idx = 0;\n+ goto update_rx_size;\n+ case MAL0_RCBS1:\n+ idx = 1;\n+ update_rx_size:\n+ mal->rcbs[idx] = val & 0x000000FF;\n+ break;\n+ }\n+}\n+\n+static void ppc40x_mal_reset(void *opaque)\n+{\n+ ppc40x_mal_t *mal;\n+\n+ mal = opaque;\n+ mal->cfg = 0x0007C000;\n+ mal->esr = 0x00000000;\n+ mal->ier = 0x00000000;\n+ mal->rxcasr = 0x00000000;\n+ mal->rxdeir = 0x00000000;\n+ mal->rxeobisr = 0x00000000;\n+ mal->txcasr = 0x00000000;\n+ mal->txdeir = 0x00000000;\n+ mal->txeobisr = 0x00000000;\n+}\n+\n+void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])\n+{\n+ ppc40x_mal_t *mal;\n+ int i;\n+\n+ mal = g_malloc0(sizeof(ppc40x_mal_t));\n+ for (i = 0; i < 4; i++) {\n+ mal->irqs[i] = irqs[i];\n+ }\n+ qemu_register_reset(&ppc40x_mal_reset, mal);\n+ ppc_dcr_register(env, MAL0_CFG,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_ESR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_IER,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCASR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCARR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXEOBISR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXDEIR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXCASR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXCARR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXEOBISR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXDEIR,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCTP0R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCTP1R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCTP2R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_TXCTP3R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXCTP0R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RXCTP1R,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RCBS0,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ ppc_dcr_register(env, MAL0_RCBS1,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+}\ndiff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h\nindex 66e57a5194..db50cfac02 100644\n--- a/include/hw/ppc/ppc4xx.h\n+++ b/include/hw/ppc/ppc4xx.h\n@@ -53,6 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,\n hwaddr *ram_sizes,\n int do_init);\n \n+void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]);\n+\n #define TYPE_PPC4xx_PCI_HOST_BRIDGE \"ppc4xx-pcihost\"\n \n #endif /* PPC4XX_H */\n", "prefixes": [ "PULL", "22/40" ] }