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GET /api/patches/811531/?format=api
{ "id": 811531, "url": "http://patchwork.ozlabs.org/api/patches/811531/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-24-david@gibson.dropbear.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170908103558.31632-24-david@gibson.dropbear.id.au>", "list_archive_url": null, "date": "2017-09-08T10:35:41", "name": "[PULL,23/40] ppc4xx: Make MAL emulation more generic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a1d1ce9a017f698ae13ee215b7ec6016f669b892", "submitter": { "id": 47, "url": "http://patchwork.ozlabs.org/api/people/47/?format=api", "name": "David Gibson", "email": "david@gibson.dropbear.id.au" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170908103558.31632-24-david@gibson.dropbear.id.au/mbox/", "series": [ { "id": 2179, "url": "http://patchwork.ozlabs.org/api/series/2179/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2179", "date": "2017-09-08T10:35:20", "name": "[PULL,01/40] hw/ppc/spapr_drc.c: change spapr_drc_needed to use drc->dev", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2179/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811531/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811531/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"Q7BIb3HW\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpZF33tywz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 21:03:35 +1000 (AEST)", "from localhost ([::1]:44582 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dqH4P-0000dT-Ia\n\tfor incoming@patchwork.ozlabs.org; Fri, 08 Sep 2017 07:03:33 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:58801)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1dqGeA-0002Du-IW\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:37 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1dqGe3-0003IK-Ef\n\tfor qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:26 -0400", "from ozlabs.org ([103.22.144.67]:57411)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <dgibson@ozlabs.org>)\n\tid 1dqGe2-0003FY-Qo; Fri, 08 Sep 2017 06:36:19 -0400", "by ozlabs.org (Postfix, from userid 1007)\n\tid 3xpYdP1RSRz9t5h; Fri, 8 Sep 2017 20:36:05 +1000 (AEST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1504866969;\n\tbh=jnm0a6a0YbVHVnmGQZi3FlzyTJ20sCwj2wfkNfIPn/Y=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Q7BIb3HWYA159Z/AdgU4Fhtepjrzk4mQYL6cW6y0XER1l/GKXc+l7khwBXdrv6lZo\n\tlTVbNKbUdPITMkojjuGCWKvRD0qm+WtvlH/8ZL3B4lrtR2gk0sCbQ9FHnV1LGgU3y0\n\ttNUaSXFOPtSL9A59sNe/SoQqYbJZJlVFvEmJ9BWk=", "From": "David Gibson <david@gibson.dropbear.id.au>", "To": "peter.maydell@linaro.org", "Date": "Fri, 8 Sep 2017 20:35:41 +1000", "Message-Id": "<20170908103558.31632-24-david@gibson.dropbear.id.au>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170908103558.31632-1-david@gibson.dropbear.id.au>", "References": "<20170908103558.31632-1-david@gibson.dropbear.id.au>", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "103.22.144.67", "Subject": "[Qemu-devel] [PULL 23/40] ppc4xx: Make MAL emulation more generic", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de,\n\tmdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org,\n\timammedo@redhat.com, sam.bobroff@au1.ibm.com,\n\tDavid Gibson <david@gibson.dropbear.id.au>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: BALATON Zoltan <balaton@eik.bme.hu>\n\nAllow MAL with more RX and TX channels as found in newer versions.\n\nSigned-off-by: BALATON Zoltan <balaton@eik.bme.hu>\nReviewed-by: David Gibson <david@gibson.dropbear.id.au>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n---\n hw/ppc/ppc405_uc.c | 2 +-\n hw/ppc/ppc4xx_devs.c | 171 +++++++++++++++++++-----------------------------\n include/hw/ppc/ppc4xx.h | 3 +-\n 3 files changed, 70 insertions(+), 106 deletions(-)", "diff": "diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c\nindex 3c744021d6..03856d573f 100644\n--- a/hw/ppc/ppc405_uc.c\n+++ b/hw/ppc/ppc405_uc.c\n@@ -2281,7 +2281,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,\n mal_irqs[1] = pic[12];\n mal_irqs[2] = pic[13];\n mal_irqs[3] = pic[14];\n- ppc405_mal_init(env, mal_irqs);\n+ ppc4xx_mal_init(env, 4, 2, mal_irqs);\n /* Ethernet */\n /* Uses pic[9], pic[15], pic[17] */\n /* CPU control */\ndiff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c\nindex b296ea66c2..ec90f13295 100644\n--- a/hw/ppc/ppc4xx_devs.c\n+++ b/hw/ppc/ppc4xx_devs.c\n@@ -737,6 +737,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,\n \n /*****************************************************************************/\n /* MAL */\n+\n enum {\n MAL0_CFG = 0x180,\n MAL0_ESR = 0x181,\n@@ -750,17 +751,13 @@ enum {\n MAL0_RXEOBISR = 0x192,\n MAL0_RXDEIR = 0x193,\n MAL0_TXCTP0R = 0x1A0,\n- MAL0_TXCTP1R = 0x1A1,\n- MAL0_TXCTP2R = 0x1A2,\n- MAL0_TXCTP3R = 0x1A3,\n MAL0_RXCTP0R = 0x1C0,\n- MAL0_RXCTP1R = 0x1C1,\n MAL0_RCBS0 = 0x1E0,\n MAL0_RCBS1 = 0x1E1,\n };\n \n-typedef struct ppc40x_mal_t ppc40x_mal_t;\n-struct ppc40x_mal_t {\n+typedef struct ppc4xx_mal_t ppc4xx_mal_t;\n+struct ppc4xx_mal_t {\n qemu_irq irqs[4];\n uint32_t cfg;\n uint32_t esr;\n@@ -773,16 +770,32 @@ struct ppc40x_mal_t {\n uint32_t rxcarr;\n uint32_t rxeobisr;\n uint32_t rxdeir;\n- uint32_t txctpr[4];\n- uint32_t rxctpr[2];\n- uint32_t rcbs[2];\n+ uint32_t *txctpr;\n+ uint32_t *rxctpr;\n+ uint32_t *rcbs;\n+ uint8_t txcnum;\n+ uint8_t rxcnum;\n };\n \n-static void ppc40x_mal_reset(void *opaque);\n+static void ppc4xx_mal_reset(void *opaque)\n+{\n+ ppc4xx_mal_t *mal;\n+\n+ mal = opaque;\n+ mal->cfg = 0x0007C000;\n+ mal->esr = 0x00000000;\n+ mal->ier = 0x00000000;\n+ mal->rxcasr = 0x00000000;\n+ mal->rxdeir = 0x00000000;\n+ mal->rxeobisr = 0x00000000;\n+ mal->txcasr = 0x00000000;\n+ mal->txdeir = 0x00000000;\n+ mal->txeobisr = 0x00000000;\n+}\n \n static uint32_t dcr_read_mal(void *opaque, int dcrn)\n {\n- ppc40x_mal_t *mal;\n+ ppc4xx_mal_t *mal;\n uint32_t ret;\n \n mal = opaque;\n@@ -820,48 +833,32 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)\n case MAL0_RXDEIR:\n ret = mal->rxdeir;\n break;\n- case MAL0_TXCTP0R:\n- ret = mal->txctpr[0];\n- break;\n- case MAL0_TXCTP1R:\n- ret = mal->txctpr[1];\n- break;\n- case MAL0_TXCTP2R:\n- ret = mal->txctpr[2];\n- break;\n- case MAL0_TXCTP3R:\n- ret = mal->txctpr[3];\n- break;\n- case MAL0_RXCTP0R:\n- ret = mal->rxctpr[0];\n- break;\n- case MAL0_RXCTP1R:\n- ret = mal->rxctpr[1];\n- break;\n- case MAL0_RCBS0:\n- ret = mal->rcbs[0];\n- break;\n- case MAL0_RCBS1:\n- ret = mal->rcbs[1];\n- break;\n default:\n ret = 0;\n break;\n }\n+ if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {\n+ ret = mal->txctpr[dcrn - MAL0_TXCTP0R];\n+ }\n+ if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {\n+ ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];\n+ }\n+ if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {\n+ ret = mal->rcbs[dcrn - MAL0_RCBS0];\n+ }\n \n return ret;\n }\n \n static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)\n {\n- ppc40x_mal_t *mal;\n- int idx;\n+ ppc4xx_mal_t *mal;\n \n mal = opaque;\n switch (dcrn) {\n case MAL0_CFG:\n if (val & 0x80000000) {\n- ppc40x_mal_reset(mal);\n+ ppc4xx_mal_reset(mal);\n }\n mal->cfg = val & 0x00FFC087;\n break;\n@@ -900,65 +897,35 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)\n /* Read/clear */\n mal->rxdeir &= ~val;\n break;\n- case MAL0_TXCTP0R:\n- idx = 0;\n- goto update_tx_ptr;\n- case MAL0_TXCTP1R:\n- idx = 1;\n- goto update_tx_ptr;\n- case MAL0_TXCTP2R:\n- idx = 2;\n- goto update_tx_ptr;\n- case MAL0_TXCTP3R:\n- idx = 3;\n- update_tx_ptr:\n- mal->txctpr[idx] = val;\n- break;\n- case MAL0_RXCTP0R:\n- idx = 0;\n- goto update_rx_ptr;\n- case MAL0_RXCTP1R:\n- idx = 1;\n- update_rx_ptr:\n- mal->rxctpr[idx] = val;\n- break;\n- case MAL0_RCBS0:\n- idx = 0;\n- goto update_rx_size;\n- case MAL0_RCBS1:\n- idx = 1;\n- update_rx_size:\n- mal->rcbs[idx] = val & 0x000000FF;\n- break;\n+ }\n+ if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {\n+ mal->txctpr[dcrn - MAL0_TXCTP0R] = val;\n+ }\n+ if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {\n+ mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;\n+ }\n+ if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {\n+ mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;\n }\n }\n \n-static void ppc40x_mal_reset(void *opaque)\n-{\n- ppc40x_mal_t *mal;\n-\n- mal = opaque;\n- mal->cfg = 0x0007C000;\n- mal->esr = 0x00000000;\n- mal->ier = 0x00000000;\n- mal->rxcasr = 0x00000000;\n- mal->rxdeir = 0x00000000;\n- mal->rxeobisr = 0x00000000;\n- mal->txcasr = 0x00000000;\n- mal->txdeir = 0x00000000;\n- mal->txeobisr = 0x00000000;\n-}\n-\n-void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])\n+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,\n+ qemu_irq irqs[4])\n {\n- ppc40x_mal_t *mal;\n+ ppc4xx_mal_t *mal;\n int i;\n \n- mal = g_malloc0(sizeof(ppc40x_mal_t));\n+ assert(txcnum <= 32 && rxcnum <= 32);\n+ mal = g_malloc0(sizeof(*mal));\n+ mal->txcnum = txcnum;\n+ mal->rxcnum = rxcnum;\n+ mal->txctpr = g_new0(uint32_t, txcnum);\n+ mal->rxctpr = g_new0(uint32_t, rxcnum);\n+ mal->rcbs = g_new0(uint32_t, rxcnum);\n for (i = 0; i < 4; i++) {\n mal->irqs[i] = irqs[i];\n }\n- qemu_register_reset(&ppc40x_mal_reset, mal);\n+ qemu_register_reset(&ppc4xx_mal_reset, mal);\n ppc_dcr_register(env, MAL0_CFG,\n mal, &dcr_read_mal, &dcr_write_mal);\n ppc_dcr_register(env, MAL0_ESR,\n@@ -981,20 +948,16 @@ void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])\n mal, &dcr_read_mal, &dcr_write_mal);\n ppc_dcr_register(env, MAL0_RXDEIR,\n mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP0R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP1R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP2R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_TXCTP3R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCTP0R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RXCTP1R,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RCBS0,\n- mal, &dcr_read_mal, &dcr_write_mal);\n- ppc_dcr_register(env, MAL0_RCBS1,\n- mal, &dcr_read_mal, &dcr_write_mal);\n+ for (i = 0; i < txcnum; i++) {\n+ ppc_dcr_register(env, MAL0_TXCTP0R + i,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ }\n+ for (i = 0; i < rxcnum; i++) {\n+ ppc_dcr_register(env, MAL0_RXCTP0R + i,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ }\n+ for (i = 0; i < rxcnum; i++) {\n+ ppc_dcr_register(env, MAL0_RCBS0 + i,\n+ mal, &dcr_read_mal, &dcr_write_mal);\n+ }\n }\ndiff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h\nindex db50cfac02..cb0bb55cec 100644\n--- a/include/hw/ppc/ppc4xx.h\n+++ b/include/hw/ppc/ppc4xx.h\n@@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,\n hwaddr *ram_sizes,\n int do_init);\n \n-void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]);\n+void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,\n+ qemu_irq irqs[4]);\n \n #define TYPE_PPC4xx_PCI_HOST_BRIDGE \"ppc4xx-pcihost\"\n \n", "prefixes": [ "PULL", "23/40" ] }