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GET /api/patches/811431/?format=api
{ "id": 811431, "url": "http://patchwork.ozlabs.org/api/patches/811431/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-4-thomas.petazzoni@free-electrons.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170908095348.16578-4-thomas.petazzoni@free-electrons.com>", "list_archive_url": null, "date": "2017-09-08T09:53:44", "name": "[3/7] PCI: aardvark: set host and device to the same MAX payload size", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6cddf1a954c91daa44b9403b1951c683a42cd442", "submitter": { "id": 2230, "url": "http://patchwork.ozlabs.org/api/people/2230/?format=api", "name": "Thomas Petazzoni", "email": "thomas.petazzoni@free-electrons.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170908095348.16578-4-thomas.petazzoni@free-electrons.com/mbox/", "series": [ { "id": 2162, "url": "http://patchwork.ozlabs.org/api/series/2162/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=2162", "date": "2017-09-08T09:53:41", "name": "PCI: aardvark: improve compatibility with PCI devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2162/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811431/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811431/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpXhr51SGz9s8J\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 19:54:04 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754141AbdIHJyC (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 8 Sep 2017 05:54:02 -0400", "from mail.free-electrons.com ([62.4.15.54]:41961 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753442AbdIHJyA (ORCPT\n\t<rfc822;linux-pci@vger.kernel.org>); Fri, 8 Sep 2017 05:54:00 -0400", "by mail.free-electrons.com (Postfix, from userid 110)\n\tid EC6F021D31; Fri, 8 Sep 2017 11:53:57 +0200 (CEST)", "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id C461720A4E;\n\tFri, 8 Sep 2017 11:53:57 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0", "From": "Thomas Petazzoni <thomas.petazzoni@free-electrons.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org", "Cc": "Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,\n\tYehuda Yitschak <yehuday@marvell.com>, Victor Gu <xigu@marvell.com>,\n\tJason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,\n\tSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement\n\t<gregory.clement@free-electrons.com>, \n\tlinux-arm-kernel@lists.infradead.org, =?utf-8?q?Miqu=C3=A8l_Raynal?=\n\t<miquel.raynal@free-electrons.com>, Antoine Tenart\n\t<antoine.tenart@free-electrons.com>, Thomas Petazzoni\n\t<thomas.petazzoni@free-electrons.com>", "Subject": "[PATCH 3/7] PCI: aardvark: set host and device to the same MAX\n\tpayload size", "Date": "Fri, 8 Sep 2017 11:53:44 +0200", "Message-Id": "<20170908095348.16578-4-thomas.petazzoni@free-electrons.com>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>", "References": "<20170908095348.16578-1-thomas.petazzoni@free-electrons.com>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "From: Victor Gu <xigu@marvell.com>\n\nSince the Aardvark does not implement a PCIe root bus, the Linux PCIe\nsubsystem will not align the MAX payload size between the host and the\ndevice. This patch ensures that the host and device have the same MAX\npayload size, fixing a number of problems with various PCIe devices.\n\nThis is part of fixing bug\nhttps://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was\nreported as the user to be important to get a Intel 7260 mini-PCIe\nWiFi card working.\n\nFixes: Fixes: 8c39d710363c1 (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Victor Gu <xigu@marvell.com>\nReviewed-by: Evan Wang <xswang@marvell.com>\nReviewed-by: Nadav Haklai <nadavh@marvell.com>\n[Thomas: tweak commit log.]\nSigned-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n---\n drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 59 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c\nindex 68ff10e17c74..e361c673732f 100644\n--- a/drivers/pci/host/pci-aardvark.c\n+++ b/drivers/pci/host/pci-aardvark.c\n@@ -30,8 +30,10 @@\n #define PCIE_CORE_DEV_CTRL_STATS_REG\t\t\t\t0xc8\n #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE\t(0 << 4)\n #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT\t5\n+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ\t\t0x2\n #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE\t\t(0 << 11)\n #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT\t12\n+#define PCIE_CORE_MPS_UNIT_BYTE\t\t\t\t128\n #define PCIE_CORE_LINK_CTRL_STAT_REG\t\t\t\t0xd0\n #define PCIE_CORE_LINK_L0S_ENTRY\t\t\t\tBIT(0)\n #define PCIE_CORE_LINK_TRAINING\t\t\t\tBIT(5)\n@@ -298,7 +300,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)\n \n \t/* Set PCIe Device Control and Status 1 PF0 register */\n \treg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |\n-\t\t(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |\n+\t\t(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<\n+\t\t PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |\n \t\tPCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |\n \t\tPCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;\n \tadvk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);\n@@ -880,6 +883,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)\n \treturn err;\n }\n \n+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)\n+{\n+\tu8 *smpss = data;\n+\n+\tif (!dev)\n+\t\treturn 0;\n+\n+\tif (!pci_is_pcie(dev))\n+\t\treturn 0;\n+\n+\tif (*smpss > dev->pcie_mpss)\n+\t\t*smpss = dev->pcie_mpss;\n+\n+\treturn 0;\n+}\n+\n+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)\n+{\n+\tint mps;\n+\n+\tif (!dev)\n+\t\treturn 0;\n+\n+\tif (!pci_is_pcie(dev))\n+\t\treturn 0;\n+\n+\tmps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;\n+\tpcie_set_mps(dev, mps);\n+\n+\treturn 0;\n+}\n+\n+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)\n+{\n+\tu8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;\n+\tu32 reg;\n+\n+\t/* Find the minimal supported MAX payload size */\n+\tadvk_pcie_find_smpss(bus->self, &smpss);\n+\tpci_walk_bus(bus, advk_pcie_find_smpss, &smpss);\n+\n+\t/* Configure RC MAX payload size */\n+\treg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);\n+\treg &= ~PCI_EXP_DEVCTL_PAYLOAD;\n+\treg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;\n+\tadvk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);\n+\n+\t/* Configure device MAX payload size */\n+\tadvk_pcie_bus_configure_mps(bus->self, &smpss);\n+\tpci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);\n+}\n+\n static int advk_pcie_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -951,6 +1006,9 @@ static int advk_pcie_probe(struct platform_device *pdev)\n \tlist_for_each_entry(child, &bus->children, node)\n \t\tpcie_bus_configure_settings(child);\n \n+\t/* Configure the MAX pay load size */\n+\tadvk_pcie_configure_mps(bus, pcie);\n+\n \tpci_bus_add_devices(bus);\n \treturn 0;\n }\n", "prefixes": [ "3/7" ] }