Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/811189/?format=api
{ "id": 811189, "url": "http://patchwork.ozlabs.org/api/patches/811189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170907221912.1804-1-jacob.e.keller@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907221912.1804-1-jacob.e.keller@intel.com>", "list_archive_url": null, "date": "2017-09-07T22:19:12", "name": "[v4] i40e/i40evf: organize and re-number feature flags", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "395b561d8d73657766d727ceb2a2f7c476275e39", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170907221912.1804-1-jacob.e.keller@intel.com/mbox/", "series": [ { "id": 2072, "url": "http://patchwork.ozlabs.org/api/series/2072/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=2072", "date": "2017-09-07T22:19:12", "name": "[v4] i40e/i40evf: organize and re-number feature flags", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/2072/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811189/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811189/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpFHJ1q3lz9sCZ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 08:19:23 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id E0EF489F41;\n\tThu, 7 Sep 2017 22:19:21 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UzZuMqSH9CyJ; Thu, 7 Sep 2017 22:19:21 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 1E31D89CA5;\n\tThu, 7 Sep 2017 22:19:21 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id AD9291C3F85\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 22:19:19 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id A701689CA5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 22:19:19 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CBtKQvTCwFMb for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 22:19:18 +0000 (UTC)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 7445D89C75\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 22:19:18 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP; 07 Sep 2017 15:19:17 -0700", "from jekeller-desk.amr.corp.intel.com ([134.134.177.230])\n\tby orsmga003.jf.intel.com with ESMTP; 07 Sep 2017 15:19:17 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,360,1500966000\"; d=\"scan'208\";\n\ta=\"1012179849\"", "From": "Jacob Keller <jacob.e.keller@intel.com>", "To": "Intel Wired LAN <intel-wired-lan@lists.osuosl.org>", "Date": "Thu, 7 Sep 2017 15:19:12 -0700", "Message-Id": "<20170907221912.1804-1-jacob.e.keller@intel.com>", "X-Mailer": "git-send-email 2.14.1.436.g33e61a4f0239", "Subject": "[Intel-wired-lan] [PATCH v4] i40e/i40evf: organize and re-number\n\tfeature flags", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Now that we've reduced the number of flags, organize similar flags\ntogether and re-number them accordingly.\n\nSince we don't yet have more than 32 flags, we'll use a u32 for both the\nhw_features and flag field. Should we gain more flags in the future, we\nmay need to convert to a u64 or separate flags out into two fields.\n\nOne alternative approach considered, but not implemented here, was to\nuse an enumeration for the flag variables, and create a macro\nI40E_FLAG() which used string concatenation to generate BIT_ULL values.\nThis has the advantage of making the actual bit values compile-time\ndynamic so that we do not need to worry about matching the order to the\nbit value. However, this does produce a high level of code churn, and\nmakes it more difficult to read a dumped flags value when debugging.\n\nv3: rebased patch based on the current dev-queue branch\n\nv4: fix bug with cmpxchg\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nReviewed-by: Mitch Williams <mitch.a.williams@intel.com>\nChange-ID: I8653fff69453cd547d6fe98d29dfa9d8710387d1\n---\n\nV2 of the patch was supposed to fix the issue with flags unnecessarily\nbeing u64, but the patch contents did not get converted properly. Fix\nthis up to use a u32, which also resolves the issue of cmpxchg.\n\n drivers/net/ethernet/intel/i40e/i40e.h | 100 ++++++++++++-------------\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 6 +-\n drivers/net/ethernet/intel/i40evf/i40evf.h | 32 ++++----\n 3 files changed, 69 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex 4dc6d43f8812..7baf6d8a84dd 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -403,57 +403,57 @@ struct i40e_pf {\n \tstruct timer_list service_timer;\n \tstruct work_struct service_task;\n \n-\tu64 hw_features;\n-#define I40E_HW_RSS_AQ_CAPABLE\t\t\tBIT_ULL(0)\n-#define I40E_HW_128_QP_RSS_CAPABLE\t\tBIT_ULL(1)\n-#define I40E_HW_ATR_EVICT_CAPABLE\t\tBIT_ULL(2)\n-#define I40E_HW_WB_ON_ITR_CAPABLE\t\tBIT_ULL(3)\n-#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE\tBIT_ULL(4)\n-#define I40E_HW_NO_PCI_LINK_CHECK\t\tBIT_ULL(5)\n-#define I40E_HW_100M_SGMII_CAPABLE\t\tBIT_ULL(6)\n-#define I40E_HW_NO_DCB_SUPPORT\t\t\tBIT_ULL(7)\n-#define I40E_HW_USE_SET_LLDP_MIB\t\tBIT_ULL(8)\n-#define I40E_HW_GENEVE_OFFLOAD_CAPABLE\t\tBIT_ULL(9)\n-#define I40E_HW_PTP_L4_CAPABLE\t\t\tBIT_ULL(10)\n-#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE\t\tBIT_ULL(11)\n-#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE\tBIT_ULL(12)\n-#define I40E_HW_HAVE_CRT_RETIMER\t\tBIT_ULL(13)\n-#define I40E_HW_OUTER_UDP_CSUM_CAPABLE\t\tBIT_ULL(14)\n-#define I40E_HW_PHY_CONTROLS_LEDS\t\tBIT_ULL(15)\n-#define I40E_HW_STOP_FW_LLDP\t\t\tBIT_ULL(16)\n-#define I40E_HW_PORT_ID_VALID\t\t\tBIT_ULL(17)\n-#define I40E_HW_RESTART_AUTONEG\t\t\tBIT_ULL(18)\n+\tu32 hw_features;\n+#define I40E_HW_RSS_AQ_CAPABLE\t\t\tBIT(0)\n+#define I40E_HW_128_QP_RSS_CAPABLE\t\tBIT(1)\n+#define I40E_HW_ATR_EVICT_CAPABLE\t\tBIT(2)\n+#define I40E_HW_WB_ON_ITR_CAPABLE\t\tBIT(3)\n+#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE\tBIT(4)\n+#define I40E_HW_NO_PCI_LINK_CHECK\t\tBIT(5)\n+#define I40E_HW_100M_SGMII_CAPABLE\t\tBIT(6)\n+#define I40E_HW_NO_DCB_SUPPORT\t\t\tBIT(7)\n+#define I40E_HW_USE_SET_LLDP_MIB\t\tBIT(8)\n+#define I40E_HW_GENEVE_OFFLOAD_CAPABLE\t\tBIT(9)\n+#define I40E_HW_PTP_L4_CAPABLE\t\t\tBIT(10)\n+#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE\t\tBIT(11)\n+#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE\tBIT(12)\n+#define I40E_HW_HAVE_CRT_RETIMER\t\tBIT(13)\n+#define I40E_HW_OUTER_UDP_CSUM_CAPABLE\t\tBIT(14)\n+#define I40E_HW_PHY_CONTROLS_LEDS\t\tBIT(15)\n+#define I40E_HW_STOP_FW_LLDP\t\t\tBIT(16)\n+#define I40E_HW_PORT_ID_VALID\t\t\tBIT(17)\n+#define I40E_HW_RESTART_AUTONEG\t\t\tBIT(18)\n \n-\tu64 flags;\n-#define I40E_FLAG_RX_CSUM_ENABLED\t\tBIT_ULL(1)\n-#define I40E_FLAG_MSI_ENABLED\t\t\tBIT_ULL(2)\n-#define I40E_FLAG_MSIX_ENABLED\t\t\tBIT_ULL(3)\n-#define I40E_FLAG_HW_ATR_EVICT_ENABLED\t\tBIT_ULL(4)\n-#define I40E_FLAG_RSS_ENABLED\t\t\tBIT_ULL(6)\n-#define I40E_FLAG_VMDQ_ENABLED\t\t\tBIT_ULL(7)\n-#define I40E_FLAG_IWARP_ENABLED\t\t\tBIT_ULL(10)\n-#define I40E_FLAG_FILTER_SYNC\t\t\tBIT_ULL(15)\n-#define I40E_FLAG_SERVICE_CLIENT_REQUESTED\tBIT_ULL(16)\n-#define I40E_FLAG_SRIOV_ENABLED\t\t\tBIT_ULL(19)\n-#define I40E_FLAG_DCB_ENABLED\t\t\tBIT_ULL(20)\n-#define I40E_FLAG_FD_SB_ENABLED\t\t\tBIT_ULL(21)\n-#define I40E_FLAG_FD_ATR_ENABLED\t\tBIT_ULL(22)\n-#define I40E_FLAG_FD_SB_AUTO_DISABLED\t\tBIT_ULL(23)\n-#define I40E_FLAG_FD_ATR_AUTO_DISABLED\t\tBIT_ULL(24)\n-#define I40E_FLAG_PTP\t\t\t\tBIT_ULL(25)\n-#define I40E_FLAG_MFP_ENABLED\t\t\tBIT_ULL(26)\n-#define I40E_FLAG_UDP_FILTER_SYNC\t\tBIT_ULL(27)\n-#define I40E_FLAG_DCB_CAPABLE\t\t\tBIT_ULL(29)\n-#define I40E_FLAG_VEB_STATS_ENABLED\t\tBIT_ULL(37)\n-#define I40E_FLAG_LINK_POLLING_ENABLED\t\tBIT_ULL(39)\n-#define I40E_FLAG_VEB_MODE_ENABLED\t\tBIT_ULL(40)\n-#define I40E_FLAG_TRUE_PROMISC_SUPPORT\t\tBIT_ULL(51)\n-#define I40E_FLAG_CLIENT_RESET\t\t\tBIT_ULL(54)\n-#define I40E_FLAG_TEMP_LINK_POLLING\t\tBIT_ULL(55)\n-#define I40E_FLAG_CLIENT_L2_CHANGE\t\tBIT_ULL(56)\n-#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED\tBIT_ULL(57)\n-#define I40E_FLAG_LEGACY_RX\t\t\tBIT_ULL(58)\n-#define I40E_FLAG_SOURCE_PRUNING_DISABLED\tBIT_ULL(59)\n+\tu32 flags;\n+#define I40E_FLAG_RX_CSUM_ENABLED\t\tBIT(0)\n+#define I40E_FLAG_MSI_ENABLED\t\t\tBIT(1)\n+#define I40E_FLAG_MSIX_ENABLED\t\t\tBIT(2)\n+#define I40E_FLAG_RSS_ENABLED\t\t\tBIT(3)\n+#define I40E_FLAG_VMDQ_ENABLED\t\t\tBIT(4)\n+#define I40E_FLAG_FILTER_SYNC\t\t\tBIT(5)\n+#define I40E_FLAG_SRIOV_ENABLED\t\t\tBIT(6)\n+#define I40E_FLAG_DCB_CAPABLE\t\t\tBIT(7)\n+#define I40E_FLAG_DCB_ENABLED\t\t\tBIT(8)\n+#define I40E_FLAG_FD_SB_ENABLED\t\t\tBIT(9)\n+#define I40E_FLAG_FD_ATR_ENABLED\t\tBIT(10)\n+#define I40E_FLAG_FD_SB_AUTO_DISABLED\t\tBIT(11)\n+#define I40E_FLAG_FD_ATR_AUTO_DISABLED\t\tBIT(12)\n+#define I40E_FLAG_MFP_ENABLED\t\t\tBIT(13)\n+#define I40E_FLAG_UDP_FILTER_SYNC\t\tBIT(14)\n+#define I40E_FLAG_HW_ATR_EVICT_ENABLED\t\tBIT(15)\n+#define I40E_FLAG_VEB_MODE_ENABLED\t\tBIT(16)\n+#define I40E_FLAG_VEB_STATS_ENABLED\t\tBIT(17)\n+#define I40E_FLAG_LINK_POLLING_ENABLED\t\tBIT(18)\n+#define I40E_FLAG_TRUE_PROMISC_SUPPORT\t\tBIT(19)\n+#define I40E_FLAG_TEMP_LINK_POLLING\t\tBIT(20)\n+#define I40E_FLAG_LEGACY_RX\t\t\tBIT(21)\n+#define I40E_FLAG_PTP\t\t\t\tBIT(22)\n+#define I40E_FLAG_IWARP_ENABLED\t\t\tBIT(23)\n+#define I40E_FLAG_SERVICE_CLIENT_REQUESTED\tBIT(24)\n+#define I40E_FLAG_CLIENT_L2_CHANGE\t\tBIT(25)\n+#define I40E_FLAG_CLIENT_RESET\t\t\tBIT(26)\n+#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED\tBIT(27)\n+#define I40E_FLAG_SOURCE_PRUNING_DISABLED\tBIT(28)\n \n \tstruct i40e_client_instance *cinst;\n \tbool stat_offsets_loaded;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 389e3903ec26..b531aa3cc2d5 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -4095,7 +4095,7 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)\n \tstruct i40e_netdev_priv *np = netdev_priv(dev);\n \tstruct i40e_vsi *vsi = np->vsi;\n \tstruct i40e_pf *pf = vsi->back;\n-\tu64 orig_flags, new_flags, changed_flags;\n+\tu32 orig_flags, new_flags, changed_flags;\n \tu32 i, j;\n \n \torig_flags = READ_ONCE(pf->flags);\n@@ -4147,12 +4147,12 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)\n \t\treturn -EOPNOTSUPP;\n \n \t/* Compare and exchange the new flags into place. If we failed, that\n-\t * is if cmpxchg64 returns anything but the old value, this means that\n+\t * is if cmpxchg returns anything but the old value, this means that\n \t * something else has modified the flags variable since we copied it\n \t * originally. We'll just punt with an error and log something in the\n \t * message buffer.\n \t */\n-\tif (cmpxchg64(&pf->flags, orig_flags, new_flags) != orig_flags) {\n+\tif (cmpxchg(&pf->flags, orig_flags, new_flags) != orig_flags) {\n \t\tdev_warn(&pf->pdev->dev,\n \t\t\t \"Unable to update pf->flags as it was modified by another thread...\\n\");\n \t\treturn -EAGAIN;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/i40evf/i40evf.h\nindex 5982362c5643..de0af521d602 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf.h\n@@ -222,22 +222,22 @@ struct i40evf_adapter {\n \n \tu32 flags;\n #define I40EVF_FLAG_RX_CSUM_ENABLED\t\tBIT(0)\n-#define I40EVF_FLAG_IMIR_ENABLED\t\tBIT(5)\n-#define I40EVF_FLAG_MQ_CAPABLE\t\t\tBIT(6)\n-#define I40EVF_FLAG_PF_COMMS_FAILED\t\tBIT(8)\n-#define I40EVF_FLAG_RESET_PENDING\t\tBIT(9)\n-#define I40EVF_FLAG_RESET_NEEDED\t\tBIT(10)\n-#define I40EVF_FLAG_WB_ON_ITR_CAPABLE\t\tBIT(11)\n-#define I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE\tBIT(12)\n-#define I40EVF_FLAG_ADDR_SET_BY_PF\t\tBIT(13)\n-#define I40EVF_FLAG_SERVICE_CLIENT_REQUESTED\tBIT(14)\n-#define I40EVF_FLAG_CLIENT_NEEDS_OPEN\t\tBIT(15)\n-#define I40EVF_FLAG_CLIENT_NEEDS_CLOSE\t\tBIT(16)\n-#define I40EVF_FLAG_CLIENT_NEEDS_L2_PARAMS\tBIT(17)\n-#define I40EVF_FLAG_PROMISC_ON\t\t\tBIT(18)\n-#define I40EVF_FLAG_ALLMULTI_ON\t\t\tBIT(19)\n-#define I40EVF_FLAG_LEGACY_RX\t\t\tBIT(20)\n-#define I40EVF_FLAG_REINIT_ITR_NEEDED\t\tBIT(21)\n+#define I40EVF_FLAG_IMIR_ENABLED\t\tBIT(1)\n+#define I40EVF_FLAG_MQ_CAPABLE\t\t\tBIT(2)\n+#define I40EVF_FLAG_PF_COMMS_FAILED\t\tBIT(3)\n+#define I40EVF_FLAG_RESET_PENDING\t\tBIT(4)\n+#define I40EVF_FLAG_RESET_NEEDED\t\tBIT(5)\n+#define I40EVF_FLAG_WB_ON_ITR_CAPABLE\t\tBIT(6)\n+#define I40EVF_FLAG_OUTER_UDP_CSUM_CAPABLE\tBIT(7)\n+#define I40EVF_FLAG_ADDR_SET_BY_PF\t\tBIT(8)\n+#define I40EVF_FLAG_SERVICE_CLIENT_REQUESTED\tBIT(9)\n+#define I40EVF_FLAG_CLIENT_NEEDS_OPEN\t\tBIT(10)\n+#define I40EVF_FLAG_CLIENT_NEEDS_CLOSE\t\tBIT(11)\n+#define I40EVF_FLAG_CLIENT_NEEDS_L2_PARAMS\tBIT(12)\n+#define I40EVF_FLAG_PROMISC_ON\t\t\tBIT(13)\n+#define I40EVF_FLAG_ALLMULTI_ON\t\t\tBIT(14)\n+#define I40EVF_FLAG_LEGACY_RX\t\t\tBIT(15)\n+#define I40EVF_FLAG_REINIT_ITR_NEEDED\t\tBIT(16)\n /* duplicates for common code */\n #define I40E_FLAG_DCB_ENABLED\t\t\t0\n #define I40E_FLAG_RX_CSUM_ENABLED\t\tI40EVF_FLAG_RX_CSUM_ENABLED\n", "prefixes": [ "v4" ] }