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{
    "id": 811181,
    "url": "http://patchwork.ozlabs.org/api/patches/811181/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/93AF473E2DA327428DE3D46B72B1E9FD41121A8E@CHN-SV-EXMX02.mchp-main.com/",
    "project": {
        "id": 7,
        "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api",
        "name": "Linux network development",
        "link_name": "netdev",
        "list_id": "netdev.vger.kernel.org",
        "list_email": "netdev@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<93AF473E2DA327428DE3D46B72B1E9FD41121A8E@CHN-SV-EXMX02.mchp-main.com>",
    "list_archive_url": null,
    "date": "2017-09-07T21:17:27",
    "name": "[RFC,4/5] Add KSZ8795 register definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "rfc",
    "archived": true,
    "hash": "d957bc83c4895aef892ece51c291c7d5ba1b4bd9",
    "submitter": {
        "id": 72262,
        "url": "http://patchwork.ozlabs.org/api/people/72262/?format=api",
        "name": "",
        "email": "Tristram.Ha@microchip.com"
    },
    "delegate": {
        "id": 34,
        "url": "http://patchwork.ozlabs.org/api/users/34/?format=api",
        "username": "davem",
        "first_name": "David",
        "last_name": "Miller",
        "email": "davem@davemloft.net"
    },
    "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/93AF473E2DA327428DE3D46B72B1E9FD41121A8E@CHN-SV-EXMX02.mchp-main.com/mbox/",
    "series": [
        {
            "id": 2066,
            "url": "http://patchwork.ozlabs.org/api/series/2066/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=2066",
            "date": "2017-09-07T21:17:33",
            "name": "[RFC,1/5] Add KSZ8795 switch driver support in Kconfig",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/2066/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/811181/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/811181/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<netdev-owner@vger.kernel.org>",
        "X-Original-To": "patchwork-incoming@ozlabs.org",
        "Delivered-To": "patchwork-incoming@ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpCxL23rcz9s3T\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri,  8 Sep 2017 07:18:46 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932503AbdIGVST convert rfc822-to-8bit (ORCPT\n\t<rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 7 Sep 2017 17:18:19 -0400",
            "from esa3.microchip.iphmx.com ([68.232.153.233]:62985 \"EHLO\n\tesa3.microchip.iphmx.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932496AbdIGVSO (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 7 Sep 2017 17:18:14 -0400",
            "from smtpout.microchip.com (HELO email.microchip.com)\n\t([198.175.253.82])\n\tby esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA;\n\t07 Sep 2017 14:17:28 -0700",
            "from CHN-SV-EXMX02.mchp-main.com ([fe80::7dfe:3761:863e:3963]) by\n\tCHN-SV-EXCH06.mchp-main.com ([fe80::5404:4dc9:559:e436%16]) with\n\tmapi id 14.03.0352.000; Thu, 7 Sep 2017 14:17:28 -0700"
        ],
        "X-IronPort-AV": "E=Sophos;i=\"5.42,360,1500966000\"; d=\"scan'208\";a=\"6868788\"",
        "From": "<Tristram.Ha@microchip.com>",
        "To": "<andrew@lunn.ch>, <muvarov@gmail.com>, <pavel@ucw.cz>,\n\t<nathan.leigh.conrad@gmail.com>,\n\t<vivien.didelot@savoirfairelinux.com>, <f.fainelli@gmail.com>,\n\t<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<Woojung.Huh@microchip.com>",
        "Subject": "[PATCH RFC 4/5] Add KSZ8795 register definitions",
        "Thread-Topic": "[PATCH RFC 4/5] Add KSZ8795 register definitions",
        "Thread-Index": "AdMoGvyzrTnL6+xfTt6chTSjW9ka7wAA2yVg",
        "Date": "Thu, 7 Sep 2017 21:17:27 +0000",
        "Message-ID": "<93AF473E2DA327428DE3D46B72B1E9FD41121A8E@CHN-SV-EXMX02.mchp-main.com>",
        "Accept-Language": "en-US",
        "Content-Language": "en-US",
        "X-MS-Has-Attach": "",
        "X-MS-TNEF-Correlator": "",
        "x-originating-ip": "[10.10.76.4]",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "8BIT",
        "MIME-Version": "1.0",
        "Sender": "netdev-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<netdev.vger.kernel.org>",
        "X-Mailing-List": "netdev@vger.kernel.org"
    },
    "content": "From: Tristram Ha <Tristram.Ha@microchip.com>\n\nAdd KSZ8795 switch support with register definitions.\n\nSigned-off-by: Tristram Ha <Tristram.Ha@microchip.com>\n---",
    "diff": "diff --git a/drivers/net/dsa/microchip/ksz8795.h b/drivers/net/dsa/microchip/ksz8795.h\nnew file mode 100644\nindex 0000000..005eda5\n--- /dev/null\n+++ b/drivers/net/dsa/microchip/ksz8795.h\n@@ -0,0 +1,1015 @@\n+/**\n+ * Microchip KSZ8795 definition file\n+ *\n+ * Copyright (c) 2017 Microchip Technology Inc.\n+ *\tTristram Ha <Tristram.Ha@microchip.com>\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#ifndef __KSZ8795_H\n+#define __KSZ8795_H\n+\n+#define KS_PORT_M\t\t\t0x1F\n+\n+#define KS_PRIO_M\t\t\t0x3\n+#define KS_PRIO_S\t\t\t2\n+\n+#define REG_CHIP_ID0\t\t\t0x00\n+\n+#define FAMILY_ID\t\t\t0x87\n+\n+#define REG_CHIP_ID1\t\t\t0x01\n+\n+#define SW_CHIP_ID_M\t\t\t0xF0\n+#define SW_CHIP_ID_S\t\t\t4\n+#define SW_REVISION_M\t\t\t0x0E\n+#define SW_REVISION_S\t\t\t1\n+#define SW_START\t\t\t0x01\n+\n+#define CHIP_ID_94\t\t\t0x60\n+#define CHIP_ID_95\t\t\t0x90\n+\n+#define REG_SW_CTRL_0\t\t\t0x02\n+\n+#define SW_NEW_BACKOFF\t\t\tBIT(7)\n+#define SW_GLOBAL_RESET\t\t\tBIT(6)\n+#define SW_FLUSH_DYN_MAC_TABLE\t\tBIT(5)\n+#define SW_FLUSH_STA_MAC_TABLE\t\tBIT(4)\n+#define SW_LINK_AUTO_AGING\t\tBIT(0)\n+\n+#define REG_SW_CTRL_1\t\t\t0x03\n+\n+#define SW_HUGE_PACKET\t\t\tBIT(6)\n+#define SW_TX_FLOW_CTRL_DISABLE\t\tBIT(5)\n+#define SW_RX_FLOW_CTRL_DISABLE\t\tBIT(4)\n+#define SW_CHECK_LENGTH\t\t\tBIT(3)\n+#define SW_AGING_ENABLE\t\t\tBIT(2)\n+#define SW_FAST_AGING\t\t\tBIT(1)\n+#define SW_AGGR_BACKOFF\t\t\tBIT(0)\n+\n+#define REG_SW_CTRL_2\t\t\t0x04\n+\n+#define UNICAST_VLAN_BOUNDARY\t\tBIT(7)\n+#define MULTICAST_STORM_DISABLE\t\tBIT(6)\n+#define SW_BACK_PRESSURE\t\tBIT(5)\n+#define FAIR_FLOW_CTRL\t\t\tBIT(4)\n+#define NO_EXC_COLLISION_DROP\t\tBIT(3)\n+#define SW_LEGAL_PACKET_DISABLE\t\tBIT(1)\n+\n+#define REG_SW_CTRL_3\t\t\t0x05\n+ #define WEIGHTED_FAIR_QUEUE_ENABLE\tBIT(3)\n+\n+#define SW_VLAN_ENABLE\t\t\tBIT(7)\n+#define SW_IGMP_SNOOP\t\t\tBIT(6)\n+#define SW_MIRROR_RX_TX\t\t\tBIT(0)\n+\n+#define REG_SW_CTRL_4\t\t\t0x06\n+\n+#define SW_HALF_DUPLEX_FLOW_CTRL\tBIT(7)\n+#define SW_HALF_DUPLEX\t\t\tBIT(6)\n+#define SW_FLOW_CTRL\t\t\tBIT(5)\n+#define SW_10_MBIT\t\t\tBIT(4)\n+#define SW_REPLACE_VID\t\t\tBIT(3)\n+#define BROADCAST_STORM_RATE_HI\t\t0x07\n+\n+#define REG_SW_CTRL_5\t\t\t0x07\n+\n+#define BROADCAST_STORM_RATE_LO\t\t0xFF\n+#define BROADCAST_STORM_RATE\t\t0x07FF\n+\n+#define REG_SW_CTRL_6\t\t\t0x08\n+\n+#define SW_MIB_COUNTER_FLUSH\t\tBIT(7)\n+#define SW_MIB_COUNTER_FREEZE\t\tBIT(6)\n+#define SW_MIB_COUNTER_CTRL_ENABLE\tKS_PORT_M\n+\n+#define REG_SW_CTRL_9\t\t\t0x0B\n+\n+#define SPI_CLK_125_MHZ\t\t\t0x80\n+#define SPI_CLK_62_5_MHZ\t\t0x40\n+#define SPI_CLK_31_25_MHZ\t\t0x00\n+\n+#define SW_LED_MODE_M\t\t\t0x3\n+#define SW_LED_MODE_S\t\t\t4\n+#define SW_LED_LINK_ACT_SPEED\t\t0\n+#define SW_LED_LINK_ACT\t\t\t1\n+#define SW_LED_LINK_ACT_DUPLEX\t\t2\n+#define SW_LED_LINK_DUPLEX\t\t3\n+\n+#define REG_SW_CTRL_10\t\t\t0x0C\n+\n+#define SW_TAIL_TAG_ENABLE\t\tBIT(1)\n+#define SW_PASS_PAUSE\t\t\tBIT(0)\n+\n+#define REG_SW_CTRL_11\t\t\t0x0D\n+\n+#define REG_POWER_MANAGEMENT_1\t\t0x0E\n+\n+#define SW_PLL_POWER_DOWN\t\tBIT(5)\n+#define SW_POWER_MANAGEMENT_MODE_M\t0x3\n+#define SW_POWER_MANAGEMENT_MODE_S\t3\n+#define SW_POWER_NORMAL\t\t\t0\n+#define SW_ENERGY_DETECTION\t\t1\n+#define SW_SOFTWARE_POWER_DOWN\t\t2\n+\n+#define REG_POWER_MANAGEMENT_2\t\t0x0F\n+\n+#define REG_PORT_1_CTRL_0\t\t0x10\n+#define REG_PORT_2_CTRL_0\t\t0x20\n+#define REG_PORT_3_CTRL_0\t\t0x30\n+#define REG_PORT_4_CTRL_0\t\t0x40\n+#define REG_PORT_5_CTRL_0\t\t0x50\n+\n+#define PORT_BROADCAST_STORM\t\tBIT(7)\n+#define PORT_DIFFSERV_ENABLE\t\tBIT(6)\n+#define PORT_802_1P_ENABLE\t\tBIT(5)\n+#define PORT_BASED_PRIO_S\t\t3\n+#define PORT_BASED_PRIO_M\t\tKS_PRIO_M\n+#define PORT_BASED_PRIO_0\t\t0\n+#define PORT_BASED_PRIO_1\t\t1\n+#define PORT_BASED_PRIO_2\t\t2\n+#define PORT_BASED_PRIO_3\t\t3\n+#define PORT_INSERT_TAG\t\t\tBIT(2)\n+#define PORT_REMOVE_TAG\t\t\tBIT(1)\n+#define PORT_QUEUE_SPLIT_L\t\tBIT(0)\n+\n+#define REG_PORT_1_CTRL_1\t\t0x11\n+#define REG_PORT_2_CTRL_1\t\t0x21\n+#define REG_PORT_3_CTRL_1\t\t0x31\n+#define REG_PORT_4_CTRL_1\t\t0x41\n+#define REG_PORT_5_CTRL_1\t\t0x51\n+\n+#define PORT_MIRROR_SNIFFER\t\tBIT(7)\n+#define PORT_MIRROR_RX\t\t\tBIT(6)\n+#define PORT_MIRROR_TX\t\t\tBIT(5)\n+#define PORT_VLAN_MEMBERSHIP\t\tKS_PORT_M\n+\n+#define REG_PORT_1_CTRL_2\t\t0x12\n+#define REG_PORT_2_CTRL_2\t\t0x22\n+#define REG_PORT_3_CTRL_2\t\t0x32\n+#define REG_PORT_4_CTRL_2\t\t0x42\n+#define REG_PORT_5_CTRL_2\t\t0x52\n+\n+#define PORT_802_1P_REMAPPING\t\tBIT(7)\n+#define PORT_INGRESS_FILTER\t\tBIT(6)\n+#define PORT_DISCARD_NON_VID\t\tBIT(5)\n+#define PORT_FORCE_FLOW_CTRL\t\tBIT(4)\n+#define PORT_BACK_PRESSURE\t\tBIT(3)\n+#define PORT_TX_ENABLE\t\t\tBIT(2)\n+#define PORT_RX_ENABLE\t\t\tBIT(1)\n+#define PORT_LEARN_DISABLE\t\tBIT(0)\n+\n+#define REG_PORT_1_CTRL_3\t\t0x13\n+#define REG_PORT_2_CTRL_3\t\t0x23\n+#define REG_PORT_3_CTRL_3\t\t0x33\n+#define REG_PORT_4_CTRL_3\t\t0x43\n+#define REG_PORT_5_CTRL_3\t\t0x53\n+#define REG_PORT_1_CTRL_4\t\t0x14\n+#define REG_PORT_2_CTRL_4\t\t0x24\n+#define REG_PORT_3_CTRL_4\t\t0x34\n+#define REG_PORT_4_CTRL_4\t\t0x44\n+#define REG_PORT_5_CTRL_4\t\t0x54\n+\n+#define PORT_DEFAULT_VID\t\t0x0001\n+\n+#define REG_PORT_1_CTRL_5\t\t0x15\n+#define REG_PORT_2_CTRL_5\t\t0x25\n+#define REG_PORT_3_CTRL_5\t\t0x35\n+#define REG_PORT_4_CTRL_5\t\t0x45\n+#define REG_PORT_5_CTRL_5\t\t0x55\n+\n+#define PORT_ACL_ENABLE\t\t\tBIT(2)\n+#define PORT_AUTHEN_MODE\t\t0x3\n+#define PORT_AUTHEN_PASS\t\t0\n+#define PORT_AUTHEN_BLOCK\t\t1\n+#define PORT_AUTHEN_TRAP\t\t2\n+\n+#define REG_PORT_5_CTRL_6\t\t0x56\n+\n+#define PORT_MII_INTERNAL_CLOCK\t\tBIT(7)\n+#define PORT_GMII_1GPS_MODE\t\tBIT(6)\n+#define PORT_RGMII_ID_IN_ENABLE\t\tBIT(4)\n+#define PORT_RGMII_ID_OUT_ENABLE\tBIT(3)\n+#define PORT_GMII_MAC_MODE\t\tBIT(2)\n+#define PORT_INTERFACE_TYPE\t\t0x3\n+#define PORT_INTERFACE_MII\t\t0\n+#define PORT_INTERFACE_RMII\t\t1\n+#define PORT_INTERFACE_GMII\t\t2\n+#define PORT_INTERFACE_RGMII\t\t3\n+\n+#define REG_PORT_1_CTRL_7\t\t0x17\n+#define REG_PORT_2_CTRL_7\t\t0x27\n+#define REG_PORT_3_CTRL_7\t\t0x37\n+#define REG_PORT_4_CTRL_7\t\t0x47\n+\n+#define PORT_AUTO_NEG_ASYM_PAUSE\tBIT(5)\n+#define PORT_AUTO_NEG_SYM_PAUSE\t\tBIT(4)\n+#define PORT_AUTO_NEG_100BTX_FD\t\tBIT(3)\n+#define PORT_AUTO_NEG_100BTX\t\tBIT(2)\n+#define PORT_AUTO_NEG_10BT_FD\t\tBIT(1)\n+#define PORT_AUTO_NEG_10BT\t\tBIT(0)\n+\n+#define REG_PORT_1_STATUS_0\t\t0x18\n+#define REG_PORT_2_STATUS_0\t\t0x28\n+#define REG_PORT_3_STATUS_0\t\t0x38\n+#define REG_PORT_4_STATUS_0\t\t0x48\n+\n+/* For KSZ8765. */\n+#define PORT_FIBER_MODE\t\t\tBIT(7)\n+\n+#define PORT_REMOTE_ASYM_PAUSE\t\tBIT(5)\n+#define PORT_REMOTE_SYM_PAUSE\t\tBIT(4)\n+#define PORT_REMOTE_100BTX_FD\t\tBIT(3)\n+#define PORT_REMOTE_100BTX\t\tBIT(2)\n+#define PORT_REMOTE_10BT_FD\t\tBIT(1)\n+#define PORT_REMOTE_10BT\t\tBIT(0)\n+\n+#define REG_PORT_1_STATUS_1\t\t0x19\n+#define REG_PORT_2_STATUS_1\t\t0x29\n+#define REG_PORT_3_STATUS_1\t\t0x39\n+#define REG_PORT_4_STATUS_1\t\t0x49\n+\n+#define PORT_HP_MDIX\t\t\tBIT(7)\n+#define PORT_REVERSED_POLARITY\t\tBIT(5)\n+#define PORT_TX_FLOW_CTRL\t\tBIT(4)\n+#define PORT_RX_FLOW_CTRL\t\tBIT(3)\n+#define PORT_STAT_SPEED_100MBIT\t\tBIT(2)\n+#define PORT_STAT_FULL_DUPLEX\t\tBIT(1)\n+\n+#define PORT_REMOTE_FAULT\t\tBIT(0)\n+\n+#define REG_PORT_1_LINK_MD_CTRL\t\t0x1A\n+#define REG_PORT_2_LINK_MD_CTRL\t\t0x2A\n+#define REG_PORT_3_LINK_MD_CTRL\t\t0x3A\n+#define REG_PORT_4_LINK_MD_CTRL\t\t0x4A\n+\n+#define PORT_CABLE_10M_SHORT\t\tBIT(7)\n+#define PORT_CABLE_DIAG_RESULT_M\t0x3\n+#define PORT_CABLE_DIAG_RESULT_S\t5\n+#define PORT_CABLE_STAT_NORMAL\t\t0\n+#define PORT_CABLE_STAT_OPEN\t\t1\n+#define PORT_CABLE_STAT_SHORT\t\t2\n+#define PORT_CABLE_STAT_FAILED\t\t3\n+#define PORT_START_CABLE_DIAG\t\tBIT(4)\n+#define PORT_FORCE_LINK\t\t\tBIT(3)\n+#define PORT_POWER_SAVING\t\tBIT(2)\n+#define PORT_PHY_REMOTE_LOOPBACK\tBIT(1)\n+#define PORT_CABLE_FAULT_COUNTER_H\t0x01\n+\n+#define REG_PORT_1_LINK_MD_RESULT\t0x1B\n+#define REG_PORT_2_LINK_MD_RESULT\t0x2B\n+#define REG_PORT_3_LINK_MD_RESULT\t0x3B\n+#define REG_PORT_4_LINK_MD_RESULT\t0x4B\n+\n+#define PORT_CABLE_FAULT_COUNTER_L\t0xFF\n+#define PORT_CABLE_FAULT_COUNTER\t0x1FF\n+\n+#define REG_PORT_1_CTRL_9\t\t0x1C\n+#define REG_PORT_2_CTRL_9\t\t0x2C\n+#define REG_PORT_3_CTRL_9\t\t0x3C\n+#define REG_PORT_4_CTRL_9\t\t0x4C\n+\n+#define PORT_AUTO_NEG_DISABLE\t\tBIT(7)\n+#define PORT_FORCE_100_MBIT\t\tBIT(6)\n+#define PORT_FORCE_FULL_DUPLEX\t\tBIT(5)\n+\n+#define REG_PORT_1_CTRL_10\t\t0x1D\n+#define REG_PORT_2_CTRL_10\t\t0x2D\n+#define REG_PORT_3_CTRL_10\t\t0x3D\n+#define REG_PORT_4_CTRL_10\t\t0x4D\n+\n+#define PORT_LED_OFF\t\t\tBIT(7)\n+#define PORT_TX_DISABLE\t\t\tBIT(6)\n+#define PORT_AUTO_NEG_RESTART\t\tBIT(5)\n+#define PORT_POWER_DOWN\t\t\tBIT(3)\n+#define PORT_AUTO_MDIX_DISABLE\t\tBIT(2)\n+#define PORT_FORCE_MDIX\t\t\tBIT(1)\n+#define PORT_MAC_LOOPBACK\t\tBIT(0)\n+\n+#define REG_PORT_1_STATUS_2\t\t0x1E\n+#define REG_PORT_2_STATUS_2\t\t0x2E\n+#define REG_PORT_3_STATUS_2\t\t0x3E\n+#define REG_PORT_4_STATUS_2\t\t0x4E\n+\n+#define PORT_MDIX_STATUS\t\tBIT(7)\n+#define PORT_AUTO_NEG_COMPLETE\t\tBIT(6)\n+#define PORT_STAT_LINK_GOOD\t\tBIT(5)\n+\n+#define REG_PORT_1_STATUS_3\t\t0x1F\n+#define REG_PORT_2_STATUS_3\t\t0x2F\n+#define REG_PORT_3_STATUS_3\t\t0x3F\n+#define REG_PORT_4_STATUS_3\t\t0x4F\n+\n+#define PORT_PHY_LOOPBACK\t\tBIT(7)\n+#define PORT_PHY_ISOLATE\t\tBIT(5)\n+#define PORT_PHY_SOFT_RESET\t\tBIT(4)\n+#define PORT_PHY_FORCE_LINK\t\tBIT(3)\n+#define PORT_PHY_MODE_M\t\t\t0x7\n+#define PHY_MODE_IN_AUTO_NEG\t\t1\n+#define PHY_MODE_10BT_HALF\t\t2\n+#define PHY_MODE_100BT_HALF\t\t3\n+#define PHY_MODE_10BT_FULL\t\t5\n+#define PHY_MODE_100BT_FULL\t\t6\n+#define PHY_MODE_ISOLDATE\t\t7\n+\n+#define REG_PORT_CTRL_0\t\t\t0x00\n+#define REG_PORT_CTRL_1\t\t\t0x01\n+#define REG_PORT_CTRL_2\t\t\t0x02\n+#define REG_PORT_CTRL_VID\t\t0x03\n+\n+#define REG_PORT_CTRL_5\t\t\t0x05\n+\n+#define REG_PORT_CTRL_7\t\t\t0x07\n+#define REG_PORT_STATUS_0\t\t0x08\n+#define REG_PORT_STATUS_1\t\t0x09\n+#define REG_PORT_LINK_MD_CTRL\t\t0x0A\n+#define REG_PORT_LINK_MD_RESULT\t\t0x0B\n+#define REG_PORT_CTRL_9\t\t\t0x0C\n+#define REG_PORT_CTRL_10\t\t0x0D\n+#define REG_PORT_STATUS_2\t\t0x0E\n+#define REG_PORT_STATUS_3\t\t0x0F\n+\n+#define REG_PORT_CTRL_12\t\t0xA0\n+#define REG_PORT_CTRL_13\t\t0xA1\n+#define REG_PORT_RATE_CTRL_3\t\t0xA2\n+#define REG_PORT_RATE_CTRL_2\t\t0xA3\n+#define REG_PORT_RATE_CTRL_1\t\t0xA4\n+#define REG_PORT_RATE_CTRL_0\t\t0xA5\n+#define REG_PORT_RATE_LIMIT\t\t0xA6\n+#define REG_PORT_IN_RATE_0\t\t0xA7\n+#define REG_PORT_IN_RATE_1\t\t0xA8\n+#define REG_PORT_IN_RATE_2\t\t0xA9\n+#define REG_PORT_IN_RATE_3\t\t0xAA\n+#define REG_PORT_OUT_RATE_0\t\t0xAB\n+#define REG_PORT_OUT_RATE_1\t\t0xAC\n+#define REG_PORT_OUT_RATE_2\t\t0xAD\n+#define REG_PORT_OUT_RATE_3\t\t0xAE\n+\n+#define PORT_CTRL_ADDR(port, addr)\t\t\\\n+\t((addr) + REG_PORT_1_CTRL_0 + (port) *\t\\\n+\t\t(REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))\n+\n+#define REG_SW_MAC_ADDR_0\t\t0x68\n+#define REG_SW_MAC_ADDR_1\t\t0x69\n+#define REG_SW_MAC_ADDR_2\t\t0x6A\n+#define REG_SW_MAC_ADDR_3\t\t0x6B\n+#define REG_SW_MAC_ADDR_4\t\t0x6C\n+#define REG_SW_MAC_ADDR_5\t\t0x6D\n+\n+#define REG_IND_CTRL_0\t\t\t0x6E\n+\n+#define TABLE_EXT_SELECT_S\t\t5\n+#define TABLE_EEE_V\t\t\t1\n+#define TABLE_ACL_V\t\t\t2\n+#define TABLE_PME_V\t\t\t4\n+#define TABLE_LINK_MD_V\t\t\t5\n+#define TABLE_EEE\t\t\t(TABLE_EEE_V << TABLE_EXT_SELECT_S)\n+#define TABLE_ACL\t\t\t(TABLE_ACL_V << TABLE_EXT_SELECT_S)\n+#define TABLE_PME\t\t\t(TABLE_PME_V << TABLE_EXT_SELECT_S)\n+#define TABLE_LINK_MD\t\t\t(TABLE_LINK_MD << TABLE_EXT_SELECT_S)\n+#define TABLE_READ\t\t\tBIT(4)\n+#define TABLE_SELECT_S\t\t\t2\n+#define TABLE_STATIC_MAC_V\t\t0\n+#define TABLE_VLAN_V\t\t\t1\n+#define TABLE_DYNAMIC_MAC_V\t\t2\n+#define TABLE_MIB_V\t\t\t3\n+#define TABLE_STATIC_MAC\t\t(TABLE_STATIC_MAC_V << TABLE_SELECT_S)\n+#define TABLE_VLAN\t\t\t(TABLE_VLAN_V << TABLE_SELECT_S)\n+#define TABLE_DYNAMIC_MAC\t\t(TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)\n+#define TABLE_MIB\t\t\t(TABLE_MIB_V << TABLE_SELECT_S)\n+\n+#define REG_IND_CTRL_1\t\t\t0x6F\n+\n+#define TABLE_ENTRY_MASK\t\t0x03FF\n+#define TABLE_EXT_ENTRY_MASK\t\t0x0FFF\n+\n+#define REG_IND_DATA_8\t\t\t0x70\n+#define REG_IND_DATA_7\t\t\t0x71\n+#define REG_IND_DATA_6\t\t\t0x72\n+#define REG_IND_DATA_5\t\t\t0x73\n+#define REG_IND_DATA_4\t\t\t0x74\n+#define REG_IND_DATA_3\t\t\t0x75\n+#define REG_IND_DATA_2\t\t\t0x76\n+#define REG_IND_DATA_1\t\t\t0x77\n+#define REG_IND_DATA_0\t\t\t0x78\n+\n+#define REG_IND_DATA_PME_EEE_ACL\t0xA0\n+\n+#define REG_IND_DATA_CHECK\t\tREG_IND_DATA_6\n+#define REG_IND_MIB_CHECK\t\tREG_IND_DATA_4\n+#define REG_IND_DATA_HI\t\t\tREG_IND_DATA_7\n+#define REG_IND_DATA_LO\t\t\tREG_IND_DATA_3\n+\n+#define REG_INT_STATUS\t\t\t0x7C\n+#define REG_INT_ENABLE\t\t\t0x7D\n+\n+#define INT_PME\t\t\t\tBIT(4)\n+\n+#define REG_ACL_INT_STATUS\t\t0x7E\n+#define REG_ACL_INT_ENABLE\t\t0x7F\n+\n+#define INT_PORT_5\t\t\tBIT(4)\n+#define INT_PORT_4\t\t\tBIT(3)\n+#define INT_PORT_3\t\t\tBIT(2)\n+#define INT_PORT_2\t\t\tBIT(1)\n+#define INT_PORT_1\t\t\tBIT(0)\n+\n+#define INT_PORT_ALL\t\t\t\\\n+\t(INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)\n+\n+#define REG_SW_CTRL_12\t\t\t0x80\n+#define REG_SW_CTRL_13\t\t\t0x81\n+\n+#define SWITCH_802_1P_MASK\t\t3\n+#define SWITCH_802_1P_BASE\t\t3\n+#define SWITCH_802_1P_SHIFT\t\t2\n+\n+#define SW_802_1P_MAP_M\t\t\tKS_PRIO_M\n+#define SW_802_1P_MAP_S\t\t\tKS_PRIO_S\n+\n+#define REG_SWITCH_CTRL_14\t\t0x82\n+\n+#define SW_PRIO_MAPPING_M\t\tKS_PRIO_M\n+#define SW_PRIO_MAPPING_S\t\t6\n+#define SW_PRIO_MAP_3_HI\t\t0\n+#define SW_PRIO_MAP_2_HI\t\t2\n+#define SW_PRIO_MAP_0_LO\t\t3\n+\n+#define REG_SW_CTRL_15\t\t\t0x83\n+#define REG_SW_CTRL_16\t\t\t0x84\n+#define REG_SW_CTRL_17\t\t\t0x85\n+#define REG_SW_CTRL_18\t\t\t0x86\n+\n+#define SW_SELF_ADDR_FILTER_ENABLE\tBIT(6)\n+\n+#define REG_SW_UNK_UCAST_CTRL\t\t0x83\n+#define REG_SW_UNK_MCAST_CTRL\t\t0x84\n+#define REG_SW_UNK_VID_CTRL\t\t0x85\n+#define REG_SW_UNK_IP_MCAST_CTRL\t0x86\n+\n+#define SW_UNK_FWD_ENABLE\t\tBIT(5)\n+#define SW_UNK_FWD_MAP\t\t\tKS_PORT_M\n+\n+#define REG_SW_CTRL_19\t\t\t0x87\n+\n+#define SW_IN_RATE_LIMIT_PERIOD_M\t0x3\n+#define SW_IN_RATE_LIMIT_PERIOD_S\t4\n+#define SW_IN_RATE_LIMIT_16_MS\t\t0\n+#define SW_IN_RATE_LIMIT_64_MS\t\t1\n+#define SW_IN_RATE_LIMIT_256_MS\t\t2\n+#define SW_OUT_RATE_LIMIT_QUEUE_BASED\tBIT(3)\n+#define SW_INS_TAG_ENABLE\t\tBIT(2)\n+\n+#define REG_TOS_PRIO_CTRL_0\t\t0x90\n+#define REG_TOS_PRIO_CTRL_1\t\t0x91\n+#define REG_TOS_PRIO_CTRL_2\t\t0x92\n+#define REG_TOS_PRIO_CTRL_3\t\t0x93\n+#define REG_TOS_PRIO_CTRL_4\t\t0x94\n+#define REG_TOS_PRIO_CTRL_5\t\t0x95\n+#define REG_TOS_PRIO_CTRL_6\t\t0x96\n+#define REG_TOS_PRIO_CTRL_7\t\t0x97\n+#define REG_TOS_PRIO_CTRL_8\t\t0x98\n+#define REG_TOS_PRIO_CTRL_9\t\t0x99\n+#define REG_TOS_PRIO_CTRL_10\t\t0x9A\n+#define REG_TOS_PRIO_CTRL_11\t\t0x9B\n+#define REG_TOS_PRIO_CTRL_12\t\t0x9C\n+#define REG_TOS_PRIO_CTRL_13\t\t0x9D\n+#define REG_TOS_PRIO_CTRL_14\t\t0x9E\n+#define REG_TOS_PRIO_CTRL_15\t\t0x9F\n+\n+#define TOS_PRIO_M\t\t\tKS_PRIO_M\n+#define TOS_PRIO_S\t\t\tKS_PRIO_S\n+\n+#define REG_SW_CTRL_20\t\t\t0xA3\n+\n+#define SW_GMII_DRIVE_STRENGTH_S\t4\n+#define SW_DRIVE_STRENGTH_M\t\t0x7\n+#define SW_DRIVE_STRENGTH_2MA\t\t0\n+#define SW_DRIVE_STRENGTH_4MA\t\t1\n+#define SW_DRIVE_STRENGTH_8MA\t\t2\n+#define SW_DRIVE_STRENGTH_12MA\t\t3\n+#define SW_DRIVE_STRENGTH_16MA\t\t4\n+#define SW_DRIVE_STRENGTH_20MA\t\t5\n+#define SW_DRIVE_STRENGTH_24MA\t\t6\n+#define SW_DRIVE_STRENGTH_28MA\t\t7\n+#define SW_MII_DRIVE_STRENGTH_S\t\t0\n+\n+#define REG_SW_CTRL_21\t\t\t0xA4\n+\n+#define SW_IPV6_MLD_OPTION\t\tBIT(3)\n+#define SW_IPV6_MLD_SNOOP\t\tBIT(2)\n+\n+#define REG_PORT_1_CTRL_12\t\t0xB0\n+#define REG_PORT_2_CTRL_12\t\t0xC0\n+#define REG_PORT_3_CTRL_12\t\t0xD0\n+#define REG_PORT_4_CTRL_12\t\t0xE0\n+#define REG_PORT_5_CTRL_12\t\t0xF0\n+\n+#define PORT_PASS_ALL\t\t\tBIT(6)\n+#define PORT_INS_TAG_FOR_PORT_5_S\t3\n+#define PORT_INS_TAG_FOR_PORT_5\t\tBIT(3)\n+#define PORT_INS_TAG_FOR_PORT_4\t\tBIT(2)\n+#define PORT_INS_TAG_FOR_PORT_3\t\tBIT(1)\n+#define PORT_INS_TAG_FOR_PORT_2\t\tBIT(0)\n+\n+#define REG_PORT_1_CTRL_13\t\t0xB1\n+#define REG_PORT_2_CTRL_13\t\t0xC1\n+#define REG_PORT_3_CTRL_13\t\t0xD1\n+#define REG_PORT_4_CTRL_13\t\t0xE1\n+#define REG_PORT_5_CTRL_13\t\t0xF1\n+\n+#define PORT_QUEUE_SPLIT_H\t\tBIT(1)\n+#define PORT_QUEUE_SPLIT_1\t\t0\n+#define PORT_QUEUE_SPLIT_2\t\t1\n+#define PORT_QUEUE_SPLIT_4\t\t2\n+#define PORT_DROP_TAG\t\t\tBIT(0)\n+\n+#define REG_PORT_1_CTRL_14\t\t0xB2\n+#define REG_PORT_2_CTRL_14\t\t0xC2\n+#define REG_PORT_3_CTRL_14\t\t0xD2\n+#define REG_PORT_4_CTRL_14\t\t0xE2\n+#define REG_PORT_5_CTRL_14\t\t0xF2\n+#define REG_PORT_1_CTRL_15\t\t0xB3\n+#define REG_PORT_2_CTRL_15\t\t0xC3\n+#define REG_PORT_3_CTRL_15\t\t0xD3\n+#define REG_PORT_4_CTRL_15\t\t0xE3\n+#define REG_PORT_5_CTRL_15\t\t0xF3\n+#define REG_PORT_1_CTRL_16\t\t0xB4\n+#define REG_PORT_2_CTRL_16\t\t0xC4\n+#define REG_PORT_3_CTRL_16\t\t0xD4\n+#define REG_PORT_4_CTRL_16\t\t0xE4\n+#define REG_PORT_5_CTRL_16\t\t0xF4\n+#define REG_PORT_1_CTRL_17\t\t0xB5\n+#define REG_PORT_2_CTRL_17\t\t0xC5\n+#define REG_PORT_3_CTRL_17\t\t0xD5\n+#define REG_PORT_4_CTRL_17\t\t0xE5\n+#define REG_PORT_5_CTRL_17\t\t0xF5\n+\n+#define REG_PORT_1_RATE_CTRL_3\t\t0xB2\n+#define REG_PORT_1_RATE_CTRL_2\t\t0xB3\n+#define REG_PORT_1_RATE_CTRL_1\t\t0xB4\n+#define REG_PORT_1_RATE_CTRL_0\t\t0xB5\n+#define REG_PORT_2_RATE_CTRL_3\t\t0xC2\n+#define REG_PORT_2_RATE_CTRL_2\t\t0xC3\n+#define REG_PORT_2_RATE_CTRL_1\t\t0xC4\n+#define REG_PORT_2_RATE_CTRL_0\t\t0xC5\n+#define REG_PORT_3_RATE_CTRL_3\t\t0xD2\n+#define REG_PORT_3_RATE_CTRL_2\t\t0xD3\n+#define REG_PORT_3_RATE_CTRL_1\t\t0xD4\n+#define REG_PORT_3_RATE_CTRL_0\t\t0xD5\n+#define REG_PORT_4_RATE_CTRL_3\t\t0xE2\n+#define REG_PORT_4_RATE_CTRL_2\t\t0xE3\n+#define REG_PORT_4_RATE_CTRL_1\t\t0xE4\n+#define REG_PORT_4_RATE_CTRL_0\t\t0xE5\n+#define REG_PORT_5_RATE_CTRL_3\t\t0xF2\n+#define REG_PORT_5_RATE_CTRL_2\t\t0xF3\n+#define REG_PORT_5_RATE_CTRL_1\t\t0xF4\n+#define REG_PORT_5_RATE_CTRL_0\t\t0xF5\n+\n+#define RATE_CTRL_ENABLE\t\tBIT(7)\n+#define RATE_RATIO_M\t\t\t(BIT(7) - 1)\n+\n+#define PORT_OUT_RATE_ENABLE\t\tBIT(7)\n+\n+#define REG_PORT_1_RATE_LIMIT\t\t0xB6\n+#define REG_PORT_2_RATE_LIMIT\t\t0xC6\n+#define REG_PORT_3_RATE_LIMIT\t\t0xD6\n+#define REG_PORT_4_RATE_LIMIT\t\t0xE6\n+#define REG_PORT_5_RATE_LIMIT\t\t0xF6\n+\n+#define PORT_IN_PORT_BASED_S\t\t6\n+#define PORT_RATE_PACKET_BASED_S\t5\n+#define PORT_IN_FLOW_CTRL_S\t\t4\n+#define PORT_IN_LIMIT_MODE_M\t\t0x3\n+#define PORT_IN_LIMIT_MODE_S\t\t2\n+#define PORT_COUNT_IFG_S\t\t1\n+#define PORT_COUNT_PREAMBLE_S\t\t0\n+#define PORT_IN_PORT_BASED\t\tBIT(PORT_IN_PORT_BASED_S)\n+#define PORT_RATE_PACKET_BASED\t\tBIT(PORT_RATE_PACKET_BASED_S)\n+#define PORT_IN_FLOW_CTRL\t\tBIT(PORT_IN_FLOW_CTRL_S)\n+#define PORT_IN_ALL\t\t\t0\n+#define PORT_IN_UNICAST\t\t\t1\n+#define PORT_IN_MULTICAST\t\t2\n+#define PORT_IN_BROADCAST\t\t3\n+#define PORT_COUNT_IFG\t\t\tBIT(PORT_COUNT_IFG_S)\n+#define PORT_COUNT_PREAMBLE\t\tBIT(PORT_COUNT_PREAMBLE_S)\n+\n+#define REG_PORT_1_IN_RATE_0\t\t0xB7\n+#define REG_PORT_2_IN_RATE_0\t\t0xC7\n+#define REG_PORT_3_IN_RATE_0\t\t0xD7\n+#define REG_PORT_4_IN_RATE_0\t\t0xE7\n+#define REG_PORT_5_IN_RATE_0\t\t0xF7\n+#define REG_PORT_1_IN_RATE_1\t\t0xB8\n+#define REG_PORT_2_IN_RATE_1\t\t0xC8\n+#define REG_PORT_3_IN_RATE_1\t\t0xD8\n+#define REG_PORT_4_IN_RATE_1\t\t0xE8\n+#define REG_PORT_5_IN_RATE_1\t\t0xF8\n+#define REG_PORT_1_IN_RATE_2\t\t0xB9\n+#define REG_PORT_2_IN_RATE_2\t\t0xC9\n+#define REG_PORT_3_IN_RATE_2\t\t0xD9\n+#define REG_PORT_4_IN_RATE_2\t\t0xE9\n+#define REG_PORT_5_IN_RATE_2\t\t0xF9\n+#define REG_PORT_1_IN_RATE_3\t\t0xBA\n+#define REG_PORT_2_IN_RATE_3\t\t0xCA\n+#define REG_PORT_3_IN_RATE_3\t\t0xDA\n+#define REG_PORT_4_IN_RATE_3\t\t0xEA\n+#define REG_PORT_5_IN_RATE_3\t\t0xFA\n+\n+#define PORT_IN_RATE_ENABLE\t\tBIT(7)\n+#define PORT_RATE_LIMIT_M\t\t(BIT(7) - 1)\n+\n+#define REG_PORT_1_OUT_RATE_0\t\t0xBB\n+#define REG_PORT_2_OUT_RATE_0\t\t0xCB\n+#define REG_PORT_3_OUT_RATE_0\t\t0xDB\n+#define REG_PORT_4_OUT_RATE_0\t\t0xEB\n+#define REG_PORT_5_OUT_RATE_0\t\t0xFB\n+#define REG_PORT_1_OUT_RATE_1\t\t0xBC\n+#define REG_PORT_2_OUT_RATE_1\t\t0xCC\n+#define REG_PORT_3_OUT_RATE_1\t\t0xDC\n+#define REG_PORT_4_OUT_RATE_1\t\t0xEC\n+#define REG_PORT_5_OUT_RATE_1\t\t0xFC\n+#define REG_PORT_1_OUT_RATE_2\t\t0xBD\n+#define REG_PORT_2_OUT_RATE_2\t\t0xCD\n+#define REG_PORT_3_OUT_RATE_2\t\t0xDD\n+#define REG_PORT_4_OUT_RATE_2\t\t0xED\n+#define REG_PORT_5_OUT_RATE_2\t\t0xFD\n+#define REG_PORT_1_OUT_RATE_3\t\t0xBE\n+#define REG_PORT_2_OUT_RATE_3\t\t0xCE\n+#define REG_PORT_3_OUT_RATE_3\t\t0xDE\n+#define REG_PORT_4_OUT_RATE_3\t\t0xEE\n+#define REG_PORT_5_OUT_RATE_3\t\t0xFE\n+\n+/* PME */\n+\n+#define SW_PME_OUTPUT_ENABLE\t\tBIT(1)\n+#define SW_PME_ACTIVE_HIGH\t\tBIT(0)\n+\n+#define PORT_MAGIC_PACKET_DETECT\tBIT(2)\n+#define PORT_LINK_UP_DETECT\t\tBIT(1)\n+#define PORT_ENERGY_DETECT\t\tBIT(0)\n+\n+/* ACL */\n+\n+#define ACL_FIRST_RULE_M\t\t0xF\n+\n+#define ACL_MODE_M\t\t\t0x3\n+#define ACL_MODE_S\t\t\t4\n+#define ACL_MODE_DISABLE\t\t0\n+#define ACL_MODE_LAYER_2\t\t1\n+#define ACL_MODE_LAYER_3\t\t2\n+#define ACL_MODE_LAYER_4\t\t3\n+#define ACL_ENABLE_M\t\t\t0x3\n+#define ACL_ENABLE_S\t\t\t2\n+#define ACL_ENABLE_2_COUNT\t\t0\n+#define ACL_ENABLE_2_TYPE\t\t1\n+#define ACL_ENABLE_2_MAC\t\t2\n+#define ACL_ENABLE_2_BOTH\t\t3\n+#define ACL_ENABLE_3_IP\t\t\t1\n+#define ACL_ENABLE_3_SRC_DST_COMP\t2\n+#define ACL_ENABLE_4_PROTOCOL\t\t0\n+#define ACL_ENABLE_4_TCP_PORT_COMP\t1\n+#define ACL_ENABLE_4_UDP_PORT_COMP\t2\n+#define ACL_ENABLE_4_TCP_SEQN_COMP\t3\n+#define ACL_SRC\t\t\t\tBIT(1)\n+#define ACL_EQUAL\t\t\tBIT(0)\n+\n+#define ACL_MAX_PORT\t\t\t0xFFFF\n+\n+#define ACL_MIN_PORT\t\t\t0xFFFF\n+#define ACL_IP_ADDR\t\t\t0xFFFFFFFF\n+#define ACL_TCP_SEQNUM\t\t\t0xFFFFFFFF\n+\n+#define ACL_RESERVED\t\t\t0xF8\n+#define ACL_PORT_MODE_M\t\t\t0x3\n+#define ACL_PORT_MODE_S\t\t\t1\n+#define ACL_PORT_MODE_DISABLE\t\t0\n+#define ACL_PORT_MODE_EITHER\t\t1\n+#define ACL_PORT_MODE_IN_RANGE\t\t2\n+#define ACL_PORT_MODE_OUT_OF_RANGE\t3\n+\n+#define ACL_TCP_FLAG_ENABLE\t\tBIT(0)\n+\n+#define ACL_TCP_FLAG_M\t\t\t0xFF\n+\n+#define ACL_TCP_FLAG\t\t\t0xFF\n+#define ACL_ETH_TYPE\t\t\t0xFFFF\n+#define ACL_IP_M\t\t\t0xFFFFFFFF\n+\n+#define ACL_PRIO_MODE_M\t\t\t0x3\n+#define ACL_PRIO_MODE_S\t\t\t6\n+#define ACL_PRIO_MODE_DISABLE\t\t0\n+#define ACL_PRIO_MODE_HIGHER\t\t1\n+#define ACL_PRIO_MODE_LOWER\t\t2\n+#define ACL_PRIO_MODE_REPLACE\t\t3\n+#define ACL_PRIO_M\t\t\t0x7\n+#define ACL_PRIO_S\t\t\t3\n+#define ACL_VLAN_PRIO_REPLACE\t\tBIT(2)\n+#define ACL_VLAN_PRIO_M\t\t\t0x7\n+#define ACL_VLAN_PRIO_HI_M\t\t0x3\n+\n+#define ACL_VLAN_PRIO_LO_M\t\t0x8\n+#define ACL_VLAN_PRIO_S\t\t\t7\n+#define ACL_MAP_MODE_M\t\t\t0x3\n+#define ACL_MAP_MODE_S\t\t\t5\n+#define ACL_MAP_MODE_DISABLE\t\t0\n+#define ACL_MAP_MODE_OR\t\t\t1\n+#define ACL_MAP_MODE_AND\t\t2\n+#define ACL_MAP_MODE_REPLACE\t\t3\n+#define ACL_MAP_PORT_M\t\t\t0x1F\n+\n+#define ACL_CNT_M\t\t\t(BIT(11) - 1)\n+#define ACL_CNT_S\t\t\t5\n+#define ACL_MSEC_UNIT\t\t\tBIT(4)\n+#define ACL_INTR_MODE\t\t\tBIT(3)\n+\n+#define REG_PORT_ACL_BYTE_EN_MSB\t0x10\n+\n+#define ACL_BYTE_EN_MSB_M\t\t0x3F\n+\n+#define REG_PORT_ACL_BYTE_EN_LSB\t0x11\n+\n+#define ACL_ACTION_START\t\t0xA\n+#define ACL_ACTION_LEN\t\t\t2\n+#define ACL_INTR_CNT_START\t\t0xB\n+#define ACL_RULESET_START\t\t0xC\n+#define ACL_RULESET_LEN\t\t\t2\n+#define ACL_TABLE_LEN\t\t\t14\n+\n+#define ACL_ACTION_ENABLE\t\t0x000C\n+#define ACL_MATCH_ENABLE\t\t0x1FF0\n+#define ACL_RULESET_ENABLE\t\t0x2003\n+#define ACL_BYTE_ENABLE\t\t\t((ACL_BYTE_EN_MSB_M << 8) | 0xFF)\n+#define ACL_MODE_ENABLE\t\t\t(0x10 << 8)\n+\n+#define REG_PORT_ACL_CTRL_0\t\t0x12\n+\n+#define PORT_ACL_WRITE_DONE\t\tBIT(6)\n+#define PORT_ACL_READ_DONE\t\tBIT(5)\n+#define PORT_ACL_WRITE\t\t\tBIT(4)\n+#define PORT_ACL_INDEX_M\t\t0xF\n+\n+#define REG_PORT_ACL_CTRL_1\t\t0x13\n+\n+#define PORT_ACL_FORCE_DLR_MISS\t\tBIT(0)\n+\n+#ifndef PHY_REG_CTRL\n+#define PHY_REG_CTRL\t\t\t0\n+\n+#define PHY_RESET\t\t\tBIT(15)\n+#define PHY_LOOPBACK\t\t\tBIT(14)\n+#define PHY_SPEED_100MBIT\t\tBIT(13)\n+#define PHY_AUTO_NEG_ENABLE\t\tBIT(12)\n+#define PHY_POWER_DOWN\t\t\tBIT(11)\n+#define PHY_MII_DISABLE\t\t\tBIT(10)\n+#define PHY_AUTO_NEG_RESTART\t\tBIT(9)\n+#define PHY_FULL_DUPLEX\t\t\tBIT(8)\n+#define PHY_COLLISION_TEST_NOT\t\tBIT(7)\n+#define PHY_HP_MDIX\t\t\tBIT(5)\n+#define PHY_FORCE_MDIX\t\t\tBIT(4)\n+#define PHY_AUTO_MDIX_DISABLE\t\tBIT(3)\n+#define PHY_REMOTE_FAULT_DISABLE\tBIT(2)\n+#define PHY_TRANSMIT_DISABLE\t\tBIT(1)\n+#define PHY_LED_DISABLE\t\t\tBIT(0)\n+\n+#define PHY_REG_STATUS\t\t\t1\n+\n+#define PHY_100BT4_CAPABLE\t\tBIT(15)\n+#define PHY_100BTX_FD_CAPABLE\t\tBIT(14)\n+#define PHY_100BTX_CAPABLE\t\tBIT(13)\n+#define PHY_10BT_FD_CAPABLE\t\tBIT(12)\n+#define PHY_10BT_CAPABLE\t\tBIT(11)\n+#define PHY_MII_SUPPRESS_CAPABLE_NOT\tBIT(6)\n+#define PHY_AUTO_NEG_ACKNOWLEDGE\tBIT(5)\n+#define PHY_REMOTE_FAULT\t\tBIT(4)\n+#define PHY_AUTO_NEG_CAPABLE\t\tBIT(3)\n+#define PHY_LINK_STATUS\t\t\tBIT(2)\n+#define PHY_JABBER_DETECT_NOT\t\tBIT(1)\n+#define PHY_EXTENDED_CAPABILITY\t\tBIT(0)\n+\n+#define PHY_REG_ID_1\t\t\t2\n+#define PHY_REG_ID_2\t\t\t3\n+\n+#define PHY_REG_AUTO_NEGOTIATION\t4\n+\n+#define PHY_AUTO_NEG_NEXT_PAGE_NOT\tBIT(15)\n+#define PHY_AUTO_NEG_REMOTE_FAULT_NOT\tBIT(13)\n+#define PHY_AUTO_NEG_SYM_PAUSE\t\tBIT(10)\n+#define PHY_AUTO_NEG_100BT4\t\tBIT(9)\n+#define PHY_AUTO_NEG_100BTX_FD\t\tBIT(8)\n+#define PHY_AUTO_NEG_100BTX\t\tBIT(7)\n+#define PHY_AUTO_NEG_10BT_FD\t\tBIT(6)\n+#define PHY_AUTO_NEG_10BT\t\tBIT(5)\n+#define PHY_AUTO_NEG_SELECTOR\t\t0x001F\n+#define PHY_AUTO_NEG_802_3\t\t0x0001\n+\n+#define PHY_REG_REMOTE_CAPABILITY\t5\n+\n+#define PHY_REMOTE_NEXT_PAGE_NOT\tBIT(15)\n+#define PHY_REMOTE_ACKNOWLEDGE_NOT\tBIT(14)\n+#define PHY_REMOTE_REMOTE_FAULT_NOT\tBIT(13)\n+#define PHY_REMOTE_SYM_PAUSE\t\tBIT(10)\n+#define PHY_REMOTE_100BTX_FD\t\tBIT(8)\n+#define PHY_REMOTE_100BTX\t\tBIT(7)\n+#define PHY_REMOTE_10BT_FD\t\tBIT(6)\n+#define PHY_REMOTE_10BT\t\t\tBIT(5)\n+#endif\n+\n+#define KSZ8795_ID_HI\t\t\t0x0022\n+#define KSZ8795_ID_LO\t\t\t0x1550\n+\n+#define KSZ8795_SW_ID\t\t\t0x8795\n+\n+#define PHY_REG_LINK_MD\t\t\t0x1D\n+\n+#define PHY_START_CABLE_DIAG\t\tBIT(15)\n+#define PHY_CABLE_DIAG_RESULT\t\t0x6000\n+#define PHY_CABLE_STAT_NORMAL\t\t0x0000\n+#define PHY_CABLE_STAT_OPEN\t\t0x2000\n+#define PHY_CABLE_STAT_SHORT\t\t0x4000\n+#define PHY_CABLE_STAT_FAILED\t\t0x6000\n+#define PHY_CABLE_10M_SHORT\t\tBIT(12)\n+#define PHY_CABLE_FAULT_COUNTER\t\t0x01FF\n+\n+#define PHY_REG_PHY_CTRL\t\t0x1F\n+\n+#define PHY_MODE_M\t\t\t0x7\n+#define PHY_MODE_S\t\t\t8\n+#define PHY_STAT_REVERSED_POLARITY\tBIT(5)\n+#define PHY_STAT_MDIX\t\t\tBIT(4)\n+#define PHY_FORCE_LINK\t\t\tBIT(3)\n+#define PHY_POWER_SAVING_ENABLE\t\tBIT(2)\n+#define PHY_REMOTE_LOOPBACK\t\tBIT(1)\n+\n+/* Chip resource */\n+\n+#define PRIO_QUEUES\t\t\t4\n+\n+#define KS_PRIO_IN_REG\t\t\t4\n+\n+#define TOTAL_PORT_NUM\t\t\t5\n+\n+/* Host port can only be last of them. */\n+#define SWITCH_PORT_NUM\t\t\t(TOTAL_PORT_NUM - 1)\n+\n+#define KSZ8795_COUNTER_NUM\t\t0x20\n+#define TOTAL_KSZ8795_COUNTER_NUM\t(KSZ8795_COUNTER_NUM + 4)\n+\n+#define SWITCH_COUNTER_NUM\t\tKSZ8795_COUNTER_NUM\n+#define TOTAL_SWITCH_COUNTER_NUM\tTOTAL_KSZ8795_COUNTER_NUM\n+\n+/* Common names used by other drivers */\n+\n+#define P_BCAST_STORM_CTRL\t\tREG_PORT_CTRL_0\n+#define P_PRIO_CTRL\t\t\tREG_PORT_CTRL_0\n+#define P_TAG_CTRL\t\t\tREG_PORT_CTRL_0\n+#define P_MIRROR_CTRL\t\t\tREG_PORT_CTRL_1\n+#define P_802_1P_CTRL\t\t\tREG_PORT_CTRL_2\n+#define P_STP_CTRL\t\t\tREG_PORT_CTRL_2\n+#define P_LOCAL_CTRL\t\t\tREG_PORT_CTRL_7\n+#define P_REMOTE_STATUS\t\t\tREG_PORT_STATUS_0\n+#define P_FORCE_CTRL\t\t\tREG_PORT_CTRL_9\n+#define P_NEG_RESTART_CTRL\t\tREG_PORT_CTRL_10\n+#define P_SPEED_STATUS\t\t\tREG_PORT_STATUS_1\n+#define P_LINK_STATUS\t\t\tREG_PORT_STATUS_2\n+#define P_PASS_ALL_CTRL\t\t\tREG_PORT_CTRL_12\n+#define P_INS_SRC_PVID_CTRL\t\tREG_PORT_CTRL_12\n+#define P_DROP_TAG_CTRL\t\t\tREG_PORT_CTRL_13\n+#define P_RATE_LIMIT_CTRL\t\tREG_PORT_RATE_LIMIT\n+\n+#define S_UNKNOWN_DA_CTRL\t\tREG_SWITCH_CTRL_12\n+#define S_FORWARD_INVALID_VID_CTRL\tREG_FORWARD_INVALID_VID\n+\n+#define S_FLUSH_TABLE_CTRL\t\tREG_SW_CTRL_0\n+#define S_LINK_AGING_CTRL\t\tREG_SW_CTRL_0\n+#define S_HUGE_PACKET_CTRL\t\tREG_SW_CTRL_1\n+#define S_MIRROR_CTRL\t\t\tREG_SW_CTRL_3\n+#define S_REPLACE_VID_CTRL\t\tREG_SW_CTRL_4\n+#define S_PASS_PAUSE_CTRL\t\tREG_SW_CTRL_10\n+#define S_TAIL_TAG_CTRL\t\t\tREG_SW_CTRL_10\n+#define S_802_1P_PRIO_CTRL\t\tREG_SW_CTRL_12\n+#define S_TOS_PRIO_CTRL\t\t\tREG_TOS_PRIO_CTRL_0\n+#define S_IPV6_MLD_CTRL\t\t\tREG_SW_CTRL_21\n+\n+#define IND_ACC_TABLE(table)\t\t((table) << 8)\n+\n+/* Driver set switch broadcast storm protection at 10% rate. */\n+#define BROADCAST_STORM_PROT_RATE\t10\n+\n+/* 148,800 frames * 67 ms / 100 */\n+#define BROADCAST_STORM_VALUE\t\t9969\n+\n+/**\n+ * STATIC_MAC_TABLE_ADDR\t\t00-0000FFFF-FFFFFFFF\n+ * STATIC_MAC_TABLE_FWD_PORTS\t\t00-001F0000-00000000\n+ * STATIC_MAC_TABLE_VALID\t\t00-00200000-00000000\n+ * STATIC_MAC_TABLE_OVERRIDE\t\t00-00400000-00000000\n+ * STATIC_MAC_TABLE_USE_FID\t\t00-00800000-00000000\n+ * STATIC_MAC_TABLE_FID\t\t\t00-7F000000-00000000\n+ */\n+\n+#define STATIC_MAC_TABLE_ADDR\t\t0x0000FFFF\n+#define STATIC_MAC_TABLE_FWD_PORTS\t0x001F0000\n+#define STATIC_MAC_TABLE_VALID\t\t0x00200000\n+#define STATIC_MAC_TABLE_OVERRIDE\t0x00400000\n+#define STATIC_MAC_TABLE_USE_FID\t0x00800000\n+#define STATIC_MAC_TABLE_FID\t\t0x7F000000\n+\n+#define STATIC_MAC_FWD_PORTS_S\t\t16\n+#define STATIC_MAC_FID_S\t\t24\n+\n+/**\n+ * VLAN_TABLE_FID\t\t\t00-007F007F-007F007F\n+ * VLAN_TABLE_MEMBERSHIP\t\t00-0F800F80-0F800F80\n+ * VLAN_TABLE_VALID\t\t\t00-10001000-10001000\n+ */\n+\n+#define VLAN_TABLE_FID\t\t\t0x007F\n+#define VLAN_TABLE_MEMBERSHIP\t\t0x0F80\n+#define VLAN_TABLE_VALID\t\t0x1000\n+\n+#define VLAN_TABLE_MEMBERSHIP_S\t\t7\n+#define VLAN_TABLE_S\t\t\t16\n+\n+/**\n+ * DYNAMIC_MAC_TABLE_ADDR\t\t00-0000FFFF-FFFFFFFF\n+ * DYNAMIC_MAC_TABLE_FID\t\t00-007F0000-00000000\n+ * DYNAMIC_MAC_TABLE_NOT_READY\t\t00-00800000-00000000\n+ * DYNAMIC_MAC_TABLE_SRC_PORT\t\t00-07000000-00000000\n+ * DYNAMIC_MAC_TABLE_TIMESTAMP\t\t00-18000000-00000000\n+ * DYNAMIC_MAC_TABLE_ENTRIES\t\t7F-E0000000-00000000\n+ * DYNAMIC_MAC_TABLE_MAC_EMPTY\t\t80-00000000-00000000\n+ */\n+\n+#define DYNAMIC_MAC_TABLE_ADDR\t\t0x0000FFFF\n+#define DYNAMIC_MAC_TABLE_FID\t\t0x007F0000\n+#define DYNAMIC_MAC_TABLE_SRC_PORT\t0x07000000\n+#define DYNAMIC_MAC_TABLE_TIMESTAMP\t0x18000000\n+#define DYNAMIC_MAC_TABLE_ENTRIES\t0xE0000000\n+\n+#define DYNAMIC_MAC_TABLE_NOT_READY\t0x80\n+\n+#define DYNAMIC_MAC_TABLE_ENTRIES_H\t0x7F\n+#define DYNAMIC_MAC_TABLE_MAC_EMPTY\t0x80\n+\n+#define DYNAMIC_MAC_FID_S\t\t16\n+#define DYNAMIC_MAC_SRC_PORT_S\t\t24\n+#define DYNAMIC_MAC_TIMESTAMP_S\t\t27\n+#define DYNAMIC_MAC_ENTRIES_S\t\t29\n+#define DYNAMIC_MAC_ENTRIES_H_S\t\t3\n+\n+/**\n+ * MIB_COUNTER_VALUE\t\t\t00-00000000-3FFFFFFF\n+ * MIB_TOTAL_BYTES\t\t\t00-0000000F-FFFFFFFF\n+ * MIB_PACKET_DROPPED\t\t\t00-00000000-0000FFFF\n+ * MIB_COUNTER_VALID\t\t\t00-00000020-00000000\n+ * MIB_COUNTER_OVERFLOW\t\t\t00-00000040-00000000\n+ */\n+\n+#define MIB_COUNTER_OVERFLOW\t\tBIT(6)\n+#define MIB_COUNTER_VALID\t\tBIT(5)\n+\n+#define MIB_COUNTER_VALUE\t\t0x3FFFFFFF\n+\n+#define KS_MIB_TOTAL_RX_0\t\t0x100\n+#define KS_MIB_TOTAL_TX_0\t\t0x101\n+#define KS_MIB_PACKET_DROPPED_RX_0\t0x102\n+#define KS_MIB_PACKET_DROPPED_TX_0\t0x103\n+#define KS_MIB_TOTAL_RX_1\t\t0x104\n+#define KS_MIB_TOTAL_TX_1\t\t0x105\n+#define KS_MIB_PACKET_DROPPED_TX_1\t0x106\n+#define KS_MIB_PACKET_DROPPED_RX_1\t0x107\n+#define KS_MIB_TOTAL_RX_2\t\t0x108\n+#define KS_MIB_TOTAL_TX_2\t\t0x109\n+#define KS_MIB_PACKET_DROPPED_TX_2\t0x10A\n+#define KS_MIB_PACKET_DROPPED_RX_2\t0x10B\n+#define KS_MIB_TOTAL_RX_3\t\t0x10C\n+#define KS_MIB_TOTAL_TX_3\t\t0x10D\n+#define KS_MIB_PACKET_DROPPED_TX_3\t0x10E\n+#define KS_MIB_PACKET_DROPPED_RX_3\t0x10F\n+#define KS_MIB_TOTAL_RX_4\t\t0x110\n+#define KS_MIB_TOTAL_TX_4\t\t0x111\n+#define KS_MIB_PACKET_DROPPED_TX_4\t0x112\n+#define KS_MIB_PACKET_DROPPED_RX_4\t0x113\n+\n+#define MIB_PACKET_DROPPED\t\t0x0000FFFF\n+\n+#define MIB_TOTAL_BYTES_H\t\t0x0000000F\n+\n+#define TAIL_TAG_OVERRIDE\t\tBIT(6)\n+#define TAIL_TAG_LOOKUP\t\t\tBIT(7)\n+\n+#define VLAN_TABLE_ENTRIES\t\t(4096 / 4)\n+#define FID_ENTRIES\t\t\t128\n+\n+#endif\n",
    "prefixes": [
        "RFC",
        "4/5"
    ]
}