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GET /api/patches/811127/?format=api
{ "id": 811127, "url": "http://patchwork.ozlabs.org/api/patches/811127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170907120556.45699-6-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907120556.45699-6-alice.michael@intel.com>", "list_archive_url": null, "date": "2017-09-07T12:05:51", "name": "[next,S80-V3,06/11] i40e/i40evf: bump tail only in multiples of 8", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "583919b9c24554df6cd3aa9a64b03d41e989b85c", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170907120556.45699-6-alice.michael@intel.com/mbox/", "series": [ { "id": 2052, "url": "http://patchwork.ozlabs.org/api/series/2052/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=2052", "date": "2017-09-07T12:05:46", "name": "[next,S80-V3,01/11] i40e: use the safe hash table iterator when deleting mac filters", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2052/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811127/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811127/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpBRD2DpPz9sMN\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 06:11:04 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id DAC1330574;\n\tThu, 7 Sep 2017 20:11:02 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id H8DEOdwSPntb; Thu, 7 Sep 2017 20:11:01 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id E71FD3057B;\n\tThu, 7 Sep 2017 20:11:01 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id ADFE21CEB4A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 20:11:00 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id A5D5C85910\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 20:11:00 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id cIdBkYVHSziL for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 20:10:59 +0000 (UTC)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 58F4987A44\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 7 Sep 2017 20:10:59 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga105.fm.intel.com with ESMTP; 07 Sep 2017 13:10:58 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.16.121])\n\tby orsmga001.jf.intel.com with ESMTP; 07 Sep 2017 13:10:58 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,360,1500966000\"; d=\"scan'208\";\n\ta=\"1170126580\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Thu, 7 Sep 2017 08:05:51 -0400", "Message-Id": "<20170907120556.45699-6-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.9.4", "In-Reply-To": "<20170907120556.45699-1-alice.michael@intel.com>", "References": "<20170907120556.45699-1-alice.michael@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S80-V3 06/11] i40e/i40evf: bump tail\n\tonly in multiples of 8", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Jacob Keller <jacob.e.keller@intel.com>\n\nHardware only fetches descriptors on cachelines of 8, essentially\nignoring the lower 3 bits of the tail register. Thus, it is pointless to\nbump tail by an unaligned access as the hardware will ignore some of the\nnew descriptors we allocated. Thus, it's ideal if we can ensure tail\nwrites are always aligned to 8.\n\nAt first, it seems like we'd already do this, since we allocate\ndescriptors in batches which are a multiple of 8. Since we'd always\nincrement by a multiple of 8, it seems like the value should always be\naligned.\n\nHowever, this ignores allocation failures. If we fail to allocate\na buffer, our tail register will become unaligned. Once it has become\nunaligned it will essentially be stuck unaligned until a buffer\nallocation happens to fail at the exact amount necessary to re-align it.\n\nWe can do better, by simply rounding down the number of buffers we're\nabout to allocate (cleaned_count) such that \"next_to_clean\n+ cleaned_count\" is rounded to the nearest multiple of 8.\n\nWe do this by calculating how far off that value is and subtracting it\nfrom the cleaned_count. This essentially defers allocation of buffers if\nthey're going to be ignored by hardware anyways, and re-aligns our\nnext_to_use and tail values after a failure to allocate a descriptor.\n\nThis calculation ensures that we always align the tail writes in a way\nthe hardware expects and don't unnecessarily allocate buffers which\nwon't be fetched immediately.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 9 +++++++++\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 9 +++++++++\n 2 files changed, 18 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 0e9a910..94311e3 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -1372,6 +1372,15 @@ bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \tunion i40e_rx_desc *rx_desc;\n \tstruct i40e_rx_buffer *bi;\n \n+\t/* Hardware only fetches new descriptors in cache lines of 8,\n+\t * essentially ignoring the lower 3 bits of the tail register. We want\n+\t * to ensure our tail writes are aligned to avoid unnecessary work. We\n+\t * can't simply round down the cleaned count, since we might fail to\n+\t * allocate some buffers. What we really want is to ensure that\n+\t * next_to_used + cleaned_count produces an aligned value.\n+\t */\n+\tcleaned_count -= (ntu + cleaned_count) & 0x7;\n+\n \t/* do nothing if no valid netdev defined */\n \tif (!rx_ring->netdev || !cleaned_count)\n \t\treturn false;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 4ae054d..212fc1f 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -711,6 +711,15 @@ bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)\n \tunion i40e_rx_desc *rx_desc;\n \tstruct i40e_rx_buffer *bi;\n \n+\t/* Hardware only fetches new descriptors in cache lines of 8,\n+\t * essentially ignoring the lower 3 bits of the tail register. We want\n+\t * to ensure our tail writes are aligned to avoid unnecessary work. We\n+\t * can't simply round down the cleaned count, since we might fail to\n+\t * allocate some buffers. What we really want is to ensure that\n+\t * next_to_used + cleaned_count produces an aligned value.\n+\t */\n+\tcleaned_count -= (ntu + cleaned_count) & 0x7;\n+\n \t/* do nothing if no valid netdev defined */\n \tif (!rx_ring->netdev || !cleaned_count)\n \t\treturn false;\n", "prefixes": [ "next", "S80-V3", "06/11" ] }