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GET /api/patches/811117/?format=api
{ "id": 811117, "url": "http://patchwork.ozlabs.org/api/patches/811117/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-5-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907185057.23421-5-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:50:56", "name": "[v2,4/5] target/sh4: Convert to DisasContextBase", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d5c6a14a1c4fc86532f6e0d99a51d04b682758a", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-5-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2042, "url": "http://patchwork.ozlabs.org/api/series/2042/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2042", "date": "2017-09-07T18:50:52", "name": "target/sh4 updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2042/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811117/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811117/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"U4JrNREy\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp8lD2xXrz9sBW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:54:48 +1000 (AEST)", "from localhost ([::1]:41778 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1ws-0002sN-H2\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:54:46 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54189)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tQ-0000Dx-B1\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:18 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tK-0000Wa-7N\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:12 -0400", "from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:33555)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1tJ-0000W0-VB\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:06 -0400", "by mail-pg0-x22e.google.com with SMTP id t3so1011170pgt.0\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:51:05 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tl74sm481401pfi.9.2017.09.07.11.51.02\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:51:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=4i80/mNJBgdsRZ6rI0oMRFx3xHTE62r5Hp+trlIew1s=;\n\tb=U4JrNREynaBrJh9am2WUR74AJwRgjiPSL5k00YBPqoxbdQLa3S62Ika7zu++3JsdAc\n\t/WPA0Ozz6JSw8jJ18zuBzda1jYiZjElZXaS8K2Pudw5bj1AbsBvEYKE9X/qW1gBFJAk8\n\txmNt7DUno4H+gzt9fIEEBN6tZcyVp4/8yMmqo=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=4i80/mNJBgdsRZ6rI0oMRFx3xHTE62r5Hp+trlIew1s=;\n\tb=rRs15+8e3DUepEm3OfbHa1LdqEZqWWXzz+zfhFG3Nbna8Vd3WpLX7Tb/+8cGJFvxv9\n\tZXq70CAkOkwNF/wVp6jnqd7Ry+aD2JPlawoM0w9wQjTbGVaEgG6+RsZasGGsr6Jfdqlg\n\tI2yrvu7ObGqgMT2g922cHhcVWJWamvnpwVqSX7+UqQCbvPM/G73g0g2hpyWI/0DjWiud\n\tr+s4QF7ubEU3MINbV9VDLy+g7lQGHORZ6rvtPYZEGx4lyKLHjiaLXmCVJqU9vttnsBSm\n\t0YWcmpVBHl3ctU+v/irnxDYFfbf4YXhAVZySkRVxY6EcStjazHn7W3wIZtTHHXcbOXMr\n\tXXJg==", "X-Gm-Message-State": "AHPjjUjBNxRLh9ZlA4ENRlB/+3Koq4jSPkfwl0U9JN7OHeX4bs5eiUjB\n\tSf4j1xyJXB+EyApyAbloSg==", "X-Google-Smtp-Source": "ADKCNb57dtXnGFCor03Cox8ncJNeJgxgl0aX8WZKcibrtsPz0r308SP28Y3FjSx4VgZHV++Uq6MN3A==", "X-Received": "by 10.98.245.207 with SMTP id b76mr307435pfm.223.1504810264426; \n\tThu, 07 Sep 2017 11:51:04 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:50:56 -0700", "Message-Id": "<20170907185057.23421-5-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907185057.23421-1-richard.henderson@linaro.org>", "References": "<20170907185057.23421-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22e", "Subject": "[Qemu-devel] [PATCH v2 4/5] target/sh4: Convert to DisasContextBase", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "aurelien@aurel32.net, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/sh4/translate.c | 146 ++++++++++++++++++++++++-------------------------\n 1 file changed, 73 insertions(+), 73 deletions(-)", "diff": "diff --git a/target/sh4/translate.c b/target/sh4/translate.c\nindex 5cda27cc0a..ed462bab12 100644\n--- a/target/sh4/translate.c\n+++ b/target/sh4/translate.c\n@@ -33,19 +33,19 @@\n \n \n typedef struct DisasContext {\n- struct TranslationBlock *tb;\n- target_ulong pc;\n- uint16_t opcode;\n- uint32_t tbflags; /* should stay unmodified during the TB translation */\n- uint32_t envflags; /* should stay in sync with env->flags using TCG ops */\n- DisasJumpType bstate;\n+ DisasContextBase base;\n+\n+ uint32_t tbflags; /* should stay unmodified during the TB translation */\n+ uint32_t envflags; /* should stay in sync with env->flags using TCG ops */\n int memidx;\n int gbank;\n int fbank;\n uint32_t delayed_pc;\n- int singlestep_enabled;\n uint32_t features;\n- int has_movcal;\n+\n+ uint16_t opcode;\n+\n+ bool has_movcal;\n } DisasContext;\n \n #if defined(CONFIG_USER_ONLY)\n@@ -54,7 +54,7 @@ typedef struct DisasContext {\n #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))\n #endif\n \n-/* Target-specific values for ctx->bstate. */\n+/* Target-specific values for ctx->base.is_jmp. */\n /* We want to exit back to the cpu loop for some reason.\n Usually this is to recognize interrupts immediately. */\n #define DISAS_STOP DISAS_TARGET_0\n@@ -220,7 +220,7 @@ static void gen_write_sr(TCGv src)\n static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)\n {\n if (save_pc) {\n- tcg_gen_movi_i32(cpu_pc, ctx->pc);\n+ tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);\n }\n if (ctx->delayed_pc != (uint32_t) -1) {\n tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);\n@@ -238,11 +238,11 @@ static inline bool use_exit_tb(DisasContext *ctx)\n static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)\n {\n /* Use a direct jump if in same page and singlestep not enabled */\n- if (unlikely(ctx->singlestep_enabled || use_exit_tb(ctx))) {\n+ if (unlikely(ctx->base.singlestep_enabled || use_exit_tb(ctx))) {\n return false;\n }\n #ifndef CONFIG_USER_ONLY\n- return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);\n+ return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);\n #else\n return true;\n #endif\n@@ -253,10 +253,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)\n if (use_goto_tb(ctx, dest)) {\n tcg_gen_goto_tb(n);\n tcg_gen_movi_i32(cpu_pc, dest);\n- tcg_gen_exit_tb((uintptr_t)ctx->tb + n);\n+ tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n);\n } else {\n tcg_gen_movi_i32(cpu_pc, dest);\n- if (ctx->singlestep_enabled) {\n+ if (ctx->base.singlestep_enabled) {\n gen_helper_debug(cpu_env);\n } else if (use_exit_tb(ctx)) {\n tcg_gen_exit_tb(0);\n@@ -264,7 +264,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n }\n }\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_jump(DisasContext * ctx)\n@@ -274,14 +274,14 @@ static void gen_jump(DisasContext * ctx)\n \t delayed jump as immediate jump are conditinal jumps */\n \ttcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);\n tcg_gen_discard_i32(cpu_delayed_pc);\n- if (ctx->singlestep_enabled) {\n+\tif (ctx->base.singlestep_enabled) {\n gen_helper_debug(cpu_env);\n } else if (use_exit_tb(ctx)) {\n tcg_gen_exit_tb(0);\n } else {\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n }\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n } else {\n \tgen_goto_tb(ctx, 0, ctx->delayed_pc);\n }\n@@ -311,8 +311,8 @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,\n tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);\n gen_goto_tb(ctx, 0, dest);\n gen_set_label(l1);\n- gen_goto_tb(ctx, 1, ctx->pc + 2);\n- ctx->bstate = DISAS_NORETURN;\n+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 2);\n+ ctx->base.is_jmp = DISAS_NORETURN;\n }\n \n /* Delayed conditional jump (bt or bf) */\n@@ -335,12 +335,12 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)\n gen_jump(ctx);\n \n gen_set_label(l1);\n- ctx->bstate = DISAS_NEXT;\n+ ctx->base.is_jmp = DISAS_NEXT;\n return;\n }\n \n tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);\n- gen_goto_tb(ctx, 1, ctx->pc + 2);\n+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 2);\n gen_set_label(l1);\n gen_jump(ctx);\n }\n@@ -477,7 +477,7 @@ static void _decode_opc(DisasContext * ctx)\n \ttcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);\n ctx->envflags |= DELAY_SLOT_RTE;\n \tctx->delayed_pc = (uint32_t) - 1;\n- ctx->bstate = DISAS_STOP;\n+ ctx->base.is_jmp = DISAS_STOP;\n \treturn;\n case 0x0058:\t\t/* sets */\n tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));\n@@ -488,23 +488,23 @@ static void _decode_opc(DisasContext * ctx)\n case 0xfbfd:\t\t/* frchg */\n CHECK_FPSCR_PR_0\n \ttcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);\n-\tctx->bstate = DISAS_STOP;\n+\tctx->base.is_jmp = DISAS_STOP;\n \treturn;\n case 0xf3fd:\t\t/* fschg */\n CHECK_FPSCR_PR_0\n tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);\n-\tctx->bstate = DISAS_STOP;\n+\tctx->base.is_jmp = DISAS_STOP;\n \treturn;\n case 0xf7fd: /* fpchg */\n CHECK_SH4A\n tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR);\n- ctx->bstate = DISAS_STOP;\n+ ctx->base.is_jmp = DISAS_STOP;\n return;\n case 0x0009:\t\t/* nop */\n \treturn;\n case 0x001b:\t\t/* sleep */\n \tCHECK_PRIVILEGED\n- tcg_gen_movi_i32(cpu_pc, ctx->pc + 2);\n+ tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2);\n gen_helper_sleep(cpu_env);\n \treturn;\n }\n@@ -533,21 +533,21 @@ static void _decode_opc(DisasContext * ctx)\n region (stored in R0) in the next TB. */\n if (B11_8 == 15 && B7_0s < 0 && parallel_cpus) {\n ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);\n- ctx->bstate = DISAS_STOP;\n+ ctx->base.is_jmp = DISAS_STOP;\n }\n #endif\n \ttcg_gen_movi_i32(REG(B11_8), B7_0s);\n \treturn;\n case 0x9000:\t\t/* mov.w @(disp,PC),Rn */\n \t{\n-\t TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);\n+\t TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2);\n tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);\n \t tcg_temp_free(addr);\n \t}\n \treturn;\n case 0xd000:\t\t/* mov.l @(disp,PC),Rn */\n \t{\n-\t TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);\n+\t TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);\n tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);\n \t tcg_temp_free(addr);\n \t}\n@@ -557,13 +557,13 @@ static void _decode_opc(DisasContext * ctx)\n \treturn;\n case 0xa000:\t\t/* bra disp */\n \tCHECK_NOT_DELAY_SLOT\n-\tctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;\n+\tctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;\n ctx->envflags |= DELAY_SLOT;\n \treturn;\n case 0xb000:\t\t/* bsr disp */\n \tCHECK_NOT_DELAY_SLOT\n-\ttcg_gen_movi_i32(cpu_pr, ctx->pc + 4);\n-\tctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;\n+\ttcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);\n+\tctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;\n ctx->envflags |= DELAY_SLOT;\n \treturn;\n }\n@@ -1190,22 +1190,22 @@ static void _decode_opc(DisasContext * ctx)\n \treturn;\n case 0x8b00:\t\t/* bf label */\n \tCHECK_NOT_DELAY_SLOT\n- gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, false);\n+ gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, false);\n \treturn;\n case 0x8f00:\t\t/* bf/s label */\n \tCHECK_NOT_DELAY_SLOT\n tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1);\n- ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2;\n+ ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;\n ctx->envflags |= DELAY_SLOT_CONDITIONAL;\n \treturn;\n case 0x8900:\t\t/* bt label */\n \tCHECK_NOT_DELAY_SLOT\n- gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, true);\n+ gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, true);\n \treturn;\n case 0x8d00:\t\t/* bt/s label */\n \tCHECK_NOT_DELAY_SLOT\n tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t);\n- ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2;\n+ ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;\n ctx->envflags |= DELAY_SLOT_CONDITIONAL;\n \treturn;\n case 0x8800:\t\t/* cmp/eq #imm,R0 */\n@@ -1292,7 +1292,7 @@ static void _decode_opc(DisasContext * ctx)\n \t}\n \treturn;\n case 0xc700:\t\t/* mova @(disp,PC),R0 */\n-\ttcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);\n+\ttcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + 4 + B7_0 * 4) & ~3);\n \treturn;\n case 0xcb00:\t\t/* or #imm,R0 */\n \ttcg_gen_ori_i32(REG(0), REG(0), B7_0);\n@@ -1318,7 +1318,7 @@ static void _decode_opc(DisasContext * ctx)\n \t imm = tcg_const_i32(B7_0);\n gen_helper_trapa(cpu_env, imm);\n \t tcg_temp_free(imm);\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n \t}\n \treturn;\n case 0xc800:\t\t/* tst #imm,R0 */\n@@ -1386,13 +1386,13 @@ static void _decode_opc(DisasContext * ctx)\n switch (ctx->opcode & 0xf0ff) {\n case 0x0023:\t\t/* braf Rn */\n \tCHECK_NOT_DELAY_SLOT\n-\ttcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);\n+\ttcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4);\n ctx->envflags |= DELAY_SLOT;\n \tctx->delayed_pc = (uint32_t) - 1;\n \treturn;\n case 0x0003:\t\t/* bsrf Rn */\n \tCHECK_NOT_DELAY_SLOT\n-\ttcg_gen_movi_i32(cpu_pr, ctx->pc + 4);\n+\ttcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);\n \ttcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);\n ctx->envflags |= DELAY_SLOT;\n \tctx->delayed_pc = (uint32_t) - 1;\n@@ -1415,7 +1415,7 @@ static void _decode_opc(DisasContext * ctx)\n \treturn;\n case 0x400b:\t\t/* jsr @Rn */\n \tCHECK_NOT_DELAY_SLOT\n-\ttcg_gen_movi_i32(cpu_pr, ctx->pc + 4);\n+\ttcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);\n \ttcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));\n ctx->envflags |= DELAY_SLOT;\n \tctx->delayed_pc = (uint32_t) - 1;\n@@ -1427,7 +1427,7 @@ static void _decode_opc(DisasContext * ctx)\n tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3);\n gen_write_sr(val);\n tcg_temp_free(val);\n- ctx->bstate = DISAS_STOP;\n+ ctx->base.is_jmp = DISAS_STOP;\n }\n \treturn;\n case 0x4007:\t\t/* ldc.l @Rm+,SR */\n@@ -1439,7 +1439,7 @@ static void _decode_opc(DisasContext * ctx)\n gen_write_sr(val);\n \t tcg_temp_free(val);\n \t tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);\n-\t ctx->bstate = DISAS_STOP;\n+\t ctx->base.is_jmp = DISAS_STOP;\n \t}\n \treturn;\n case 0x0002:\t\t/* stc SR,Rn */\n@@ -1501,7 +1501,7 @@ static void _decode_opc(DisasContext * ctx)\n case 0x406a:\t\t/* lds Rm,FPSCR */\n \tCHECK_FPU_ENABLED\n gen_helper_ld_fpscr(cpu_env, REG(B11_8));\n-\tctx->bstate = DISAS_STOP;\n+\tctx->base.is_jmp = DISAS_STOP;\n \treturn;\n case 0x4066:\t\t/* lds.l @Rm+,FPSCR */\n \tCHECK_FPU_ENABLED\n@@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx)\n \t tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);\n gen_helper_ld_fpscr(cpu_env, addr);\n \t tcg_temp_free(addr);\n-\t ctx->bstate = DISAS_STOP;\n+\t ctx->base.is_jmp = DISAS_STOP;\n \t}\n \treturn;\n case 0x006a:\t\t/* sts FPSCR,Rn */\n@@ -1835,7 +1835,7 @@ static void _decode_opc(DisasContext * ctx)\n }\n #if 0\n fprintf(stderr, \"unknown instruction 0x%04x at pc 0x%08x\\n\",\n-\t ctx->opcode, ctx->pc);\n+\t ctx->opcode, ctx->base.pc_next);\n fflush(stderr);\n #endif\n do_illegal:\n@@ -1847,7 +1847,7 @@ static void _decode_opc(DisasContext * ctx)\n gen_save_cpu_state(ctx, true);\n gen_helper_raise_illegal_instruction(cpu_env);\n }\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n return;\n \n do_fpu_disabled:\n@@ -1857,7 +1857,7 @@ static void _decode_opc(DisasContext * ctx)\n } else {\n gen_helper_raise_fpu_disable(cpu_env);\n }\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n return;\n }\n \n@@ -1909,8 +1909,8 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n int mv_src, mt_dst, st_src, st_mop;\n TCGv op_arg;\n \n- uint32_t pc = ctx->pc;\n- uint32_t pc_end = ctx->tb->cs_base;\n+ uint32_t pc = ctx->base.pc_next;\n+ uint32_t pc_end = ctx->base.tb->cs_base;\n int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);\n int max_insns = (pc_end - pc) / 2;\n int i;\n@@ -2240,7 +2240,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n \n /* The entire region has been translated. */\n ctx->envflags &= ~GUSA_MASK;\n- ctx->pc = pc_end;\n+ ctx->base.pc_next = pc_end;\n return max_insns;\n \n fail:\n@@ -2253,13 +2253,13 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n ctx->envflags |= GUSA_EXCLUSIVE;\n gen_save_cpu_state(ctx, false);\n gen_helper_exclusive(cpu_env);\n- ctx->bstate = DISAS_NORETURN;\n+ ctx->base.is_jmp = DISAS_NORETURN;\n \n /* We're not executing an instruction, but we must report one for the\n purposes of accounting within the TB. We might as well report the\n- entire region consumed via ctx->pc so that it's immediately available\n- in the disassembly dump. */\n- ctx->pc = pc_end;\n+ entire region consumed via ctx->base.pc_next so that it's immediately\n+ available in the disassembly dump. */\n+ ctx->base.pc_next = pc_end;\n return 1;\n }\n #endif\n@@ -2273,16 +2273,16 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n int max_insns;\n \n pc_start = tb->pc;\n- ctx.pc = pc_start;\n+ ctx.base.pc_next = pc_start;\n ctx.tbflags = (uint32_t)tb->flags;\n ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;\n- ctx.bstate = DISAS_NEXT;\n+ ctx.base.is_jmp = DISAS_NEXT;\n ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;\n /* We don't know if the delayed pc came from a dynamic or static branch,\n so assume it is a dynamic branch. */\n ctx.delayed_pc = -1; /* use delayed pc from env pointer */\n- ctx.tb = tb;\n- ctx.singlestep_enabled = cs->singlestep_enabled;\n+ ctx.base.tb = tb;\n+ ctx.base.singlestep_enabled = cs->singlestep_enabled;\n ctx.features = env->features;\n ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);\n ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&\n@@ -2297,11 +2297,11 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n \n /* Since the ISA is fixed-width, we can bound by the number\n of instructions remaining on the page. */\n- num_insns = -(ctx.pc | TARGET_PAGE_MASK) / 2;\n+ num_insns = -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2;\n max_insns = MIN(max_insns, num_insns);\n \n /* Single stepping means just that. */\n- if (ctx.singlestep_enabled || singlestep) {\n+ if (ctx.base.singlestep_enabled || singlestep) {\n max_insns = 1;\n }\n \n@@ -2314,22 +2314,22 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n }\n #endif\n \n- while (ctx.bstate == DISAS_NEXT\n+ while (ctx.base.is_jmp == DISAS_NEXT\n && num_insns < max_insns\n && !tcg_op_buf_full()) {\n- tcg_gen_insn_start(ctx.pc, ctx.envflags);\n+ tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags);\n num_insns++;\n \n- if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {\n+ if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {\n /* We have hit a breakpoint - make sure PC is up-to-date */\n gen_save_cpu_state(&ctx, true);\n gen_helper_debug(cpu_env);\n- ctx.bstate = DISAS_NORETURN;\n+ ctx.base.is_jmp = DISAS_NORETURN;\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n the logic setting tb->size below does the right thing. */\n- ctx.pc += 2;\n+ ctx.base.pc_next += 2;\n break;\n }\n \n@@ -2337,9 +2337,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n gen_io_start();\n }\n \n- ctx.opcode = cpu_lduw_code(env, ctx.pc);\n+ ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);\n \tdecode_opc(&ctx);\n-\tctx.pc += 2;\n+\tctx.base.pc_next += 2;\n }\n if (tb->cflags & CF_LAST_IO) {\n gen_io_end();\n@@ -2350,10 +2350,10 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n ctx.envflags &= ~GUSA_MASK;\n }\n \n- switch (ctx.bstate) {\n+ switch (ctx.base.is_jmp) {\n case DISAS_STOP:\n gen_save_cpu_state(&ctx, true);\n- if (cs->singlestep_enabled) {\n+ if (ctx.base.singlestep_enabled) {\n gen_helper_debug(cpu_env);\n } else {\n tcg_gen_exit_tb(0);\n@@ -2361,7 +2361,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n break;\n case DISAS_NEXT:\n gen_save_cpu_state(&ctx, false);\n- gen_goto_tb(&ctx, 0, ctx.pc);\n+ gen_goto_tb(&ctx, 0, ctx.base.pc_next);\n break;\n case DISAS_NORETURN:\n break;\n@@ -2371,7 +2371,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n \n gen_tb_end(tb, num_insns);\n \n- tb->size = ctx.pc - pc_start;\n+ tb->size = ctx.base.pc_next - pc_start;\n tb->icount = num_insns;\n \n #ifdef DEBUG_DISAS\n@@ -2379,7 +2379,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n && qemu_log_in_addr_range(pc_start)) {\n qemu_log_lock();\n \tqemu_log(\"IN:\\n\");\t/* , lookup_symbol(pc_start)); */\n- log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);\n+ log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 0);\n \tqemu_log(\"\\n\");\n qemu_log_unlock();\n }\n", "prefixes": [ "v2", "4/5" ] }