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GET /api/patches/811116/?format=api
{ "id": 811116, "url": "http://patchwork.ozlabs.org/api/patches/811116/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-6-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907185057.23421-6-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:50:57", "name": "[v2,5/5] target/sh4: Convert to TranslatorOps", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad3a85a2b48252c7cd4138600e5b1ce7ace798e3", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-6-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2042, "url": "http://patchwork.ozlabs.org/api/series/2042/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2042", "date": "2017-09-07T18:50:52", "name": "target/sh4 updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2042/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811116/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811116/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"L9oXoSq2\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp8kM215Dz9t1t\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:54:01 +1000 (AEST)", "from localhost ([::1]:41777 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1w7-0002FR-FR\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:53:59 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54202)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tR-0000F0-K2\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:19 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tL-0000XV-Qi\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:13 -0400", "from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:33555)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1tL-0000X8-Ie\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:07 -0400", "by mail-pg0-x232.google.com with SMTP id t3so1011282pgt.0\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:51:07 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tl74sm481401pfi.9.2017.09.07.11.51.04\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:51:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=jYYKiAzIoFqTuiYuHu7WB/C983bpNQLGILsQ08P+xLU=;\n\tb=L9oXoSq2DECuoNTmPYiJrBxhVEXZjIc9k9ATFvMVK/lkF0V+6K6/GVrG8OMAxRsnu+\n\tnG8maRpFw9w/DYrKpxBV4+zyFbOOK6TOvADFF8bN3uLapy/jpiZZPqZr3oxgSFpJ79YY\n\tRHvypP+VSJ0Uq8XqTl/wP7MvraAz8o5Zg6pOA=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=jYYKiAzIoFqTuiYuHu7WB/C983bpNQLGILsQ08P+xLU=;\n\tb=J5zHP3Uuay3ZCBa55xUFEEaqmcg1UZqWchxhxmu+GB9jc80/CNQx6PJVeb2vQ+9Eut\n\tQetY0iA3B9pY4rQxnf8Vw7KoZnEAd2jK835x2XLt+FjbjAQ9+QPgeBS7kYXuhtpQ3ep2\n\trVkFAYIVpDVA1Z2kcnQY7fyjgRPJTb/lt8JlQgRKnQmngNFLViKT7DgbfC5YRQOwNdCl\n\tRCWfkmetgJNa/Ul8qdHNu76TG60uW+2nyaKW5YZ5l4K38G5kEI2tqjh5oS/Zixqi3zXQ\n\tWbpKOGsz2iTEVHweQ7dw+Sy8KwKdJ0qy2GzVtBP2l9xtkCeKhBpPd1Aq625CIvPzkoK5\n\tGlQA==", "X-Gm-Message-State": "AHPjjUgLxRM7RQmMXQGtDWg+17m4jlynx8Gq9+1hvs/dZvjlWHOQA1Ro\n\tgT26VUMdYIdAkUrFA/birg==", "X-Google-Smtp-Source": "ADKCNb4UTrOyIFVlHybwFTK+9HCXZVjleW8bbYPFbYbCgAcV7X4N0XMGttkp/qcHxC1uTU/dnLEh9w==", "X-Received": "by 10.98.224.92 with SMTP id f89mr363499pfh.138.1504810266049;\n\tThu, 07 Sep 2017 11:51:06 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:50:57 -0700", "Message-Id": "<20170907185057.23421-6-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907185057.23421-1-richard.henderson@linaro.org>", "References": "<20170907185057.23421-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::232", "Subject": "[Qemu-devel] [PATCH v2 5/5] target/sh4: Convert to TranslatorOps", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "aurelien@aurel32.net, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/sh4/translate.c | 272 ++++++++++++++++++++++++++-----------------------\n 1 file changed, 147 insertions(+), 125 deletions(-)", "diff": "diff --git a/target/sh4/translate.c b/target/sh4/translate.c\nindex ed462bab12..ca6589047b 100644\n--- a/target/sh4/translate.c\n+++ b/target/sh4/translate.c\n@@ -34,6 +34,9 @@\n \n typedef struct DisasContext {\n DisasContextBase base;\n+#ifdef CONFIG_USER_ONLY\n+ TranslatorOps ops;\n+#endif\n \n uint32_t tbflags; /* should stay unmodified during the TB translation */\n uint32_t envflags; /* should stay in sync with env->flags using TCG ops */\n@@ -1892,6 +1895,100 @@ static void decode_opc(DisasContext * ctx)\n }\n \n #ifdef CONFIG_USER_ONLY\n+static void sh4_tr_translate_gusa(DisasContextBase *dcbase, CPUState *cpu);\n+#endif\n+\n+static int sh4_tr_init_disas_context(DisasContextBase *dcbase,\n+ CPUState *cpu, int max_insns)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+ CPUSH4State *env = cpu->env_ptr;\n+ uint32_t pc = ctx->base.pc_next;\n+ uint32_t tbflags = ctx->base.tb->flags;\n+ int bound;\n+\n+ ctx->tbflags = tbflags;\n+ ctx->envflags = tbflags & TB_FLAG_ENVFLAGS_MASK;\n+ ctx->memidx = (tbflags & (1u << SR_MD)) == 0 ? 1 : 0;\n+ /* We don't know if the delayed pc came from a dynamic or static branch,\n+ so assume it is a dynamic branch. */\n+ ctx->delayed_pc = -1; /* use delayed pc from env pointer */\n+ ctx->features = env->features;\n+ ctx->has_movcal = (tbflags & TB_FLAG_PENDING_MOVCA) != 0;\n+ ctx->gbank = ((tbflags & (1 << SR_MD)) &&\n+ (tbflags & (1 << SR_RB))) * 0x10;\n+ ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0;\n+\n+ /* Since the ISA is fixed-width, we can bound by the number\n+ of instructions remaining on the page. */\n+ bound = -(pc | TARGET_PAGE_MASK) / 2;\n+ max_insns = MIN(max_insns, bound);\n+\n+#ifdef CONFIG_USER_ONLY\n+ if (tbflags & GUSA_MASK) {\n+ uint32_t pc_end = ctx->base.tb->cs_base;\n+ int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);\n+ int gusa_insns = -backup / 2;\n+\n+ if (pc != pc_end + backup || gusa_insns < 2) {\n+ /* This is a malformed gUSA region. Don't do anything special,\n+ since the interpreter is likely to get confused. */\n+ ctx->envflags &= ~GUSA_MASK;\n+ } else if (tbflags & GUSA_EXCLUSIVE) {\n+ /* Regardless of single-stepping or the end of the page,\n+ we must complete execution of the gUSA region while\n+ holding the exclusive lock. */\n+ max_insns = gusa_insns;\n+ } else {\n+ /* Attempt to translate to an atomic insn. */\n+ ctx->ops.translate_insn = sh4_tr_translate_gusa;\n+ }\n+ }\n+#endif\n+\n+ return max_insns;\n+}\n+\n+static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+}\n+\n+static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+\n+ tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);\n+}\n+\n+static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+\n+ /* We have hit a breakpoint - make sure PC is up-to-date */\n+ gen_save_cpu_state(ctx, true);\n+ gen_helper_debug(cpu_env);\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+\n+ /* The address covered by the breakpoint must be included in\n+ [tb->pc, tb->pc + tb->size) in order to for it to be\n+ properly cleared -- thus we increment the PC here so that\n+ the logic setting tb->size below does the right thing. */\n+ ctx->base.pc_next += 2;\n+ return true;\n+}\n+\n+static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+ CPUSH4State *env = cpu->env_ptr;\n+\n+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);\n+ decode_opc(ctx);\n+ ctx->base.pc_next += 2;\n+}\n+\n+#ifdef CONFIG_USER_ONLY\n /* For uniprocessors, SH4 uses optimistic restartable atomic sequences.\n Upon an interrupt, a real kernel would simply notice magic values in\n the registers and reset the PC to the start of the sequence.\n@@ -1901,35 +1998,23 @@ static void decode_opc(DisasContext * ctx)\n any sequence via cpu_exec_step_atomic, we can recognize the \"normal\"\n sequences and transform them into atomic operations as seen by the host.\n */\n-static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n+static void sh4_tr_translate_gusa(DisasContextBase *dcbase, CPUState *cpu)\n {\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n+ CPUSH4State *env = cpu->env_ptr;\n+\n+ int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);\n+ int max_insns = -backup / 2;\n+ uint32_t pc = ctx->base.pc_next;\n+ uint32_t pc_end = ctx->base.tb->cs_base;\n+\n uint16_t insns[5];\n int ld_adr, ld_dst, ld_mop;\n int op_dst, op_src, op_opc;\n int mv_src, mt_dst, st_src, st_mop;\n TCGv op_arg;\n-\n- uint32_t pc = ctx->base.pc_next;\n- uint32_t pc_end = ctx->base.tb->cs_base;\n- int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);\n- int max_insns = (pc_end - pc) / 2;\n int i;\n \n- if (pc != pc_end + backup || max_insns < 2) {\n- /* This is a malformed gUSA region. Don't do anything special,\n- since the interpreter is likely to get confused. */\n- ctx->envflags &= ~GUSA_MASK;\n- return 0;\n- }\n-\n- if (ctx->tbflags & GUSA_EXCLUSIVE) {\n- /* Regardless of single-stepping or the end of the page,\n- we must complete execution of the gUSA region while\n- holding the exclusive lock. */\n- *pmax_insns = max_insns;\n- return 0;\n- }\n-\n /* The state machine below will consume only a few insns.\n If there are more than that in a region, fail now. */\n if (max_insns > ARRAY_SIZE(insns)) {\n@@ -2146,7 +2231,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n /*\n * Emit the operation.\n */\n- tcg_gen_insn_start(pc, ctx->envflags);\n switch (op_opc) {\n case -1:\n /* No operation found. Look for exchange pattern. */\n@@ -2239,9 +2323,13 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n }\n \n /* The entire region has been translated. */\n- ctx->envflags &= ~GUSA_MASK;\n ctx->base.pc_next = pc_end;\n- return max_insns;\n+ ctx->base.num_insns = max_insns;\n+\n+ /* Revert to normal parsing for the rest of the TB. */\n+ ctx->envflags &= ~GUSA_MASK;\n+ ctx->ops.translate_insn = sh4_tr_translate_insn;\n+ return;\n \n fail:\n qemu_log_mask(LOG_UNIMP, \"Unrecognized gUSA sequence %08x-%08x\\n\",\n@@ -2249,7 +2337,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n \n /* Restart with the EXCLUSIVE bit set, within a TB run via\n cpu_exec_step_atomic holding the exclusive lock. */\n- tcg_gen_insn_start(pc, ctx->envflags);\n ctx->envflags |= GUSA_EXCLUSIVE;\n gen_save_cpu_state(ctx, false);\n gen_helper_exclusive(cpu_env);\n@@ -2260,129 +2347,64 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n entire region consumed via ctx->base.pc_next so that it's immediately\n available in the disassembly dump. */\n ctx->base.pc_next = pc_end;\n- return 1;\n }\n #endif\n \n-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n+static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n {\n- CPUSH4State *env = cs->env_ptr;\n- DisasContext ctx;\n- target_ulong pc_start;\n- int num_insns;\n- int max_insns;\n-\n- pc_start = tb->pc;\n- ctx.base.pc_next = pc_start;\n- ctx.tbflags = (uint32_t)tb->flags;\n- ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;\n- ctx.base.is_jmp = DISAS_NEXT;\n- ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;\n- /* We don't know if the delayed pc came from a dynamic or static branch,\n- so assume it is a dynamic branch. */\n- ctx.delayed_pc = -1; /* use delayed pc from env pointer */\n- ctx.base.tb = tb;\n- ctx.base.singlestep_enabled = cs->singlestep_enabled;\n- ctx.features = env->features;\n- ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);\n- ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&\n- (ctx.tbflags & (1 << SR_RB))) * 0x10;\n- ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- max_insns = MIN(max_insns, TCG_MAX_INSNS);\n-\n- /* Since the ISA is fixed-width, we can bound by the number\n- of instructions remaining on the page. */\n- num_insns = -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2;\n- max_insns = MIN(max_insns, num_insns);\n+ DisasContext *ctx = container_of(dcbase, DisasContext, base);\n \n- /* Single stepping means just that. */\n- if (ctx.base.singlestep_enabled || singlestep) {\n- max_insns = 1;\n- }\n-\n- gen_tb_start(tb);\n- num_insns = 0;\n-\n-#ifdef CONFIG_USER_ONLY\n- if (ctx.tbflags & GUSA_MASK) {\n- num_insns = decode_gusa(&ctx, env, &max_insns);\n- }\n-#endif\n-\n- while (ctx.base.is_jmp == DISAS_NEXT\n- && num_insns < max_insns\n- && !tcg_op_buf_full()) {\n- tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags);\n- num_insns++;\n-\n- if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) {\n- /* We have hit a breakpoint - make sure PC is up-to-date */\n- gen_save_cpu_state(&ctx, true);\n- gen_helper_debug(cpu_env);\n- ctx.base.is_jmp = DISAS_NORETURN;\n- /* The address covered by the breakpoint must be included in\n- [tb->pc, tb->pc + tb->size) in order to for it to be\n- properly cleared -- thus we increment the PC here so that\n- the logic setting tb->size below does the right thing. */\n- ctx.base.pc_next += 2;\n- break;\n- }\n-\n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- ctx.opcode = cpu_lduw_code(env, ctx.base.pc_next);\n-\tdecode_opc(&ctx);\n-\tctx.base.pc_next += 2;\n- }\n- if (tb->cflags & CF_LAST_IO) {\n- gen_io_end();\n- }\n-\n- if (ctx.tbflags & GUSA_EXCLUSIVE) {\n+ if (ctx->tbflags & GUSA_EXCLUSIVE) {\n /* Ending the region of exclusivity. Clear the bits. */\n- ctx.envflags &= ~GUSA_MASK;\n+ ctx->envflags &= ~GUSA_MASK;\n }\n \n- switch (ctx.base.is_jmp) {\n+ switch (ctx->base.is_jmp) {\n case DISAS_STOP:\n- gen_save_cpu_state(&ctx, true);\n- if (ctx.base.singlestep_enabled) {\n+ gen_save_cpu_state(ctx, true);\n+ if (ctx->base.singlestep_enabled) {\n gen_helper_debug(cpu_env);\n } else {\n tcg_gen_exit_tb(0);\n }\n break;\n- case DISAS_NEXT:\n- gen_save_cpu_state(&ctx, false);\n- gen_goto_tb(&ctx, 0, ctx.base.pc_next);\n+ case DISAS_TOO_MANY:\n+ gen_save_cpu_state(ctx, false);\n+ gen_goto_tb(ctx, 0, ctx->base.pc_next);\n break;\n case DISAS_NORETURN:\n break;\n default:\n g_assert_not_reached();\n }\n+}\n \n- gen_tb_end(tb, num_insns);\n+static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ qemu_log(\"IN: %s\\n\", lookup_symbol(dcbase->pc_first));\n+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size, 0);\n+}\n \n- tb->size = ctx.base.pc_next - pc_start;\n- tb->icount = num_insns;\n+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb)\n+{\n+ static const TranslatorOps ops = {\n+ .init_disas_context = sh4_tr_init_disas_context,\n+ .tb_start = sh4_tr_tb_start,\n+ .insn_start = sh4_tr_insn_start,\n+ .breakpoint_check = sh4_tr_breakpoint_check,\n+ .translate_insn = sh4_tr_translate_insn,\n+ .tb_stop = sh4_tr_tb_stop,\n+ .disas_log = sh4_tr_disas_log,\n+ };\n+ DisasContext ctx;\n \n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)\n- && qemu_log_in_addr_range(pc_start)) {\n- qemu_log_lock();\n-\tqemu_log(\"IN:\\n\");\t/* , lookup_symbol(pc_start)); */\n- log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 0);\n-\tqemu_log(\"\\n\");\n- qemu_log_unlock();\n- }\n+#ifdef CONFIG_USER_ONLY\n+ /* We may switch the translate_insn hook in init_disas_context\n+ and within translate_insn itself. */\n+ ctx.ops = ops;\n+ translator_loop(&ctx.ops, &ctx.base, cpu, tb);\n+#else\n+ translator_loop(&ops, &ctx.base, cpu, tb);\n #endif\n }\n \n", "prefixes": [ "v2", "5/5" ] }