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GET /api/patches/811114/?format=api
{ "id": 811114, "url": "http://patchwork.ozlabs.org/api/patches/811114/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-2-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907185057.23421-2-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:50:53", "name": "[v2,1/5] target/sh4: Use cmpxchg for movco when parallel_cpus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ffa33fc98b8d0c930e3e1231337508df7c7e82f", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-2-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2042, "url": "http://patchwork.ozlabs.org/api/series/2042/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2042", "date": "2017-09-07T18:50:52", "name": "target/sh4 updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2042/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811114/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811114/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"c5c+HUTN\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp8hl24SRz9sBW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:52:39 +1000 (AEST)", "from localhost ([::1]:41769 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1un-0000sc-DT\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:52:37 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54124)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tK-00008v-Pw\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:11 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tF-0000TY-LZ\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:06 -0400", "from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:33554)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1tF-0000T1-D7\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:01 -0400", "by mail-pg0-x230.google.com with SMTP id t3so1010855pgt.0\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:51:01 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tl74sm481401pfi.9.2017.09.07.11.50.58\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:50:59 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=upScR165ou3rsrjnioluJcuDJXLGqYreYtv7+HgSjuE=;\n\tb=c5c+HUTN0SGIquPr/Xsv8fSAKe8BrmV2CkebcLzjT4CoTG5y1910SJE7kc7fMdhRdS\n\tMkMcv00VFZS/zWLFq2Rv3vbPvRVZsAJT1MQSy/9HWzemUsDJEBpVDp/GI6ORA0GBRdMH\n\twPfTXSqMB63wJbQsKC3D5IKgiuI10fK6cQMT4=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=upScR165ou3rsrjnioluJcuDJXLGqYreYtv7+HgSjuE=;\n\tb=PCe4xqtER1FRA1nil37QosZwwJZUna9Pqpa/yZJqvvP6SiBDkscLK+3M05ibi3PRnL\n\tEAiVisa4ZJzzDhBGT8Wx++/A+eT1V71VhlOVbAtq6ACNxbBLxOIF2R4HNDAywJKl1Kgz\n\tZyxDlKLO1iuRo4b8SgRTY522gBCJQk8pRP7Xqxlsy5SdbI0pJ6yIHJgWEhFQWR25iyiN\n\tAuG8buoeNoyScpXPvRAl6M+sDfKXfS3MiJ0K4vPUSMJKaLxCAcocziK9jrOdrMJO3SoF\n\tF6lggjoM2Uth1NjEnv0X6WePy5HSWPVaYwlH7I4nH/M19u/ystsiqStoG5aCC4nVer9O\n\tqIMQ==", "X-Gm-Message-State": "AHPjjUgb//E2ku0IFvOoUlZSRxh7Lz5/e+Cq28ANNvaq5h49rRlnvxyq\n\tUBCcAtwDmbVURlUpE1ny7A==", "X-Google-Smtp-Source": "ADKCNb70S1DvMlJJwALbSuWuQyJ774ZMM0QKwQXZjQi6I0FC+zxG/T764yKy0zEUdFptYBpEp9/0fA==", "X-Received": "by 10.99.42.11 with SMTP id q11mr312130pgq.7.1504810260017;\n\tThu, 07 Sep 2017 11:51:00 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:50:53 -0700", "Message-Id": "<20170907185057.23421-2-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907185057.23421-1-richard.henderson@linaro.org>", "References": "<20170907185057.23421-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::230", "Subject": "[Qemu-devel] [PATCH v2 1/5] target/sh4: Use cmpxchg for movco when\n\tparallel_cpus", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "aurelien@aurel32.net, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nAs for other targets, cmpxchg isn't quite right for ll/sc,\nsuffering from an ABA race, but is sufficient to implement\nportable atomic operations.\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n linux-user/main.c | 19 +++++++++---\n target/sh4/cpu.h | 4 ++-\n target/sh4/helper.c | 1 +\n target/sh4/translate.c | 81 ++++++++++++++++++++++++++++++++++++--------------\n 4 files changed, 78 insertions(+), 27 deletions(-)", "diff": "diff --git a/linux-user/main.c b/linux-user/main.c\nindex 03666ef657..22b3bdafc5 100644\n--- a/linux-user/main.c\n+++ b/linux-user/main.c\n@@ -2665,6 +2665,8 @@ void cpu_loop(CPUSH4State *env)\n target_siginfo_t info;\n \n while (1) {\n+ bool arch_interrupt = true;\n+\n cpu_exec_start(cs);\n trapnr = cpu_exec(cs);\n cpu_exec_end(cs);\n@@ -2696,13 +2698,14 @@ void cpu_loop(CPUSH4State *env)\n int sig;\n \n sig = gdb_handlesig(cs, TARGET_SIGTRAP);\n- if (sig)\n- {\n+ if (sig) {\n info.si_signo = sig;\n info.si_errno = 0;\n info.si_code = TARGET_TRAP_BRKPT;\n queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);\n- }\n+ } else {\n+ arch_interrupt = false;\n+ }\n }\n break;\n \tcase 0xa0:\n@@ -2713,9 +2716,9 @@ void cpu_loop(CPUSH4State *env)\n info._sifields._sigfault._addr = env->tea;\n queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);\n \t break;\n-\n case EXCP_ATOMIC:\n cpu_exec_step_atomic(cs);\n+ arch_interrupt = false;\n break;\n default:\n printf (\"Unhandled trap: 0x%x\\n\", trapnr);\n@@ -2723,6 +2726,14 @@ void cpu_loop(CPUSH4State *env)\n exit(EXIT_FAILURE);\n }\n process_pending_signals (env);\n+\n+ /* Most of the traps imply an exception or interrupt, which\n+ implies an REI instruction has been executed. Which means\n+ that LDST (aka LOK_ADDR) should be cleared. But there are\n+ a few exceptions for traps internal to QEMU. */\n+ if (arch_interrupt) {\n+ env->lock_addr = -1;\n+ }\n }\n }\n #endif\ndiff --git a/target/sh4/cpu.h b/target/sh4/cpu.h\nindex 79f85d3365..603614a2d8 100644\n--- a/target/sh4/cpu.h\n+++ b/target/sh4/cpu.h\n@@ -184,7 +184,9 @@ typedef struct CPUSH4State {\n tlb_t itlb[ITLB_SIZE];\t/* instruction translation table */\n tlb_t utlb[UTLB_SIZE];\t/* unified translation table */\n \n- uint32_t ldst;\n+ /* LDST = LOCK_ADDR != -1. */\n+ uint32_t lock_addr;\n+ uint32_t lock_value;\n \n /* Fields up to this point are cleared by a CPU reset */\n struct {} end_reset_fields;\ndiff --git a/target/sh4/helper.c b/target/sh4/helper.c\nindex 28d93c2543..680b583e53 100644\n--- a/target/sh4/helper.c\n+++ b/target/sh4/helper.c\n@@ -171,6 +171,7 @@ void superh_cpu_do_interrupt(CPUState *cs)\n env->spc = env->pc;\n env->sgr = env->gregs[15];\n env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);\n+ env->lock_addr = -1;\n \n if (env->flags & DELAY_SLOT_MASK) {\n /* Branch instruction should be executed again before delay slot. */\ndiff --git a/target/sh4/translate.c b/target/sh4/translate.c\nindex 10191073b2..4365b21624 100644\n--- a/target/sh4/translate.c\n+++ b/target/sh4/translate.c\n@@ -70,7 +70,8 @@ static TCGv cpu_gregs[32];\n static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;\n static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;\n static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;\n-static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;\n+static TCGv cpu_pr, cpu_fpscr, cpu_fpul;\n+static TCGv cpu_lock_addr, cpu_lock_value;\n static TCGv cpu_fregs[32];\n \n /* internal register indexes */\n@@ -156,8 +157,12 @@ void sh4_translate_init(void)\n offsetof(CPUSH4State,\n delayed_cond),\n \"_delayed_cond_\");\n- cpu_ldst = tcg_global_mem_new_i32(cpu_env,\n-\t\t\t\t offsetof(CPUSH4State, ldst), \"_ldst_\");\n+ cpu_lock_addr = tcg_global_mem_new_i32(cpu_env,\n+\t\t\t\t offsetof(CPUSH4State, lock_addr),\n+ \"_lock_addr_\");\n+ cpu_lock_value = tcg_global_mem_new_i32(cpu_env,\n+\t\t\t\t offsetof(CPUSH4State, lock_value),\n+ \"_lock_value_\");\n \n for (i = 0; i < 32; i++)\n cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env,\n@@ -1558,31 +1563,63 @@ static void _decode_opc(DisasContext * ctx)\n \treturn;\n case 0x0073:\n /* MOVCO.L\n-\t LDST -> T\n- If (T == 1) R0 -> (Rn)\n- 0 -> LDST\n- */\n+ * LDST -> T\n+ * If (T == 1) R0 -> (Rn)\n+ * 0 -> LDST\n+ *\n+ * The above description doesn't work in a parallel context.\n+ * Since we currently support no smp boards, this implies user-mode.\n+ * But we can still support the official mechanism while user-mode\n+ * is single-threaded. */\n CHECK_SH4A\n {\n- TCGLabel *label = gen_new_label();\n- tcg_gen_mov_i32(cpu_sr_t, cpu_ldst);\n-\t tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);\n- tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);\n-\t gen_set_label(label);\n-\t tcg_gen_movi_i32(cpu_ldst, 0);\n-\t return;\n+ TCGLabel *fail = gen_new_label();\n+ TCGLabel *done = gen_new_label();\n+\n+ if (parallel_cpus) {\n+ TCGv tmp;\n+\n+ tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), cpu_lock_addr, fail);\n+ tmp = tcg_temp_new();\n+ tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value,\n+ REG(0), ctx->memidx, MO_TEUL);\n+ tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_value);\n+ tcg_temp_free(tmp);\n+ } else {\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail);\n+ tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);\n+ tcg_gen_movi_i32(cpu_sr_t, 1);\n+ }\n+ tcg_gen_br(done);\n+\n+ gen_set_label(fail);\n+ tcg_gen_movi_i32(cpu_sr_t, 0);\n+\n+ gen_set_label(done);\n+ tcg_gen_movi_i32(cpu_lock_addr, -1);\n }\n+ return;\n case 0x0063:\n /* MOVLI.L @Rm,R0\n- 1 -> LDST\n- (Rm) -> R0\n- When interrupt/exception\n- occurred 0 -> LDST\n- */\n+ * 1 -> LDST\n+ * (Rm) -> R0\n+ * When interrupt/exception\n+ * occurred 0 -> LDST\n+ *\n+ * In a parallel context, we must also save the loaded value\n+ * for use with the cmpxchg that we'll use with movco.l. */\n CHECK_SH4A\n- tcg_gen_movi_i32(cpu_ldst, 0);\n- tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);\n- tcg_gen_movi_i32(cpu_ldst, 1);\n+ if (parallel_cpus) {\n+ TCGv tmp = tcg_temp_new();\n+ tcg_gen_mov_i32(tmp, REG(B11_8));\n+ tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);\n+ tcg_gen_mov_i32(cpu_lock_value, REG(0));\n+ tcg_gen_mov_i32(cpu_lock_addr, tmp);\n+ tcg_temp_free(tmp);\n+ } else {\n+ tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);\n+ tcg_gen_movi_i32(cpu_lock_addr, 0);\n+ }\n return;\n case 0x0093:\t\t/* ocbi @Rn */\n \t{\n", "prefixes": [ "v2", "1/5" ] }