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GET /api/patches/811113/?format=api
{ "id": 811113, "url": "http://patchwork.ozlabs.org/api/patches/811113/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-3-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907185057.23421-3-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:50:54", "name": "[v2,2/5] target/sh4: Convert to DisasJumpType", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "73af4bfbf6150f1ff7f568aa328aadd5c3f9ba73", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907185057.23421-3-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2042, "url": "http://patchwork.ozlabs.org/api/series/2042/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2042", "date": "2017-09-07T18:50:52", "name": "target/sh4 updates", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2042/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811113/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811113/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"V3j5YqkQ\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp8gq2TjTz9sBW\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:51:51 +1000 (AEST)", "from localhost ([::1]:41767 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1u1-0000GI-CA\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:51:49 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:54134)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tL-00009b-WA\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:13 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1tG-0000UY-Sv\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:08 -0400", "from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:34895)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1tG-0000Tw-KU\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:02 -0400", "by mail-pg0-x22d.google.com with SMTP id 188so996415pgb.2\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:51:02 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tl74sm481401pfi.9.2017.09.07.11.51.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:51:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=c51vYkb1GwmgGJFPbsnYbSf4DXjQs1LHm4YBN3duoa4=;\n\tb=V3j5YqkQ/q+CaZ1f2IFdzD2popOiJHoIfFJ5FxzkD36HIUiPjCZsxXRCrmq4Z27EuT\n\tjQvXX1CiVqvQlXawAv398OsF5HWHk6FuhARpG/iI6OaVaQy96yQEt80RHcBzmE+bICKn\n\tlNle/AXYh90HkiupDJ9Yrh/sxX6/G2Xj56s7I=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=c51vYkb1GwmgGJFPbsnYbSf4DXjQs1LHm4YBN3duoa4=;\n\tb=hh/J6nMIuukSPcrmIbbAtXNOfwj88XdXIv5nPOpVAiIIpITmYP513bqyp7jAO6eaPj\n\tT3ppp09e+NcHjyFxf02gOmgAisp2jxHCiMD6hOzl1Quw7bhEZZuvUzzA35+U3vOKjrFy\n\tCK7QvUk6ltliPTfBGMz2y9cbihNZ+5OW4nMETx4GwBHB0f8RIAGCKnPCFCRwsctydehh\n\t5UFC0+DQe7q1Wfm/tX6ML2zrGcC3/6rEHCz+EnthxCIPUrefNHygMvSAzMSBNeuWqIYn\n\tDCZH4VPgflUOdhRw4LbXS/n6TKfDurSiEtvRCkJrI2/EpmIfM1PF/s65enXpigNjD9aB\n\tHZFw==", "X-Gm-Message-State": "AHPjjUgIOacHZe7SjsHwYA7VNGNLB38HB1GFKef00PmGC0ZuBTUXYaD2\n\trjj/GYR9DDmMnGtURNIb6A==", "X-Google-Smtp-Source": "ADKCNb77UgRJZhNSa7CptIdGYkSuMb9fNDflJ6+N5mtnm8ONVwq4CxLk603ba3BYzt6f5kS7GexxcA==", "X-Received": "by 10.99.99.197 with SMTP id x188mr321514pgb.298.1504810261234; \n\tThu, 07 Sep 2017 11:51:01 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:50:54 -0700", "Message-Id": "<20170907185057.23421-3-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907185057.23421-1-richard.henderson@linaro.org>", "References": "<20170907185057.23421-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22d", "Subject": "[Qemu-devel] [PATCH v2 2/5] target/sh4: Convert to DisasJumpType", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "aurelien@aurel32.net, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/sh4/translate.c | 65 +++++++++++++++++++++++---------------------------\n 1 file changed, 30 insertions(+), 35 deletions(-)", "diff": "diff --git a/target/sh4/translate.c b/target/sh4/translate.c\nindex 4365b21624..6e03370871 100644\n--- a/target/sh4/translate.c\n+++ b/target/sh4/translate.c\n@@ -25,10 +25,9 @@\n #include \"exec/exec-all.h\"\n #include \"tcg-op.h\"\n #include \"exec/cpu_ldst.h\"\n-\n #include \"exec/helper-proto.h\"\n #include \"exec/helper-gen.h\"\n-\n+#include \"exec/translator.h\"\n #include \"trace-tcg.h\"\n #include \"exec/log.h\"\n \n@@ -39,7 +38,7 @@ typedef struct DisasContext {\n uint16_t opcode;\n uint32_t tbflags; /* should stay unmodified during the TB translation */\n uint32_t envflags; /* should stay in sync with env->flags using TCG ops */\n- int bstate;\n+ DisasJumpType bstate;\n int memidx;\n int gbank;\n int fbank;\n@@ -55,14 +54,10 @@ typedef struct DisasContext {\n #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))\n #endif\n \n-enum {\n- BS_NONE = 0, /* We go out of the TB without reaching a branch or an\n- * exception condition\n- */\n- BS_STOP = 1, /* We want to stop translation for any reason */\n- BS_BRANCH = 2, /* We reached a branch condition */\n- BS_EXCP = 3, /* We reached an exception condition */\n-};\n+/* Target-specific values for ctx->bstate. */\n+/* We want to exit back to the cpu loop for some reason.\n+ Usually this is to recognize interrupts immediately. */\n+#define DISAS_STOP DISAS_TARGET_0\n \n /* global register indexes */\n static TCGv_env cpu_env;\n@@ -269,6 +264,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n }\n }\n+ ctx->bstate = DISAS_NORETURN;\n }\n \n static void gen_jump(DisasContext * ctx)\n@@ -315,7 +311,7 @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,\n gen_goto_tb(ctx, 0, dest);\n gen_set_label(l1);\n gen_goto_tb(ctx, 1, ctx->pc + 2);\n- ctx->bstate = BS_BRANCH;\n+ ctx->bstate = DISAS_NORETURN;\n }\n \n /* Delayed conditional jump (bt or bf) */\n@@ -338,6 +334,7 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)\n gen_jump(ctx);\n \n gen_set_label(l1);\n+ ctx->bstate = DISAS_NEXT;\n return;\n }\n \n@@ -479,7 +476,7 @@ static void _decode_opc(DisasContext * ctx)\n \ttcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);\n ctx->envflags |= DELAY_SLOT_RTE;\n \tctx->delayed_pc = (uint32_t) - 1;\n- ctx->bstate = BS_STOP;\n+ ctx->bstate = DISAS_STOP;\n \treturn;\n case 0x0058:\t\t/* sets */\n tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));\n@@ -490,17 +487,17 @@ static void _decode_opc(DisasContext * ctx)\n case 0xfbfd:\t\t/* frchg */\n CHECK_FPSCR_PR_0\n \ttcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);\n-\tctx->bstate = BS_STOP;\n+\tctx->bstate = DISAS_STOP;\n \treturn;\n case 0xf3fd:\t\t/* fschg */\n CHECK_FPSCR_PR_0\n tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);\n-\tctx->bstate = BS_STOP;\n+\tctx->bstate = DISAS_STOP;\n \treturn;\n case 0xf7fd: /* fpchg */\n CHECK_SH4A\n tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR);\n- ctx->bstate = BS_STOP;\n+ ctx->bstate = DISAS_STOP;\n return;\n case 0x0009:\t\t/* nop */\n \treturn;\n@@ -535,7 +532,7 @@ static void _decode_opc(DisasContext * ctx)\n region (stored in R0) in the next TB. */\n if (B11_8 == 15 && B7_0s < 0 && parallel_cpus) {\n ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);\n- ctx->bstate = BS_STOP;\n+ ctx->bstate = DISAS_STOP;\n }\n #endif\n \ttcg_gen_movi_i32(REG(B11_8), B7_0s);\n@@ -1320,7 +1317,7 @@ static void _decode_opc(DisasContext * ctx)\n \t imm = tcg_const_i32(B7_0);\n gen_helper_trapa(cpu_env, imm);\n \t tcg_temp_free(imm);\n- ctx->bstate = BS_EXCP;\n+ ctx->bstate = DISAS_NORETURN;\n \t}\n \treturn;\n case 0xc800:\t\t/* tst #imm,R0 */\n@@ -1429,7 +1426,7 @@ static void _decode_opc(DisasContext * ctx)\n tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3);\n gen_write_sr(val);\n tcg_temp_free(val);\n- ctx->bstate = BS_STOP;\n+ ctx->bstate = DISAS_STOP;\n }\n \treturn;\n case 0x4007:\t\t/* ldc.l @Rm+,SR */\n@@ -1441,7 +1438,7 @@ static void _decode_opc(DisasContext * ctx)\n gen_write_sr(val);\n \t tcg_temp_free(val);\n \t tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);\n-\t ctx->bstate = BS_STOP;\n+\t ctx->bstate = DISAS_STOP;\n \t}\n \treturn;\n case 0x0002:\t\t/* stc SR,Rn */\n@@ -1503,7 +1500,7 @@ static void _decode_opc(DisasContext * ctx)\n case 0x406a:\t\t/* lds Rm,FPSCR */\n \tCHECK_FPU_ENABLED\n gen_helper_ld_fpscr(cpu_env, REG(B11_8));\n-\tctx->bstate = BS_STOP;\n+\tctx->bstate = DISAS_STOP;\n \treturn;\n case 0x4066:\t\t/* lds.l @Rm+,FPSCR */\n \tCHECK_FPU_ENABLED\n@@ -1513,7 +1510,7 @@ static void _decode_opc(DisasContext * ctx)\n \t tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);\n gen_helper_ld_fpscr(cpu_env, addr);\n \t tcg_temp_free(addr);\n-\t ctx->bstate = BS_STOP;\n+\t ctx->bstate = DISAS_STOP;\n \t}\n \treturn;\n case 0x006a:\t\t/* sts FPSCR,Rn */\n@@ -1849,7 +1846,7 @@ static void _decode_opc(DisasContext * ctx)\n gen_save_cpu_state(ctx, true);\n gen_helper_raise_illegal_instruction(cpu_env);\n }\n- ctx->bstate = BS_EXCP;\n+ ctx->bstate = DISAS_NORETURN;\n return;\n \n do_fpu_disabled:\n@@ -1859,7 +1856,7 @@ static void _decode_opc(DisasContext * ctx)\n } else {\n gen_helper_raise_fpu_disable(cpu_env);\n }\n- ctx->bstate = BS_EXCP;\n+ ctx->bstate = DISAS_NORETURN;\n return;\n }\n \n@@ -1885,7 +1882,6 @@ static void decode_opc(DisasContext * ctx)\n ctx->envflags &= ~GUSA_MASK;\n \n tcg_gen_movi_i32(cpu_flags, ctx->envflags);\n- ctx->bstate = BS_BRANCH;\n if (old_flags & DELAY_SLOT_CONDITIONAL) {\n \t gen_delayed_conditional_jump(ctx);\n } else {\n@@ -2256,7 +2252,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)\n ctx->envflags |= GUSA_EXCLUSIVE;\n gen_save_cpu_state(ctx, false);\n gen_helper_exclusive(cpu_env);\n- ctx->bstate = BS_EXCP;\n+ ctx->bstate = DISAS_NORETURN;\n \n /* We're not executing an instruction, but we must report one for the\n purposes of accounting within the TB. We might as well report the\n@@ -2279,7 +2275,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n ctx.pc = pc_start;\n ctx.tbflags = (uint32_t)tb->flags;\n ctx.envflags = tb->flags & TB_FLAG_ENVFLAGS_MASK;\n- ctx.bstate = BS_NONE;\n+ ctx.bstate = DISAS_NEXT;\n ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;\n /* We don't know if the delayed pc came from a dynamic or static branch,\n so assume it is a dynamic branch. */\n@@ -2317,7 +2313,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n }\n #endif\n \n- while (ctx.bstate == BS_NONE\n+ while (ctx.bstate == DISAS_NEXT\n && num_insns < max_insns\n && !tcg_op_buf_full()) {\n tcg_gen_insn_start(ctx.pc, ctx.envflags);\n@@ -2327,7 +2323,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n /* We have hit a breakpoint - make sure PC is up-to-date */\n gen_save_cpu_state(&ctx, true);\n gen_helper_debug(cpu_env);\n- ctx.bstate = BS_EXCP;\n+ ctx.bstate = DISAS_NORETURN;\n /* The address covered by the breakpoint must be included in\n [tb->pc, tb->pc + tb->size) in order to for it to be\n properly cleared -- thus we increment the PC here so that\n@@ -2358,19 +2354,18 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n gen_helper_debug(cpu_env);\n } else {\n \tswitch (ctx.bstate) {\n- case BS_STOP:\n+ case DISAS_STOP:\n gen_save_cpu_state(&ctx, true);\n tcg_gen_exit_tb(0);\n break;\n- case BS_NONE:\n+ case DISAS_NEXT:\n gen_save_cpu_state(&ctx, false);\n gen_goto_tb(&ctx, 0, ctx.pc);\n break;\n- case BS_EXCP:\n- /* fall through */\n- case BS_BRANCH:\n- default:\n+ case DISAS_NORETURN:\n break;\n+ default:\n+ g_assert_not_reached();\n \t}\n }\n \n", "prefixes": [ "v2", "2/5" ] }