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GET /api/patches/811099/?format=api
{ "id": 811099, "url": "http://patchwork.ozlabs.org/api/patches/811099/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-5-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907181938.3948-5-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:19:38", "name": "[PULL,4/4] target/alpha: Switch to do_transaction_failed() hook", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ee08816c2c9faac6fbc529605eb806e4356d3701", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-5-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2035, "url": "http://patchwork.ozlabs.org/api/series/2035/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2035", "date": "2017-09-07T18:19:34", "name": "[PULL,1/4] target/alpha: Convert to DisasJumpType", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2035/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811099/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811099/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"UpuvbImH\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp82H060Cz9t2R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:22:47 +1000 (AEST)", "from localhost ([::1]:41661 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1Rt-0005NT-2v\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:22:45 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41840)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1P6-0003Kr-Ol\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:59 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1P1-0007bn-NI\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:52 -0400", "from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:35517)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1P1-0007bS-G5\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:47 -0400", "by mail-pf0-x236.google.com with SMTP id g13so718624pfm.2\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:19:47 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\ts68sm412051pfd.72.2017.09.07.11.19.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:19:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=p0w2LpuRgVCzFXHPmhLKnY8BIvj5eDTupLbjXxouJWo=;\n\tb=UpuvbImH8LyU6ghQywqm4LJlEOZ+BzDiEj0sdcbDTy24L0lMdbkM+kNhJ8KSlpsHCP\n\taM4oqsTbKF7kQzhmdN614AyNu5HmvGCp9ieDWXEhc3EykqVhu0znej9164m/Oja+C+cQ\n\t/BGtAuvIcBzch5KcuQqJz+ULuA1Tsi8FH6xys=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=p0w2LpuRgVCzFXHPmhLKnY8BIvj5eDTupLbjXxouJWo=;\n\tb=tiI8tx0vVuC977yTLt0SyYE9DErTuonGCdYTGuKY0mzAQtCQs3nP2RFo6IQqVFUhus\n\tmlBlzxJLzu9lKPwxnlLOZ6/V+G8LDmxwQ0ItGP0sY0pxCXQodTHbOjy9WYiJDhvwXd7+\n\ty7wFz6v8IpMhUGFNZXr0XEU0JK9TeQKmSHC+NFfP9QGQC6ThS95C3d1iYca9jbsEPOpH\n\tP0XkjNjYWQb/RbHy0SmCfd8Ta9OYaYNIkGTTDk+ZsUAOeVMj0T5fSNoWHIjZuYLn28rH\n\tZXWm2KcQmP6KMXqh3b89dGQibQumGXXtUJ9zLxTQTf288CdTX/iugF3LKzi/q+4H6k4i\n\thBnQ==", "X-Gm-Message-State": "AHPjjUjUuPqYootd/DuBkLhyKOw8omlhphp9JQH+4lVr3mKGJwaNWuTr\n\tkLCl/6WBmYcm/UL0hFZHxg==", "X-Google-Smtp-Source": "ADKCNb70vl5LFfVSrDBjiX1FtRnYBXD/b0BTh1f+Ymp2e45xCjnbQHb3gPPVONn2UT4xcZi+ZwD3BQ==", "X-Received": "by 10.84.210.226 with SMTP id a89mr270305pli.160.1504808386323; \n\tThu, 07 Sep 2017 11:19:46 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:19:38 -0700", "Message-Id": "<20170907181938.3948-5-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907181938.3948-1-richard.henderson@linaro.org>", "References": "<20170907181938.3948-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::236", "Subject": "[Qemu-devel] [PULL 4/4] target/alpha: Switch to\n\tdo_transaction_failed() hook", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Peter Maydell <peter.maydell@linaro.org>\n\nSwitch the alpha target from the old unassigned_access hook\nto the new do_transaction_failed hook. This allows us to\nresolve a ??? in the old hook implementation.\n\nThe only part of the alpha target that does physical\nmemory accesses is reading the page table -- add a\nTODO comment there to the effect that we should handle\nbus faults on page table walks. (Since the palcode\ndoesn't actually do anything useful on a bus fault anyway\nit's a bit moot for now.)\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nMessage-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/alpha/cpu.c | 2 +-\n target/alpha/cpu.h | 8 +++++---\n target/alpha/helper.c | 8 ++++++++\n target/alpha/mem_helper.c | 19 ++++++++++---------\n 4 files changed, 24 insertions(+), 13 deletions(-)", "diff": "diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c\nindex 1ea597b9dd..e6c6aabdf0 100644\n--- a/target/alpha/cpu.c\n+++ b/target/alpha/cpu.c\n@@ -297,7 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)\n #ifdef CONFIG_USER_ONLY\n cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;\n #else\n- cc->do_unassigned_access = alpha_cpu_unassigned_access;\n+ cc->do_transaction_failed = alpha_cpu_do_transaction_failed;\n cc->do_unaligned_access = alpha_cpu_do_unaligned_access;\n cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;\n dc->vmsd = &vmstate_alpha_cpu;\ndiff --git a/target/alpha/cpu.h b/target/alpha/cpu.h\nindex 0738e97d6d..6ae240969b 100644\n--- a/target/alpha/cpu.h\n+++ b/target/alpha/cpu.h\n@@ -486,9 +486,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);\n uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);\n void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);\n #ifndef CONFIG_USER_ONLY\n-QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,\n- bool is_write, bool is_exec,\n- int unused, unsigned size);\n+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr);\n #endif\n \n static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,\ndiff --git a/target/alpha/helper.c b/target/alpha/helper.c\nindex 34121f4cad..36407f77f5 100644\n--- a/target/alpha/helper.c\n+++ b/target/alpha/helper.c\n@@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,\n \n pt = env->ptbr;\n \n+ /* TODO: rather than using ldq_phys() to read the page table we should\n+ * use address_space_ldq() so that we can handle the case when\n+ * the page table read gives a bus fault, rather than ignoring it.\n+ * For the existing code the zero data that ldq_phys will return for\n+ * an access to invalid memory will result in our treating the page\n+ * table as invalid, which may even be the right behaviour.\n+ */\n+\n /* L1 page table read. */\n index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;\n L1pte = ldq_phys(cs->as, pt + index*8);\ndiff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c\nindex 78a7d45590..3c06baa93a 100644\n--- a/target/alpha/mem_helper.c\n+++ b/target/alpha/mem_helper.c\n@@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,\n cpu_loop_exit(cs);\n }\n \n-void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,\n- bool is_write, bool is_exec, int unused,\n- unsigned size)\n+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr)\n {\n AlphaCPU *cpu = ALPHA_CPU(cs);\n CPUAlphaState *env = &cpu->env;\n \n+ if (retaddr) {\n+ cpu_restore_state(cs, retaddr);\n+ }\n+\n env->trap_arg0 = addr;\n- env->trap_arg1 = is_write ? 1 : 0;\n+ env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0;\n cs->exception_index = EXCP_MCHK;\n env->error_code = 0;\n-\n- /* ??? We should cpu_restore_state to the faulting insn, but this hook\n- does not have access to the retaddr value from the original helper.\n- It's all moot until the QEMU PALcode grows an MCHK handler. */\n-\n cpu_loop_exit(cs);\n }\n \n", "prefixes": [ "PULL", "4/4" ] }