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GET /api/patches/811097/?format=api
{ "id": 811097, "url": "http://patchwork.ozlabs.org/api/patches/811097/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-2-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170907181938.3948-2-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-07T18:19:35", "name": "[PULL,1/4] target/alpha: Convert to DisasJumpType", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6e400ea5b5024033ce3895fdec0df1bfd2ee6999", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907181938.3948-2-richard.henderson@linaro.org/mbox/", "series": [ { "id": 2035, "url": "http://patchwork.ozlabs.org/api/series/2035/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2035", "date": "2017-09-07T18:19:34", "name": "[PULL,1/4] target/alpha: Convert to DisasJumpType", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2035/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811097/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811097/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"M+2Y06aG\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp7zs4X4Vz9ryk\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 04:20:41 +1000 (AEST)", "from localhost ([::1]:41652 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dq1Pr-0003S4-IL\n\tfor incoming@patchwork.ozlabs.org; Thu, 07 Sep 2017 14:20:39 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41791)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1P2-0003IT-LV\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dq1Ox-0007ZJ-1G\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:48 -0400", "from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:37144)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dq1Ow-0007Yk-PA\n\tfor qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:19:42 -0400", "by mail-pg0-x229.google.com with SMTP id d8so854103pgt.4\n\tfor <qemu-devel@nongnu.org>; Thu, 07 Sep 2017 11:19:42 -0700 (PDT)", "from pike.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\ts68sm412051pfd.72.2017.09.07.11.19.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 07 Sep 2017 11:19:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=U8G7jLxyl2fvoViYLUQ2i9RVyDuMQWVbBH5sbJtd/IU=;\n\tb=M+2Y06aG+zPRTd2Ca7H8mLcR8oIi/Fx3oM/mCx/OPmkPLHPMSuImh+yEpiraPa/YEr\n\t4uzPHJtOkOJoKVmKIjGeRQvLB7YEZbr0QbNz+UnozkYZ1dlO+WM/gMtREsjb0UXFVv7q\n\tS5j1SYCFGYB5wgb0NEChE+8XMZcW1HBdpZ1uU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=U8G7jLxyl2fvoViYLUQ2i9RVyDuMQWVbBH5sbJtd/IU=;\n\tb=gOTLxCRoPBKolWl7qsM+LqjNSfTw+MiCDGH0LSEVvUxHJAm6yg7NaqiaanSXjNP3hV\n\t3bV2oEe8ZgtB0DC7G6z9OD6ACpGxkiVw9+4U02Sa7ewzHnF3FoJwCQEKwWGc8Iwa1yZZ\n\tM+1j7+tu/lysJE11Ag9lqZsb6ZIqbCv7eVqOh3OnOzgYx+bwI73jvGiC2H60ptF0mHip\n\t+cXRWg3LCPt8ljFOOk2ucFe/X4NmTFIc6fXb+OAgwzBf6/J15zDU8wt10fn+BjZo01Hv\n\tt/p9pcK0umn/+O+p5k7GuPsRPrlr35j9Xgc6RUNjnrK5g3uX+PA7hGI5SJh9mwlmcveM\n\tFZ1w==", "X-Gm-Message-State": "AHPjjUixJGR/RdL/+5CtwPh/j1FGmxNBrUcD7JbpTZf1xipXDpWRZsWj\n\tnKux+xaudtbw3T3d7JjZAw==", "X-Google-Smtp-Source": "ADKCNb6FEF6AAWGG/eBy3uKjOFYA+RDuQsvHhc8vteQylc1i/kucUo9rC+AE1AhjU6xXOJzx3HMJ4g==", "X-Received": "by 10.99.4.8 with SMTP id 8mr216134pge.123.1504808381470;\n\tThu, 07 Sep 2017 11:19:41 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Thu, 7 Sep 2017 11:19:35 -0700", "Message-Id": "<20170907181938.3948-2-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170907181938.3948-1-richard.henderson@linaro.org>", "References": "<20170907181938.3948-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::229", "Subject": "[Qemu-devel] [PULL 1/4] target/alpha: Convert to DisasJumpType", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/alpha/translate.c | 132 ++++++++++++++++++++---------------------------\n 1 file changed, 55 insertions(+), 77 deletions(-)", "diff": "diff --git a/target/alpha/translate.c b/target/alpha/translate.c\nindex f465752208..a75bf5dd90 100644\n--- a/target/alpha/translate.c\n+++ b/target/alpha/translate.c\n@@ -25,11 +25,10 @@\n #include \"exec/exec-all.h\"\n #include \"tcg-op.h\"\n #include \"exec/cpu_ldst.h\"\n-\n #include \"exec/helper-proto.h\"\n #include \"exec/helper-gen.h\"\n-\n #include \"trace-tcg.h\"\n+#include \"exec/translator.h\"\n #include \"exec/log.h\"\n \n \n@@ -73,32 +72,12 @@ struct DisasContext {\n bool singlestep_enabled;\n };\n \n-/* Return values from translate_one, indicating the state of the TB.\n- Note that zero indicates that we are not exiting the TB. */\n-\n-typedef enum {\n- NO_EXIT,\n-\n- /* We have emitted one or more goto_tb. No fixup required. */\n- EXIT_GOTO_TB,\n-\n- /* We are not using a goto_tb (for whatever reason), but have updated\n- the PC (for whatever reason), so there's no need to do it again on\n- exiting the TB. */\n- EXIT_PC_UPDATED,\n- EXIT_PC_UPDATED_NOCHAIN,\n-\n- /* We are exiting the TB, but have neither emitted a goto_tb, nor\n- updated the PC for the next instruction to be executed. */\n- EXIT_PC_STALE,\n-\n- /* We are exiting the TB due to page crossing or space constraints. */\n- EXIT_FALLTHRU,\n-\n- /* We are ending the TB with a noreturn function call, e.g. longjmp.\n- No following code will be executed. */\n- EXIT_NORETURN,\n-} ExitStatus;\n+/* Target-specific return values from translate_one, indicating the\n+ state of the TB. Note that DISAS_NEXT indicates that we are not\n+ exiting the TB. */\n+#define DISAS_PC_UPDATED_NOCHAIN DISAS_TARGET_0\n+#define DISAS_PC_UPDATED DISAS_TARGET_1\n+#define DISAS_PC_STALE DISAS_TARGET_2\n \n /* global register indexes */\n static TCGv_env cpu_env;\n@@ -301,14 +280,14 @@ static void gen_excp_1(int exception, int error_code)\n tcg_temp_free_i32(tmp1);\n }\n \n-static ExitStatus gen_excp(DisasContext *ctx, int exception, int error_code)\n+static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code)\n {\n tcg_gen_movi_i64(cpu_pc, ctx->pc);\n gen_excp_1(exception, error_code);\n- return EXIT_NORETURN;\n+ return DISAS_NORETURN;\n }\n \n-static inline ExitStatus gen_invalid(DisasContext *ctx)\n+static inline DisasJumpType gen_invalid(DisasContext *ctx)\n {\n return gen_excp(ctx, EXCP_OPCDEC, 0);\n }\n@@ -434,9 +413,9 @@ static inline void gen_store_mem(DisasContext *ctx,\n tcg_temp_free(tmp);\n }\n \n-static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb,\n- int32_t disp16, int mem_idx,\n- TCGMemOp op)\n+static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,\n+ int32_t disp16, int mem_idx,\n+ TCGMemOp op)\n {\n TCGLabel *lab_fail, *lab_done;\n TCGv addr, val;\n@@ -468,7 +447,7 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb,\n \n gen_set_label(lab_done);\n tcg_gen_movi_i64(cpu_lock_addr, -1);\n- return NO_EXIT;\n+ return DISAS_NEXT;\n }\n \n static bool in_superpage(DisasContext *ctx, int64_t addr)\n@@ -507,7 +486,7 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest)\n #endif\n }\n \n-static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n+static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n {\n uint64_t dest = ctx->pc + (disp << 2);\n \n@@ -522,15 +501,15 @@ static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp)\n tcg_gen_goto_tb(0);\n tcg_gen_movi_i64(cpu_pc, dest);\n tcg_gen_exit_tb((uintptr_t)ctx->tb);\n- return EXIT_GOTO_TB;\n+ return DISAS_NORETURN;\n } else {\n tcg_gen_movi_i64(cpu_pc, dest);\n- return EXIT_PC_UPDATED;\n+ return DISAS_PC_UPDATED;\n }\n }\n \n-static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond,\n- TCGv cmp, int32_t disp)\n+static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond,\n+ TCGv cmp, int32_t disp)\n {\n uint64_t dest = ctx->pc + (disp << 2);\n TCGLabel *lab_true = gen_new_label();\n@@ -547,7 +526,7 @@ static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond,\n tcg_gen_movi_i64(cpu_pc, dest);\n tcg_gen_exit_tb((uintptr_t)ctx->tb + 1);\n \n- return EXIT_GOTO_TB;\n+ return DISAS_NORETURN;\n } else {\n TCGv_i64 z = tcg_const_i64(0);\n TCGv_i64 d = tcg_const_i64(dest);\n@@ -558,16 +537,16 @@ static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond,\n tcg_temp_free_i64(z);\n tcg_temp_free_i64(d);\n tcg_temp_free_i64(p);\n- return EXIT_PC_UPDATED;\n+ return DISAS_PC_UPDATED;\n }\n }\n \n-static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra,\n- int32_t disp, int mask)\n+static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra,\n+ int32_t disp, int mask)\n {\n if (mask) {\n TCGv tmp = tcg_temp_new();\n- ExitStatus ret;\n+ DisasJumpType ret;\n \n tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1);\n ret = gen_bcond_internal(ctx, cond, tmp, disp);\n@@ -609,11 +588,11 @@ static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src)\n }\n }\n \n-static ExitStatus gen_fbcond(DisasContext *ctx, TCGCond cond, int ra,\n- int32_t disp)\n+static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra,\n+ int32_t disp)\n {\n TCGv cmp_tmp = tcg_temp_new();\n- ExitStatus ret;\n+ DisasJumpType ret;\n \n gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra));\n ret = gen_bcond_internal(ctx, cond, cmp_tmp, disp);\n@@ -1159,7 +1138,7 @@ static void gen_rx(DisasContext *ctx, int ra, int set)\n tcg_temp_free(tmp);\n }\n \n-static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)\n+static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)\n {\n /* We're emulating OSF/1 PALcode. Many of these are trivial access\n to internal cpu registers. */\n@@ -1185,7 +1164,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)\n palcode &= 0xbf;\n goto do_call_pal;\n }\n- return NO_EXIT;\n+ return DISAS_NEXT;\n }\n \n #ifndef CONFIG_USER_ONLY\n@@ -1232,7 +1211,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)\n \n /* Allow interrupts to be recognized right away. */\n tcg_gen_movi_i64(cpu_pc, ctx->pc);\n- return EXIT_PC_UPDATED_NOCHAIN;\n+ return DISAS_PC_UPDATED_NOCHAIN;\n \n case 0x36:\n /* RDPS */\n@@ -1270,7 +1249,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)\n palcode &= 0x3f;\n goto do_call_pal;\n }\n- return NO_EXIT;\n+ return DISAS_NEXT;\n }\n #endif\n return gen_invalid(ctx);\n@@ -1307,10 +1286,10 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)\n tcg_gen_goto_tb(0);\n tcg_gen_movi_i64(cpu_pc, entry);\n tcg_gen_exit_tb((uintptr_t)ctx->tb);\n- return EXIT_GOTO_TB;\n+ return DISAS_NORETURN;\n } else {\n tcg_gen_movi_i64(cpu_pc, entry);\n- return EXIT_PC_UPDATED;\n+ return DISAS_PC_UPDATED;\n }\n }\n #endif\n@@ -1344,7 +1323,7 @@ static int cpu_pr_data(int pr)\n return 0;\n }\n \n-static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)\n+static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno)\n {\n void (*helper)(TCGv);\n int data;\n@@ -1366,7 +1345,7 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)\n gen_io_start();\n helper(va);\n gen_io_end();\n- return EXIT_PC_STALE;\n+ return DISAS_PC_STALE;\n } else {\n helper(va);\n }\n@@ -1393,10 +1372,10 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno)\n break;\n }\n \n- return NO_EXIT;\n+ return DISAS_NEXT;\n }\n \n-static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n+static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n {\n int data;\n \n@@ -1424,7 +1403,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n case 252:\n /* HALT */\n gen_helper_halt(vb);\n- return EXIT_PC_STALE;\n+ return DISAS_PC_STALE;\n \n case 251:\n /* ALARM */\n@@ -1438,7 +1417,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n that ended with a CALL_PAL. Since the base register usually only\n changes during boot, flushing everything works well. */\n gen_helper_tb_flush(cpu_env);\n- return EXIT_PC_STALE;\n+ return DISAS_PC_STALE;\n \n case 32 ... 39:\n /* Accessing the \"non-shadow\" general registers. */\n@@ -1467,7 +1446,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n break;\n }\n \n- return NO_EXIT;\n+ return DISAS_NEXT;\n }\n #endif /* !USER_ONLY*/\n \n@@ -1499,7 +1478,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)\n } \\\n } while (0)\n \n-static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n+static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)\n {\n int32_t disp21, disp16, disp12 __attribute__((unused));\n uint16_t fn11;\n@@ -1507,7 +1486,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n bool islit, real_islit;\n TCGv va, vb, vc, tmp, tmp2;\n TCGv_i32 t32;\n- ExitStatus ret;\n+ DisasJumpType ret;\n \n /* Decode all instruction fields */\n opc = extract32(insn, 26, 6);\n@@ -1530,7 +1509,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n lit = 0;\n }\n \n- ret = NO_EXIT;\n+ ret = DISAS_NEXT;\n switch (opc) {\n case 0x00:\n /* CALL_PAL */\n@@ -2432,7 +2411,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n gen_io_start();\n gen_helper_load_pcc(va, cpu_env);\n gen_io_end();\n- ret = EXIT_PC_STALE;\n+ ret = DISAS_PC_STALE;\n } else {\n gen_helper_load_pcc(va, cpu_env);\n }\n@@ -2480,7 +2459,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n if (ra != 31) {\n tcg_gen_movi_i64(ctx->ir[ra], ctx->pc);\n }\n- ret = EXIT_PC_UPDATED;\n+ ret = DISAS_PC_UPDATED;\n break;\n \n case 0x1B:\n@@ -2738,7 +2717,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)\n tcg_temp_free(tmp);\n tcg_gen_andi_i64(cpu_pc, vb, ~3);\n /* Allow interrupts to be recognized right away. */\n- ret = EXIT_PC_UPDATED_NOCHAIN;\n+ ret = DISAS_PC_UPDATED_NOCHAIN;\n break;\n #else\n goto invalid_opc;\n@@ -2959,7 +2938,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n target_ulong pc_start;\n target_ulong pc_mask;\n uint32_t insn;\n- ExitStatus ret;\n+ DisasJumpType ret;\n int num_insns;\n int max_insns;\n \n@@ -3040,41 +3019,40 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)\n \n /* If we reach a page boundary, are single stepping,\n or exhaust instruction count, stop generation. */\n- if (ret == NO_EXIT\n+ if (ret == DISAS_NEXT\n && ((ctx.pc & pc_mask) == 0\n || tcg_op_buf_full()\n || num_insns >= max_insns\n || singlestep\n || ctx.singlestep_enabled)) {\n- ret = EXIT_FALLTHRU;\n+ ret = DISAS_TOO_MANY;\n }\n- } while (ret == NO_EXIT);\n+ } while (ret == DISAS_NEXT);\n \n if (tb->cflags & CF_LAST_IO) {\n gen_io_end();\n }\n \n switch (ret) {\n- case EXIT_GOTO_TB:\n- case EXIT_NORETURN:\n+ case DISAS_NORETURN:\n break;\n- case EXIT_FALLTHRU:\n+ case DISAS_TOO_MANY:\n if (use_goto_tb(&ctx, ctx.pc)) {\n tcg_gen_goto_tb(0);\n tcg_gen_movi_i64(cpu_pc, ctx.pc);\n tcg_gen_exit_tb((uintptr_t)ctx.tb);\n }\n /* FALLTHRU */\n- case EXIT_PC_STALE:\n+ case DISAS_PC_STALE:\n tcg_gen_movi_i64(cpu_pc, ctx.pc);\n /* FALLTHRU */\n- case EXIT_PC_UPDATED:\n+ case DISAS_PC_UPDATED:\n if (!use_exit_tb(&ctx)) {\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n break;\n }\n /* FALLTHRU */\n- case EXIT_PC_UPDATED_NOCHAIN:\n+ case DISAS_PC_UPDATED_NOCHAIN:\n if (ctx.singlestep_enabled) {\n gen_excp_1(EXCP_DEBUG, 0);\n } else {\n", "prefixes": [ "PULL", "1/4" ] }