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GET /api/patches/811076/?format=api
{ "id": 811076, "url": "http://patchwork.ozlabs.org/api/patches/811076/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1504798409-32041-3-git-send-email-timur@codeaurora.org/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504798409-32041-3-git-send-email-timur@codeaurora.org>", "list_archive_url": null, "date": "2017-09-07T15:33:29", "name": "[2/2,v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "98fee9b4599e294e04f2e6b96e020f91e1940c62", "submitter": { "id": 66858, "url": "http://patchwork.ozlabs.org/api/people/66858/?format=api", "name": "Timur Tabi", "email": "timur@codeaurora.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1504798409-32041-3-git-send-email-timur@codeaurora.org/mbox/", "series": [ { "id": 2018, "url": "http://patchwork.ozlabs.org/api/series/2018/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=2018", "date": "2017-09-07T15:33:27", "name": "pinctrl: qcom: add support for sparse GPIOs", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/2018/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811076/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811076/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Aucglv+f\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Gc2LI9Dz\"; dkim-atps=neutral", "pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org", "pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xp4HQ1bvrz9t2r\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 01:33:54 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754918AbdIGPdx (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 7 Sep 2017 11:33:53 -0400", "from smtp.codeaurora.org ([198.145.29.96]:47412 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752200AbdIGPdw (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 7 Sep 2017 11:33:52 -0400", "by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid ADFB4611AE; Thu, 7 Sep 2017 15:33:51 +0000 (UTC)", "from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com\n\t[199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 44C5460D5C;\n\tThu, 7 Sep 2017 15:33:49 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1504798432;\n\tbh=h2bUshz/RlnNVyv/v37wwDYXso+VV7sx6/HCMkvOY8M=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Aucglv+fh6Vab1AAF6Vvy0bkAqRC8FCFjw2RbexPHvPEq06ylQL/Nnvb7vmzxUv7/\n\tkAWyWwSsM4DL7EgEMczmrmENCu2WJQSn6OThcZ9xPGlIf3dLEkW0s3j5ehUyVQt9nD\n\tL8wzUw1rCXowSZIlVcZzR4dXEHfnU1n+Oa6FuzIc=", "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1504798430;\n\tbh=h2bUshz/RlnNVyv/v37wwDYXso+VV7sx6/HCMkvOY8M=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Gc2LI9DzgJqBxei77V2M7uWynmG69rO3yX0+fMiM5pdI/hpC3IRGx0LAEBOR+/KcN\n\t4iOdTMVSUdvdfFPZNnhPG281vzFDtSF07zmNpGGRPZFC3Dt6/+Lx1cU4tVm4B3Doyg\n\tQLKBh1W9Efo01NPPtqUSUVgfPd1/ktR8XL6Dqu6s=" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0", "DMARC-Filter": "OpenDMARC Filter v1.3.2 smtp.codeaurora.org 44C5460D5C", "From": "Timur Tabi <timur@codeaurora.org>", "To": "Linus Walleij <linus.walleij@linaro.org>, andy.gross@linaro.org,\n\tdavid.brown@linaro.org, anjiandi@codeaurora.org,\n\tBjorn Andersson <bjorn.andersson@linaro.org>,\n\tlinux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-arm-msm@vger.kernel.org", "Cc": "timur@codeaurora.org", "Subject": "[PATCH 2/2] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI\n\tHID QCOM8002", "Date": "Thu, 7 Sep 2017 10:33:29 -0500", "Message-Id": "<1504798409-32041-3-git-send-email-timur@codeaurora.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1504798409-32041-1-git-send-email-timur@codeaurora.org>", "References": "<1504798409-32041-1-git-send-email-timur@codeaurora.org>", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Newer versions of the firmware for the Qualcomm Datacenter Technologies\nQDF2400 restricts access to a subset of the GPIOs on the TLMM. To\nprevent older kernels from accidentally accessing the restricted GPIOs,\nwe change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,\nand introduce a new property \"gpios\". This property is an array of\nspecific GPIOs that are accessible. When an older kernel boots on\nnewer (restricted) firmware, it will fail to probe.\n\nTo implement the sparse GPIO map, we register all of the GPIOs, but set\nthe pin count for the unavailable GPIOs to zero. The pinctrl-msm\ndriver will block those unavailable GPIOs from being accessed.\n\nTo allow newer kernels to support older firmware, the driver retains\nsupport for QCOM8001.\n\nSigned-off-by: Timur Tabi <timur@codeaurora.org>\n---\n drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 145 +++++++++++++++++++++++++--------\n 1 file changed, 109 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c\nindex bb3ce5c3e18b..37f746f6eb8c 100644\n--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c\n+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c\n@@ -38,68 +38,147 @@\n /* maximum size of each gpio name (enough room for \"gpioXXX\" + null) */\n #define NAME_SIZE\t8\n \n+enum {\n+\tQDF2XXX_V1,\n+\tQDF2XXX_V2,\n+};\n+\n+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {\n+\t{\"QCOM8001\", QDF2XXX_V1},\n+\t{\"QCOM8002\", QDF2XXX_V2},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);\n+\n static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)\n {\n+\tconst struct acpi_device_id *id =\n+\t\tacpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);\n \tstruct pinctrl_pin_desc *pins;\n \tstruct msm_pingroup *groups;\n \tchar (*names)[NAME_SIZE];\n \tunsigned int i;\n \tu32 num_gpios;\n+\tunsigned int avail_gpios; /* The number of GPIOs we support */\n+\tu16 *gpios; /* An array of supported GPIOs */\n \tint ret;\n \n \t/* Query the number of GPIOs from ACPI */\n \tret = device_property_read_u32(&pdev->dev, \"num-gpios\", &num_gpios);\n \tif (ret < 0) {\n-\t\tdev_warn(&pdev->dev, \"missing num-gpios property\\n\");\n+\t\tdev_err(&pdev->dev, \"missing 'num-gpios' property\\n\");\n \t\treturn ret;\n \t}\n-\n \tif (!num_gpios || num_gpios > MAX_GPIOS) {\n-\t\tdev_warn(&pdev->dev, \"invalid num-gpios property\\n\");\n+\t\tdev_err(&pdev->dev, \"invalid 'num-gpios' property\\n\");\n \t\treturn -ENODEV;\n \t}\n \n+\t/*\n+\t * The QCOM8001 HID contains only the number of GPIOs, and assumes\n+\t * that all of them are available. avail_gpios is the same as num_gpios.\n+\t *\n+\t * The QCOM8002 HID introduces the 'gpios' DSD, which lists\n+\t * specific GPIOs that the driver is allowed to access.\n+\t *\n+\t * The make the common code simpler, in both cases we create an\n+\t * array of GPIOs that are accessible. So for QCOM8001, that would\n+\t * be all of the GPIOs.\n+\t */\n+\tif (id->driver_data == QDF2XXX_V1) {\n+\t\tavail_gpios = num_gpios;\n+\n+\t\tgpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),\n+\t\t\t\t GFP_KERNEL);\n+\t\tif (!gpios)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tfor (i = 0; i < avail_gpios; i++)\n+\t\t\tgpios[i] = i;\n+\t} else {\n+\t\t/* The number of GPIOs in the approved list */\n+\t\tret = device_property_read_u16_array(&pdev->dev, \"gpios\",\n+\t\t\t\t\t\t NULL, 0);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&pdev->dev, \"missing 'num-gpios' property\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tif (!ret || ret > MAX_GPIOS) {\n+\t\t\tdev_err(&pdev->dev, \"invalid 'num-gpios' property\\n\");\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\t\tavail_gpios = ret;\n+\n+\t\tgpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),\n+\t\t\t\t GFP_KERNEL);\n+\t\tif (!gpios)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tret = device_property_read_u16_array(&pdev->dev, \"gpios\", gpios,\n+\t\t\t\t\t\t avail_gpios);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&pdev->dev, \"could not read list of GPIOs\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Because we have a specific list of GPIOs, the GPIO map\n+\t\t * is 'sparse'.\n+\t\t */\n+\t\tqdf2xxx_pinctrl.sparse = true;\n+\t}\n+\n \tpins = devm_kcalloc(&pdev->dev, num_gpios,\n \t\tsizeof(struct pinctrl_pin_desc), GFP_KERNEL);\n \tgroups = devm_kcalloc(&pdev->dev, num_gpios,\n \t\tsizeof(struct msm_pingroup), GFP_KERNEL);\n-\tnames = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);\n+\tnames = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);\n \n \tif (!pins || !groups || !names)\n \t\treturn -ENOMEM;\n \n+\t/*\n+\t * Initialize the array. GPIOs not listed in the 'gpios' array\n+\t * still need a number, but nothing else.\n+\t */\n \tfor (i = 0; i < num_gpios; i++) {\n-\t\tsnprintf(names[i], NAME_SIZE, \"gpio%u\", i);\n-\n \t\tpins[i].number = i;\n-\t\tpins[i].name = names[i];\n-\n-\t\tgroups[i].npins = 1;\n-\t\tgroups[i].name = names[i];\n \t\tgroups[i].pins = &pins[i].number;\n+\t}\n \n-\t\tgroups[i].ctl_reg = 0x10000 * i;\n-\t\tgroups[i].io_reg = 0x04 + 0x10000 * i;\n-\t\tgroups[i].intr_cfg_reg = 0x08 + 0x10000 * i;\n-\t\tgroups[i].intr_status_reg = 0x0c + 0x10000 * i;\n-\t\tgroups[i].intr_target_reg = 0x08 + 0x10000 * i;\n-\n-\t\tgroups[i].mux_bit = 2;\n-\t\tgroups[i].pull_bit = 0;\n-\t\tgroups[i].drv_bit = 6;\n-\t\tgroups[i].oe_bit = 9;\n-\t\tgroups[i].in_bit = 0;\n-\t\tgroups[i].out_bit = 1;\n-\t\tgroups[i].intr_enable_bit = 0;\n-\t\tgroups[i].intr_status_bit = 0;\n-\t\tgroups[i].intr_target_bit = 5;\n-\t\tgroups[i].intr_target_kpss_val = 1;\n-\t\tgroups[i].intr_raw_status_bit = 4;\n-\t\tgroups[i].intr_polarity_bit = 1;\n-\t\tgroups[i].intr_detection_bit = 2;\n-\t\tgroups[i].intr_detection_width = 2;\n+\t/* Populate the entries that are meant to be exposes as GPIOs. */\n+\tfor (i = 0; i < avail_gpios; i++) {\n+\t\tunsigned int gpio = gpios[i];\n+\n+\t\tgroups[gpio].npins = 1;\n+\t\tsnprintf(names[i], NAME_SIZE, \"gpio%u\", gpio);\n+\t\tpins[gpio].name = names[i];\n+\t\tgroups[gpio].name = names[i];\n+\n+\t\tgroups[gpio].ctl_reg = 0x10000 * gpio;\n+\t\tgroups[gpio].io_reg = 0x04 + 0x10000 * gpio;\n+\t\tgroups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;\n+\t\tgroups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;\n+\t\tgroups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;\n+\n+\t\tgroups[gpio].mux_bit = 2;\n+\t\tgroups[gpio].pull_bit = 0;\n+\t\tgroups[gpio].drv_bit = 6;\n+\t\tgroups[gpio].oe_bit = 9;\n+\t\tgroups[gpio].in_bit = 0;\n+\t\tgroups[gpio].out_bit = 1;\n+\t\tgroups[gpio].intr_enable_bit = 0;\n+\t\tgroups[gpio].intr_status_bit = 0;\n+\t\tgroups[gpio].intr_target_bit = 5;\n+\t\tgroups[gpio].intr_target_kpss_val = 1;\n+\t\tgroups[gpio].intr_raw_status_bit = 4;\n+\t\tgroups[gpio].intr_polarity_bit = 1;\n+\t\tgroups[gpio].intr_detection_bit = 2;\n+\t\tgroups[gpio].intr_detection_width = 2;\n \t}\n \n+\tdevm_kfree(&pdev->dev, gpios);\n+\n \tqdf2xxx_pinctrl.pins = pins;\n \tqdf2xxx_pinctrl.groups = groups;\n \tqdf2xxx_pinctrl.npins = num_gpios;\n@@ -109,12 +188,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)\n \treturn msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);\n }\n \n-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {\n-\t{\"QCOM8001\"},\n-\t{},\n-};\n-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);\n-\n static struct platform_driver qdf2xxx_pinctrl_driver = {\n \t.driver = {\n \t\t.name = \"qdf2xxx-pinctrl\",\n", "prefixes": [ "2/2", "v3" ] }