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GET /api/patches/811063/?format=api
{ "id": 811063, "url": "http://patchwork.ozlabs.org/api/patches/811063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-5-npiggin@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170907145148.24398-5-npiggin@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170907145148.24398-5-npiggin@gmail.com/", "date": "2017-09-07T14:51:44", "name": "[RFC,4/8] powerpc/64s/radix: Implement _tlbie(l)_va_range flush functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a40c8749eb08a3c57796046bf0351afa9f11c18a", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-5-npiggin@gmail.com/mbox/", "series": [ { "id": 2010, "url": "http://patchwork.ozlabs.org/api/series/2010/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2010", "date": "2017-09-07T14:51:40", "name": "Further radix TLB flush optimisations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2010/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811063/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811063/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp3Yt39qZz9s81\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 8 Sep 2017 01:01:22 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xp3Yt22LMzDrWY\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 8 Sep 2017 01:01:22 +1000 (AEST)", "from mail-pg0-x244.google.com (mail-pg0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c05::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xp3Mc5STtzDrXs\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 8 Sep 2017 00:52:28 +1000 (AEST)", "by mail-pg0-x244.google.com with SMTP id m9so5058072pgd.0\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 07 Sep 2017 07:52:28 -0700 (PDT)", "from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202])\n\tby smtp.gmail.com with ESMTPSA id\n\ta6sm4642791pfa.76.2017.09.07.07.52.23\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 07 Sep 2017 07:52:25 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LmzE0vMq\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LmzE0vMq\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LmzE0vMq\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=aCLrXLAokfH0FfTlXyiOfylUgTFq5cU4rg+EtS7+X+E=;\n\tb=LmzE0vMqaFiJuey7gskzAnk89CCqrF4s93MTQhQvatqzfWVx0rks7Jk452Njz5doKU\n\tGTODCaHN15lIBd9uGNvxmCak4lrwJlioDhmlRtcGqHpI6ypm4ByOtfA7UvkhMk0D9jDs\n\tdq4ny6OZYkG5PnpuKhAS8pbZ1m3/FlJ4Z/c4bzP/s7420gHGV4Nm85TlDaXQILaEN8zc\n\t2MER0JUWNzGI3qrVOq/VtoUjPiISBQyu6a+WMXTIgnRARhJfGkJsNahEQHjGGYXmHjwq\n\tOCiTiUwlZTkgCDKL6OMXn3q6JDEGYZs3603BviRaB7ar6eRwMiA3Kvw0CQDvZTTFBGCz\n\tAQIw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=aCLrXLAokfH0FfTlXyiOfylUgTFq5cU4rg+EtS7+X+E=;\n\tb=cU7dZb907TLJcP6oyMtKnam1DoEsDZvVBy1DcwTMf3xChRHfvV1AxXQOFWLOHW53WU\n\tV5hFSqkQjukDSpisCCwDpGXLFHxHqdObvLZtcH3S7xg5M4005SgSEQcH2+w0Nc5T9kWJ\n\tPonUq2n8pTTTNm2DMz0Wc5N2rOg32GZRFN3flRPVWBPd2G9WVMxj9UgNC/RsBUpNXorl\n\tgIrDHoNyVOxwoi76LhsklCYtKHa7GooBf+GEp69xOnAQzS0X/13Mzynhaf5lo4IHt9zU\n\tEEGD4p5+2g4im79cA2dJ462Rn/SCJCvy+aPyOKU2tRhORkFqJu12Ls/NtuZJpMPIUEVM\n\tcnPg==", "X-Gm-Message-State": "AHPjjUhUUxNhLzacFs/Xxefov2LVLnZk83k//pzrwZTzVzBnm0XT57In\n\tkuq56uSlPZ1aC2sE", "X-Google-Smtp-Source": "ADKCNb6YYiOX7Jr73SAW3BwI25+ebUrDuHlloHEO+ldZBj2ov5XfuA2hBUoxZ2qJKNkP8Krx4+Y/gQ==", "X-Received": "by 10.84.211.100 with SMTP id b91mr3410603pli.126.1504795946812; \n\tThu, 07 Sep 2017 07:52:26 -0700 (PDT)", "From": "Nicholas Piggin <npiggin@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[RFC PATCH 4/8] powerpc/64s/radix: Implement _tlbie(l)_va_range\n\tflush functions", "Date": "Fri, 8 Sep 2017 00:51:44 +1000", "Message-Id": "<20170907145148.24398-5-npiggin@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170907145148.24398-1-npiggin@gmail.com>", "References": "<20170907145148.24398-1-npiggin@gmail.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "\"Aneesh Kumar K . V\" <aneesh.kumar@linux.vnet.ibm.com>,\n\tNicholas Piggin <npiggin@gmail.com>, Anton Blanchard <anton@samba.org>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Move the barriers and range iteration down into the _tlbie* level,\nwhich improves readability.\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\n---\n arch/powerpc/mm/tlb-radix.c | 70 ++++++++++++++++++++++++++-------------------\n 1 file changed, 40 insertions(+), 30 deletions(-)", "diff": "diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c\nindex c30f3faf5356..1d3cbc01596d 100644\n--- a/arch/powerpc/mm/tlb-radix.c\n+++ b/arch/powerpc/mm/tlb-radix.c\n@@ -85,7 +85,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)\n }\n \n static inline void __tlbiel_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long ap, unsigned long ric)\n {\n \tunsigned long rb,rs,prs,r;\n \n@@ -101,13 +101,28 @@ static inline void __tlbiel_va(unsigned long va, unsigned long pid,\n }\n \n static inline void _tlbiel_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long psize, unsigned long ric)\n {\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n \tasm volatile(\"ptesync\": : :\"memory\");\n \t__tlbiel_va(va, pid, ap, ric);\n \tasm volatile(\"ptesync\": : :\"memory\");\n }\n \n+static inline void _tlbiel_va_range(unsigned long start, unsigned long end,\n+\t\t\t\t unsigned long pid, unsigned long page_size,\n+\t\t\t\t unsigned long psize)\n+{\n+\tunsigned long addr;\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+\tfor (addr = start; addr < end; addr += page_size)\n+\t\t__tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+}\n+\n static inline void __tlbie_va(unsigned long va, unsigned long pid,\n \t\t\t unsigned long ap, unsigned long ric)\n {\n@@ -125,13 +140,27 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid,\n }\n \n static inline void _tlbie_va(unsigned long va, unsigned long pid,\n-\t\t\t unsigned long ap, unsigned long ric)\n+\t\t\t unsigned long psize, unsigned long ric)\n {\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n \tasm volatile(\"ptesync\": : :\"memory\");\n \t__tlbie_va(va, pid, ap, ric);\n \tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n }\n \n+static inline void _tlbie_va_range(unsigned long start, unsigned long end,\n+\t\t\t\t unsigned long pid, unsigned long page_size,\n+\t\t\t\t unsigned long psize)\n+{\n+\tunsigned long addr;\n+\tunsigned long ap = mmu_get_ap(psize);\n+\n+\tasm volatile(\"ptesync\": : :\"memory\");\n+\tfor (addr = start; addr < end; addr += page_size)\n+\t\t__tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n+\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+}\n \n /*\n * Base TLB flushing operations:\n@@ -173,12 +202,11 @@ void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmadd\n \t\t\t\t int psize)\n {\n \tunsigned long pid;\n-\tunsigned long ap = mmu_get_ap(psize);\n \n \tpreempt_disable();\n \tpid = mm ? mm->context.id : 0;\n \tif (pid != MMU_NO_CONTEXT)\n-\t\t_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \tpreempt_enable();\n }\n \n@@ -238,16 +266,15 @@ void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,\n \t\t\t\t int psize)\n {\n \tunsigned long pid;\n-\tunsigned long ap = mmu_get_ap(psize);\n \n \tpid = mm ? mm->context.id : 0;\n \tif (unlikely(pid == MMU_NO_CONTEXT))\n \t\treturn;\n \tpreempt_disable();\n \tif (!mm_is_thread_local(mm))\n-\t\t_tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbie_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \telse\n-\t\t_tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);\n+\t\t_tlbiel_va(vmaddr, pid, psize, RIC_FLUSH_TLB);\n \tpreempt_enable();\n }\n \n@@ -331,9 +358,7 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n \t\t\t\t unsigned long end, int psize)\n {\n \tunsigned long pid;\n-\tunsigned long addr;\n \tbool local;\n-\tunsigned long ap = mmu_get_ap(psize);\n \tunsigned long page_size = 1UL << mmu_psize_defs[psize].shift;\n \n \tpid = mm ? mm->context.id : 0;\n@@ -350,18 +375,10 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n \t\t\t_tlbie_pid(pid, RIC_FLUSH_TLB);\n \n \t} else {\n-\t\tasm volatile(\"ptesync\": : :\"memory\");\n-\t\tfor (addr = start; addr < end; addr += page_size) {\n-\n-\t\t\tif (local)\n-\t\t\t\t__tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\t\telse\n-\t\t\t\t__tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\t}\n \t\tif (local)\n-\t\t\tasm volatile(\"ptesync\": : :\"memory\");\n+\t\t\t_tlbiel_va_range(start, end, pid, page_size, psize);\n \t\telse\n-\t\t\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+\t\t\t_tlbie_va_range(start, end, pid, page_size, psize);\n \t}\n \tpreempt_enable();\n }\n@@ -369,7 +386,6 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,\n #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)\n {\n-\tunsigned long ap = mmu_get_ap(mmu_virtual_psize);\n \tunsigned long pid, end;\n \tbool local;\n \n@@ -392,18 +408,12 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)\n \t\t_tlbie_pid(pid, RIC_FLUSH_PWC);\n \n \t/* Then iterate the pages */\n-\tasm volatile(\"ptesync\": : :\"memory\");\n \tend = addr + HPAGE_PMD_SIZE;\n-\tfor (; addr < end; addr += PAGE_SIZE) {\n-\t\tif (local)\n-\t\t\t_tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t\telse\n-\t\t\t_tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);\n-\t}\n+\n \tif (local)\n-\t\tasm volatile(\"ptesync\": : :\"memory\");\n+\t\t_tlbiel_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);\n \telse\n-\t\tasm volatile(\"eieio; tlbsync; ptesync\": : :\"memory\");\n+\t\t_tlbie_va_range(addr, end, pid, PAGE_SIZE, mmu_virtual_psize);\n \tpreempt_enable();\n }\n #endif /* CONFIG_TRANSPARENT_HUGEPAGE */\n", "prefixes": [ "RFC", "4/8" ] }