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GET /api/patches/811060/?format=api
{ "id": 811060, "url": "http://patchwork.ozlabs.org/api/patches/811060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-2-npiggin@gmail.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170907145148.24398-2-npiggin@gmail.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170907145148.24398-2-npiggin@gmail.com/", "date": "2017-09-07T14:51:41", "name": "[RFC,1/8] powerpc/64s/radix: Fix theoretical process table entry cache invalidation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "75374acb82f0a851ee309ea3b4d26c288cd3aa61", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170907145148.24398-2-npiggin@gmail.com/mbox/", "series": [ { "id": 2010, "url": "http://patchwork.ozlabs.org/api/series/2010/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2010", "date": "2017-09-07T14:51:40", "name": "Further radix TLB flush optimisations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2010/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp3R91sm1z9s81\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 8 Sep 2017 00:55:33 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xp3R90WKvzDrWs\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 8 Sep 2017 00:55:33 +1000 (AEST)", "from mail-pf0-x242.google.com (mail-pf0-x242.google.com\n\t[IPv6:2607:f8b0:400e:c00::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xp3MP6hDFzDrWb\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 8 Sep 2017 00:52:17 +1000 (AEST)", "by mail-pf0-x242.google.com with SMTP id a2so4609843pfj.4\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 07 Sep 2017 07:52:17 -0700 (PDT)", "from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202])\n\tby smtp.gmail.com with ESMTPSA id\n\ta6sm4642791pfa.76.2017.09.07.07.52.12\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 07 Sep 2017 07:52:14 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Cjo61LHJ\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Cjo61LHJ\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Cjo61LHJ\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=wUW++PagQ4UzHZDXfLcVZsqs8tvSNWgy0gDgIcHJ170=;\n\tb=Cjo61LHJyZ39KXo/j8Cbhc+yk5KV9OFWv10xuGgcnIBHHK7iqYR/ka8rmjzofm8nyQ\n\t4Pzd/RNUSzYf+pW982Fo90DYrsdPI0xGs+4S/9JvWPlmRKKGwx3b7/CEStms9d+gkn/G\n\tMEd6m2379bJLROY/ThNQ70ETWfTXUjo3NvD13cmTNi0xeQn20pTGcUMJYfwQd8y3Nxgw\n\tXTvJVad7UkT7XegnJAR5P8nKfndegRtkGn481pUfq6CtO2XjuJ6f9UDLre0o/m0WH3yI\n\tTarR1O5d3rUTe/PA8oY5ukNtiQvjPqzNfOBuOUh2n6L7yuard+s2ypXh1RWml6QxdJvn\n\twUwg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=wUW++PagQ4UzHZDXfLcVZsqs8tvSNWgy0gDgIcHJ170=;\n\tb=IH/SC5UIXXmH5JwkN74ZlHliWT6lp27FeHGMgvH2rE6eqltNGu6udGG8Ca4jCo/fsw\n\tYkQje/tPVjAS+/nnlW5iAVQ2muAyBMXRYY+3Cjd/dRvb0/FZvP2UYzRZgh7vwoAvqBoH\n\tgaUkDq9JDJF/WexyOfQvakrHOKK/y2FJPyx7MvENah2g5Fk1nNRM5xLII3Q0Q7nAXhb4\n\tHwaQJCC+EyzrzvEViiD0mi3NkAtL7cFJo+3+rDADnVuhksWNbsfYnhWNU0V799RlAGTL\n\tHE4/fAZXRCKjOAbZxacyFb67lDG0YagGYTrv1yjs7iHnUvxxJQEqDpUklziTHRGFwlVS\n\trhDA==", "X-Gm-Message-State": "AHPjjUg3FQILEyuA5SsWXeGM1cV54Yt1dvGpla5L9OhjPZZ5bN0F621U\n\t3WGIwgKdztn4M519", "X-Google-Smtp-Source": "ADKCNb52WyOKqlK2d1rujZMpAwWvHFoFWNB7+9lsSvGA3Kj4HpI0KB6DpOjN/emSVBDxXyJ2y5zVXw==", "X-Received": "by 10.101.73.198 with SMTP id t6mr3033508pgs.382.1504795935594; \n\tThu, 07 Sep 2017 07:52:15 -0700 (PDT)", "From": "Nicholas Piggin <npiggin@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[RFC PATCH 1/8] powerpc/64s/radix: Fix theoretical process table\n\tentry cache invalidation", "Date": "Fri, 8 Sep 2017 00:51:41 +1000", "Message-Id": "<20170907145148.24398-2-npiggin@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170907145148.24398-1-npiggin@gmail.com>", "References": "<20170907145148.24398-1-npiggin@gmail.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "\"Aneesh Kumar K . V\" <aneesh.kumar@linux.vnet.ibm.com>,\n\tNicholas Piggin <npiggin@gmail.com>, Anton Blanchard <anton@samba.org>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "According to the architecture, the process table entry cache must be\nflushed with RIC=2 tlbies. This problem doesn't hit in existing\nimplementations that do not cache process table entries over mtpid. The\nPID is only destroyed and re-used after all CPUs have switched away from\nthe mm, guaranteeing its entry is not cached anywhere. But this is not\ngenerally safe according to the ISA.\n\nFix this by clearing the process table entry before the final flush\n(which is always a RIC=2 flush that invalidates the process table entry\ncache).\n\nSigned-off-by: Nicholas Piggin <npiggin@gmail.com>\n---\n arch/powerpc/include/asm/mmu_context.h | 4 ++++\n arch/powerpc/mm/mmu_context_book3s64.c | 23 ++++++++++++++++++-----\n 2 files changed, 22 insertions(+), 5 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h\nindex 309592589e30..0a70221adcf7 100644\n--- a/arch/powerpc/include/asm/mmu_context.h\n+++ b/arch/powerpc/include/asm/mmu_context.h\n@@ -118,9 +118,13 @@ static inline void arch_dup_mmap(struct mm_struct *oldmm,\n {\n }\n \n+#ifndef CONFIG_PPC_BOOK3S_64\n static inline void arch_exit_mmap(struct mm_struct *mm)\n {\n }\n+#else\n+extern void arch_exit_mmap(struct mm_struct *mm);\n+#endif\n \n static inline void arch_unmap(struct mm_struct *mm,\n \t\t\t struct vm_area_struct *vma,\ndiff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c\nindex 05e15386d4cb..feb3f43195c2 100644\n--- a/arch/powerpc/mm/mmu_context_book3s64.c\n+++ b/arch/powerpc/mm/mmu_context_book3s64.c\n@@ -216,19 +216,32 @@ void destroy_context(struct mm_struct *mm)\n #ifdef CONFIG_SPAPR_TCE_IOMMU\n \tWARN_ON_ONCE(!list_empty(&mm->context.iommu_group_mem_list));\n #endif\n+\tif (radix_enabled())\n+\t\tWARN_ON(process_tb[mm->context.id].prtb0 != 0);\n+\telse\n+\t\tsubpage_prot_free(mm);\n+\tdestroy_pagetable_page(mm);\n+\t__destroy_context(mm->context.id);\n+\tmm->context.id = MMU_NO_CONTEXT;\n+}\n+\n+void arch_exit_mmap(struct mm_struct *mm)\n+{\n \tif (radix_enabled()) {\n \t\t/*\n \t\t * Radix doesn't have a valid bit in the process table\n \t\t * entries. However we know that at least P9 implementation\n \t\t * will avoid caching an entry with an invalid RTS field,\n \t\t * and 0 is invalid. So this will do.\n+\t\t *\n+\t\t * This runs before the \"fullmm\" tlb flush in exit_mmap,\n+\t\t * which does a RIC_FLUSH_ALL to clear the process table\n+\t\t * entry. No barrier required here after the store because\n+\t\t * this process will do the invalidate, which starts with\n+\t\t * ptesync.\n \t\t */\n \t\tprocess_tb[mm->context.id].prtb0 = 0;\n-\t} else\n-\t\tsubpage_prot_free(mm);\n-\tdestroy_pagetable_page(mm);\n-\t__destroy_context(mm->context.id);\n-\tmm->context.id = MMU_NO_CONTEXT;\n+\t}\n }\n \n #ifdef CONFIG_PPC_RADIX_MMU\n", "prefixes": [ "RFC", "1/8" ] }