Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/810992/?format=api
{ "id": 810992, "url": "http://patchwork.ozlabs.org/api/patches/810992/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com>", "list_archive_url": null, "date": "2017-09-07T11:52:45", "name": "[v4,1/4] dt-bindings: Document the STM32 DMAMUX bindings", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "0c183618ff5f62637335d2258f8909f70a1a3865", "submitter": { "id": 71499, "url": "http://patchwork.ozlabs.org/api/people/71499/?format=api", "name": "Pierre Yves MORDRET", "email": "pierre-yves.mordret@st.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com/mbox/", "series": [ { "id": 1988, "url": "http://patchwork.ozlabs.org/api/series/1988/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=1988", "date": "2017-09-07T11:52:47", "name": "Add STM32 DMAMUX support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/1988/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810992/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnzQv1smBz9t2c\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 21:55:03 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755078AbdIGLx7 (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 7 Sep 2017 07:53:59 -0400", "from mx07-00178001.pphosted.com ([62.209.51.94]:60910 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1754495AbdIGLx5 (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 7 Sep 2017 07:53:57 -0400", "from pps.filterd (m0046037.ppops.net [127.0.0.1])\n\tby mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv87BmkbP014203; Thu, 7 Sep 2017 13:53:01 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx07-00178001.pphosted.com with ESMTP id 2csteq6r1n-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tThu, 07 Sep 2017 13:53:01 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0069438;\n\tThu, 7 Sep 2017 11:52:59 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C718925AB;\n\tThu, 7 Sep 2017 11:52:59 +0000 (GMT)", "from localhost (10.75.127.51) by SFHDAG5NODE2.st.com (10.75.127.14)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tThu, 7 Sep 2017 13:52:59 +0200" ], "From": "Pierre-Yves MORDRET <pierre-yves.mordret@st.com>", "To": "Vinod Koul <vinod.koul@intel.com>, Rob Herring <robh+dt@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>,\n\tMaxime Coquelin <mcoquelin.stm32@gmail.com>,\n\tAlexandre Torgue <alexandre.torgue@st.com>,\n\tRussell King <linux@armlinux.org.uk>,\n\tDan Williams <dan.j.williams@intel.com>,\n\t\"M'boumba Cedric Madianga\" <cedric.madianga@gmail.com>,\n\tFabrice GASNIER <fabrice.gasnier@st.com>,\n\tHerbert Xu <herbert@gondor.apana.org.au>,\n\tFabien DESSENNE <fabien.dessenne@st.com>,\n\tAmelie Delaunay <amelie.delaunay@st.com>,\n\tPierre-Yves MORDRET <pierre-yves.mordret@st.com>,\n\t<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>", "Subject": "[PATCH v4 1/4] dt-bindings: Document the STM32 DMAMUX bindings", "Date": "Thu, 7 Sep 2017 13:52:45 +0200", "Message-ID": "<1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>", "References": "<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.75.127.51]", "X-ClientProxiedBy": "SFHDAG6NODE1.st.com (10.75.127.16) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-07_08:, , signatures=0", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "This patch adds the documentation of device tree bindings for the STM32\nDMAMUX.\n\nSigned-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>\nSigned-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>\n---\n Version history:\n v4:\n * Add multi-master ability for STM32 DMAMUX\n * Get rid of st,dmamux properties\n v3:\n * Change compatible to st,stm32h7-dmamux to be mode Soc specific\n * Add verbosity in dma-cells\n v2:\n * Move clock bindings from optional to mandatory one\n * Drop channelID bindings as managed dynamically from now on by\n DMAMUX driver.\n---\n---\n .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++++++++++++++++++\n 1 file changed, 84 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt", "diff": "diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt\nnew file mode 100644\nindex 0000000..1b893b2\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n@@ -0,0 +1,84 @@\n+STM32 DMA MUX (DMA request router)\n+\n+Required properties:\n+- compatible:\t\"st,stm32h7-dmamux\"\n+- reg:\t\tMemory map for accessing module\n+- #dma-cells:\tShould be set to <3>.\n+\t\tFirst parameter is request line number.\n+\t\tSecond is DMA channel configuration\n+\t\tThird is Fifo threshold\n+\t\tFor more details about the three cells, please see\n+\t\tstm32-dma.txt documentation binding file\n+- dma-masters:\tPhandle pointing to the DMA controllers.\n+\t\tSeveral controllers are allowed. Only \"st,stm32-dma\" DMA\n+\t\tcompatible are supported.\n+\n+Optional properties:\n+- dma-channels : Number of DMA requests supported.\n+- dma-requests : Number of DMAMUX requests supported.\n+- resets: Reference to a reset controller asserting the DMA controller\n+- clocks: Input clock of the DMAMUX instance.\n+\n+Example:\n+\n+/* DMA controller 1 */\n+dma1: dma-controller@40020000 {\n+\tcompatible = \"st,stm32-dma\";\n+\treg = <0x40020000 0x400>;\n+\tinterrupts = <11>,\n+\t\t <12>,\n+\t\t <13>,\n+\t\t <14>,\n+\t\t <15>,\n+\t\t <16>,\n+\t\t <17>,\n+\t\t <47>;\n+\tclocks = <&timer_clk>;\n+\t#dma-cells = <4>;\n+\tst,mem2mem;\n+\tresets = <&rcc 150>;\n+\tdma-channels = <8>;\n+\tdma-requests = <8>;\n+};\n+\n+/* DMA controller 1 */\n+dma2: dma@40020400 {\n+\tcompatible = \"st,stm32-dma\";\n+\treg = <0x40020400 0x400>;\n+\tinterrupts = <56>,\n+\t\t <57>,\n+\t\t <58>,\n+\t\t <59>,\n+\t\t <60>,\n+\t\t <68>,\n+\t\t <69>,\n+\t\t <70>;\n+\tclocks = <&timer_clk>;\n+\t#dma-cells = <4>;\n+\tst,mem2mem;\n+\tresets = <&rcc 150>;\n+\tdma-channels = <8>;\n+\tdma-requests = <8>;\n+};\n+\n+/* DMA mux */\n+dmamux1: dma-router@40020800 {\n+\tcompatible = \"st,stm32h7-dmamux\";\n+\treg = <0x40020800 0x3c>;\n+\t#dma-cells = <3>;\n+\tdma-requests = <128>;\n+\tdma-channels = <16>;\n+\tdma-masters = <&dma1 &dma2>;\n+\tclocks = <&timer_clk>;\n+};\n+\n+/* DMA client */\n+usart1: serial@40011000 {\n+\tcompatible = \"st,stm32-usart\", \"st,stm32-uart\";\n+\treg = <0x40011000 0x400>;\n+\tinterrupts = <37>;\n+\tclocks = <&timer_clk>;\n+\tdmas = <&dmamux1 41 0x414 0>,\n+\t <&dmamux1 42 0x414 0>;\n+\tdma-names = \"rx\", \"tx\";\n+};\n", "prefixes": [ "v4", "1/4" ] }