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{
    "id": 810934,
    "url": "http://patchwork.ozlabs.org/api/patches/810934/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/6a69e270519fd1c7a12a335053bf59671abc3c4b.1504776489.git.talho@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<6a69e270519fd1c7a12a335053bf59671abc3c4b.1504776489.git.talho@nvidia.com>",
    "list_archive_url": null,
    "date": "2017-09-07T09:31:02",
    "name": "[2/4] clk: tegra: check BPMP response return code",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "fa69e23d0e87e0075ea56028d75c05d98f15e2ae",
    "submitter": {
        "id": 72177,
        "url": "http://patchwork.ozlabs.org/api/people/72177/?format=api",
        "name": "Timo Alho",
        "email": "talho@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/6a69e270519fd1c7a12a335053bf59671abc3c4b.1504776489.git.talho@nvidia.com/mbox/",
    "series": [
        {
            "id": 1959,
            "url": "http://patchwork.ozlabs.org/api/series/1959/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=1959",
            "date": "2017-09-07T09:31:00",
            "name": "firmware: tegra: add checks for BPMP error return code",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/1959/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/810934/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/810934/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnwHM4PFyz9sNV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu,  7 Sep 2017 19:33:19 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755154AbdIGJdS (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 7 Sep 2017 05:33:18 -0400",
            "from hqemgate14.nvidia.com ([216.228.121.143]:4693 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1755153AbdIGJdR (ORCPT\n\t<rfc822; linux-tegra@vger.kernel.org>); Thu, 7 Sep 2017 05:33:17 -0400",
            "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B59b112420002>; Thu, 07 Sep 2017 02:32:50 -0700",
            "from HQMAIL105.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tThu, 07 Sep 2017 02:32:45 -0700",
            "from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL105.nvidia.com\n\t(172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tThu, 7 Sep 2017 09:31:26 +0000",
            "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Thu, 7 Sep 2017 09:31:26 +0000",
            "from talho-ln2.nvidia.com (Not Verified[10.21.24.139]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid <B59b111ed0002>; Thu, 07 Sep 2017 02:31:26 -0700"
        ],
        "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Thu, 07 Sep 2017 02:32:45 -0700",
        "From": "Timo Alho <talho@nvidia.com>",
        "To": "<thierry.reding@gmail.com>",
        "CC": "<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\tTimo Alho <talho@nvidia.com>",
        "Subject": "[PATCH 2/4] clk: tegra: check BPMP response return code",
        "Date": "Thu, 7 Sep 2017 12:31:02 +0300",
        "Message-ID": "<6a69e270519fd1c7a12a335053bf59671abc3c4b.1504776489.git.talho@nvidia.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<cover.1504776489.git.talho@nvidia.com>",
        "References": "<cover.1504776489.git.talho@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "Check return code in BPMP response message(s). The typical error case\nis when clock operation is attempted with invalid clock identifier.\n\nAlso remove error print from call to clk_get_info() as the\nimplementation loops through range of all possible identifier, but the\noperation is expected error out when the clock id is unused.\n\nSigned-off-by: Timo Alho <talho@nvidia.com>\n---\n drivers/clk/tegra/clk-bpmp.c | 15 ++++++++++-----\n 1 file changed, 10 insertions(+), 5 deletions(-)",
    "diff": "diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c\nindex 638ace6..a896692 100644\n--- a/drivers/clk/tegra/clk-bpmp.c\n+++ b/drivers/clk/tegra/clk-bpmp.c\n@@ -55,6 +55,7 @@ struct tegra_bpmp_clk_message {\n \tstruct {\n \t\tvoid *data;\n \t\tsize_t size;\n+\t\tint ret;\n \t} rx;\n };\n \n@@ -64,6 +65,7 @@ static int tegra_bpmp_clk_transfer(struct tegra_bpmp *bpmp,\n \tstruct mrq_clk_request request;\n \tstruct tegra_bpmp_message msg;\n \tvoid *req = &request;\n+\tint err;\n \n \tmemset(&request, 0, sizeof(request));\n \trequest.cmd_and_id = (clk->cmd << 24) | clk->id;\n@@ -84,7 +86,13 @@ static int tegra_bpmp_clk_transfer(struct tegra_bpmp *bpmp,\n \tmsg.rx.data = clk->rx.data;\n \tmsg.rx.size = clk->rx.size;\n \n-\treturn tegra_bpmp_transfer(bpmp, &msg);\n+\terr = tegra_bpmp_transfer(bpmp, &msg);\n+\tif (err < 0)\n+\t\treturn err;\n+\telse if (msg.rx.ret < 0)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n }\n \n static int tegra_bpmp_clk_prepare(struct clk_hw *hw)\n@@ -414,11 +422,8 @@ static int tegra_bpmp_probe_clocks(struct tegra_bpmp *bpmp,\n \t\tstruct tegra_bpmp_clk_info *info = &clocks[count];\n \n \t\terr = tegra_bpmp_clk_get_info(bpmp, id, info);\n-\t\tif (err < 0) {\n-\t\t\tdev_err(bpmp->dev, \"failed to query clock %u: %d\\n\",\n-\t\t\t\tid, err);\n+\t\tif (err < 0)\n \t\t\tcontinue;\n-\t\t}\n \n \t\tif (info->num_parents >= U8_MAX) {\n \t\t\tdev_err(bpmp->dev,\n",
    "prefixes": [
        "2/4"
    ]
}