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GET /api/patches/810756/?format=api
{ "id": 810756, "url": "http://patchwork.ozlabs.org/api/patches/810756/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/150472243868.24907.11184861173318139147.stgit@frigg.lan/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<150472243868.24907.11184861173318139147.stgit@frigg.lan>", "list_archive_url": null, "date": "2017-09-06T18:27:18", "name": "[v4,16/20] instrument: Add event 'guest_mem_before_trans'", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4cfbd0ced3e350f17b7116dca045e5c9a355f5b5", "submitter": { "id": 9099, "url": "http://patchwork.ozlabs.org/api/people/9099/?format=api", "name": "Lluís Vilanova", "email": "vilanova@ac.upc.edu" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/150472243868.24907.11184861173318139147.stgit@frigg.lan/mbox/", "series": [ { "id": 1859, "url": "http://patchwork.ozlabs.org/api/series/1859/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1859", "date": "2017-09-06T17:22:41", "name": "instrument: Add basic event instrumentation", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/1859/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810756/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810756/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnXC42TsTz9sRY\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 04:28:15 +1000 (AEST)", "from localhost ([::1]:37436 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpf3c-0007QS-L2\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 14:28:12 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:53388)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dpf31-0007QH-SB\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:27:41 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dpf2w-000108-8C\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:27:35 -0400", "from roura.ac.upc.es ([147.83.33.10]:51016)\n\tby eggs.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <vilanova@ac.upc.edu>) id 1dpf2v-0000zq-Lt\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:27:30 -0400", "from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91])\n\tby roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v86IRPi1005211;\n\tWed, 6 Sep 2017 20:27:25 +0200", "from localhost (unknown [31.210.187.58])\n\tby correu-1.ac.upc.es (Postfix) with ESMTPSA id 416F57FD;\n\tWed, 6 Sep 2017 20:27:20 +0200 (CEST)" ], "From": "=?utf-8?b?TGx1w61z?= Vilanova <vilanova@ac.upc.edu>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 21:27:18 +0300", "Message-Id": "<150472243868.24907.11184861173318139147.stgit@frigg.lan>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<150471856141.24907.274176769201097378.stgit@frigg.lan>", "References": "<150471856141.24907.274176769201097378.stgit@frigg.lan>", "User-Agent": "StGit/0.17.1-dirty", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "quoted-printable", "X-MIME-Autoconverted": "from 8bit to quoted-printable by roura.ac.upc.es id\n\tv86IRPi1005211", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy]", "X-Received-From": "147.83.33.10", "Subject": "[Qemu-devel] [PATCH v4 16/20] instrument: Add event\n\t'guest_mem_before_trans'", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "\"Emilio G. Cota\" <cota@braap.org>, Stefan Hajnoczi <stefanha@redhat.com>,\n\tPaolo Bonzini <pbonzini@redhat.com>, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\n---\n Makefile.target | 1 +\n instrument/control.c | 13 +++++++-\n instrument/control.h | 36 +++++++++++++++++++++-\n instrument/control.inc.h | 16 +++++++---\n instrument/events.h | 21 +++++++++++++\n instrument/events.inc.h | 19 ++++++++++++\n instrument/load.c | 1 +\n instrument/qemu-instr/control.h | 15 +++++++++\n instrument/qemu-instr/types.h | 64 +++++++++++++++++++++++++++++++++++++++\n stubs/instrument.c | 4 ++\n tcg/tcg-op.c | 5 +++\n trace/control.h | 23 ++++++++++++++\n trace/mem.h | 23 --------------\n 13 files changed, 210 insertions(+), 31 deletions(-)", "diff": "diff --git a/Makefile.target b/Makefile.target\nindex 7f42c45db8..6997b921c9 100644\n--- a/Makefile.target\n+++ b/Makefile.target\n@@ -196,6 +196,7 @@ $(QEMU_PROG_BUILD): config-devices.mak\n COMMON_LDADDS = ../libqemuutil.a ../libqemustub.a\n \n # build either PROG or PROGW\n+$(QEMU_PROG_BUILD): CFLAGS += -DQEMU_TARGET_BUILD=1\n $(QEMU_PROG_BUILD): $(all-obj-y) $(COMMON_LDADDS)\n \t$(call LINK, $(filter-out %.mak, $^))\n ifdef CONFIG_DARWIN\ndiff --git a/instrument/control.c b/instrument/control.c\nindex 3cec1028e5..3c3875dc99 100644\n--- a/instrument/control.c\n+++ b/instrument/control.c\n@@ -16,7 +16,7 @@\n #include \"qom/cpu.h\"\n \n \n-__thread InstrState instr_cur_state;\n+__thread InstrInfo instr_cur_info;\n \n \n unsigned int instr_cpus_count;\n@@ -75,3 +75,14 @@ QI_VPUBLIC void qi_event_set_guest_cpu_reset(void (*fn)(QICPU vcpu))\n ERROR_IF(!instr_get_state(), \"called outside instrumentation\");\n instr_set_event(guest_cpu_reset, fn);\n }\n+\n+\n+void (*instr_event__guest_mem_before_trans)(\n+ QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info);\n+\n+QI_VPUBLIC void qi_event_set_guest_mem_before_trans(\n+ void (*fn)(QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info))\n+{\n+ ERROR_IF(!instr_get_state(), \"called outside instrumentation\");\n+ instr_set_event(guest_mem_before_trans, fn);\n+}\ndiff --git a/instrument/control.h b/instrument/control.h\nindex 0c37692465..d9e3dd3da6 100644\n--- a/instrument/control.h\n+++ b/instrument/control.h\n@@ -56,12 +56,21 @@ typedef enum {\n INSTR_STATE_ENABLE,\n } InstrState;\n \n+#define INSTR_MAX_TCG_REGS 16\n+\n+typedef struct InstrInfo {\n+ InstrState state;\n+ unsigned int max;\n+ void *tcg_regs[INSTR_MAX_TCG_REGS];\n+} InstrInfo;\n+\n /**\n * instr_set_state:\n *\n- * Set the instrumentation state of the current host thread.\n+ * Set the instrumentation state of the current host thread, and return its\n+ * #InstrInfo.\n */\n-static inline void instr_set_state(InstrState state);\n+static inline InstrInfo *instr_set_state(InstrState state);\n \n /**\n * instr_get_state:\n@@ -70,6 +79,29 @@ static inline void instr_set_state(InstrState state);\n */\n static inline InstrState instr_get_state(void);\n \n+/**\n+ * instr_tcg_set:\n+ * @info: Pointer to #InstrInfo.\n+ * @num: Number of TCG register used by instrumentation.\n+ * @arg: TCG register.\n+ *\n+ * Get a suitable QITCGv* from a TCGv* value.\n+ */\n+#define instr_tcg_set(info, num, arg) \\\n+ ({ \\\n+ info->tcg_regs[num] = arg; \\\n+ (void *)num; \\\n+ })\n+\n+/**\n+ * instr_tcg_count:\n+ * @info: Pointer to #InstrInfo.\n+ * @count: Number of TCG registers used by instrumentation.\n+ *\n+ * Set the number of TCG registers used by instrumentation.\n+ */\n+static inline void instr_tcg_count(InstrInfo *info, unsigned int count);\n+\n \n #include \"instrument/control.inc.h\"\n \ndiff --git a/instrument/control.inc.h b/instrument/control.inc.h\nindex 18ae6a34cc..e8224319e0 100644\n--- a/instrument/control.inc.h\n+++ b/instrument/control.inc.h\n@@ -15,16 +15,18 @@\n #include <stdint.h>\n \n \n-extern __thread InstrState instr_cur_state;\n+extern __thread InstrInfo instr_cur_info;\n \n-static inline void instr_set_state(InstrState state)\n+static inline InstrInfo *instr_set_state(InstrState state)\n {\n- atomic_store_release(&instr_cur_state, state);\n+ InstrInfo *info = &instr_cur_info;\n+ atomic_store_release(&info->state, state);\n+ return info;\n }\n \n static inline InstrState instr_get_state(void)\n {\n- return atomic_load_acquire(&instr_cur_state);\n+ return atomic_load_acquire(&instr_cur_info.state);\n }\n \n \n@@ -46,3 +48,9 @@ static inline QICPU instr_cpu_set(CPUState *vcpu)\n uintptr_t idx = vcpu->cpu_index;\n return (QICPU )idx;\n }\n+\n+\n+static inline void instr_tcg_count(InstrInfo *info, unsigned int count)\n+{\n+ info->max = count;\n+}\ndiff --git a/instrument/events.h b/instrument/events.h\nindex 4a0560490a..1cc4dbb052 100644\n--- a/instrument/events.h\n+++ b/instrument/events.h\n@@ -12,6 +12,8 @@\n \n #include \"instrument/qemu-instr/control.h\"\n #include \"instrument/qemu-instr/types.h\"\n+#include \"trace/control.h\"\n+\n \n /**\n * instr_get_event:\n@@ -30,6 +32,20 @@\n atomic_store_release(&instr_event__ ## name, fn)\n \n \n+/*\n+ * Re-define types used by some instrumentation events. We need some arbitrary\n+ * definition for non-target objects.\n+ */\n+#if defined(QEMU_TARGET_BUILD)\n+#include \"tcg/tcg.h\"\n+#else\n+typedef struct TCGv_d *TCGv;\n+typedef struct TCGv_env_d *TCGv_env;\n+typedef struct TCGv_i32_d *TCGv_i32;\n+typedef struct TCGv_i64_d *TCGv_i64;\n+#endif\n+\n+\n extern qi_fini_fn instr_event__fini_fn;\n extern void *instr_event__fini_data;\n \n@@ -42,6 +58,11 @@ static inline void instr_guest_cpu_exit(CPUState *vcpu);\n extern void (*instr_event__guest_cpu_reset)(QICPU vcpu);\n static inline void instr_guest_cpu_reset(CPUState *vcpu);\n \n+extern void (*instr_event__guest_mem_before_trans)(\n+ QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info);\n+static inline void instr_guest_mem_before_trans(\n+ CPUState *vcpu_trans, TCGv_env vcpu_exec, TCGv vaddr, TraceMemInfo info);\n+\n \n #include \"instrument/events.inc.h\"\n \ndiff --git a/instrument/events.inc.h b/instrument/events.inc.h\nindex 2f2cd324aa..2cb17049f7 100644\n--- a/instrument/events.inc.h\n+++ b/instrument/events.inc.h\n@@ -8,6 +8,7 @@\n */\n \n #include \"instrument/control.h\"\n+#include \"trace/control.h\"\n \n \n static inline void instr_guest_cpu_enter(CPUState *vcpu)\n@@ -42,3 +43,21 @@ static inline void instr_guest_cpu_reset(CPUState *vcpu)\n instr_set_state(INSTR_STATE_DISABLE);\n }\n }\n+\n+static inline void instr_guest_mem_before_trans(\n+ CPUState *vcpu_trans, TCGv_env vcpu_exec, TCGv vaddr, TraceMemInfo info)\n+{\n+ void (*cb)(QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info)\n+ = instr_get_event(guest_mem_before_trans);\n+ if (cb) {\n+ InstrInfo *iinfo = instr_set_state(INSTR_STATE_ENABLE);\n+ QICPU vcpu_trans_ = instr_cpu_set(vcpu_trans);\n+ QITCGv_cpu vcpu_exec_ = instr_tcg_set(iinfo, 0, vcpu_exec);\n+ QITCGv vaddr_ = instr_tcg_set(iinfo, 1, vaddr);\n+ QIMemInfo info_;\n+ info_.raw = info.raw;\n+ instr_tcg_count(iinfo, 2);\n+ (*cb)(vcpu_trans_, vcpu_exec_, vaddr_, info_);\n+ instr_set_state(INSTR_STATE_DISABLE);\n+ }\n+}\ndiff --git a/instrument/load.c b/instrument/load.c\nindex d9310d1979..d5612af452 100644\n--- a/instrument/load.c\n+++ b/instrument/load.c\n@@ -151,6 +151,7 @@ InstrUnloadError instr_unload(int64_t handle_id)\n instr_set_event(guest_cpu_enter, NULL);\n instr_set_event(guest_cpu_exit, NULL);\n instr_set_event(guest_cpu_reset, NULL);\n+ instr_set_event(guest_mem_before_trans, NULL);\n \n /* this should never fail */\n if (dlclose(handle->dlhandle) < 0) {\ndiff --git a/instrument/qemu-instr/control.h b/instrument/qemu-instr/control.h\nindex 238ea63301..af4fda138e 100644\n--- a/instrument/qemu-instr/control.h\n+++ b/instrument/qemu-instr/control.h\n@@ -98,6 +98,21 @@ void qi_event_set_guest_cpu_exit(void (*fn)(QICPU vcpu));\n */\n void qi_event_set_guest_cpu_reset(void (*fn)(QICPU vcpu));\n \n+/*\n+ * Start virtual memory access (before any potential access violation).\n+ *\n+ * @vaddr: Access' virtual address.\n+ * @info : Access' information.\n+ *\n+ * Does not include memory accesses performed by devices.\n+ *\n+ * Mode: user, softmmu\n+ * Targets: TCG(all)\n+ * Time: trans\n+ */\n+void qi_event_set_guest_mem_before_trans(\n+ void (*fn)(QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info));\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/instrument/qemu-instr/types.h b/instrument/qemu-instr/types.h\nindex ea3a032b4f..11cbe1ccaa 100644\n--- a/instrument/qemu-instr/types.h\n+++ b/instrument/qemu-instr/types.h\n@@ -14,10 +14,18 @@\n extern \"C\" {\n #endif\n \n+#include <stdbool.h>\n+#include <stdint.h>\n+\n+\n /**\n * SECTION: types\n * @section_id: qi-types\n * @title: Common types\n+ *\n+ * Data of architecture-specific length is always passed as an #int64_t to\n+ * provide binary compatibility between the instrumentation library and QEMU,\n+ * regardless of the guest architecture being instrumented.\n */\n \n /**\n@@ -41,6 +49,62 @@ typedef struct QITraceEventIter QITraceEventIter;\n */\n typedef struct QICPU_d *QICPU;\n \n+/**\n+ * QIMemInfo:\n+ * @size_shift: Memoy access size, interpreted as \"1 << size_shift\" bytes.\n+ * @sign_extend: Whether the access is sign-extended.\n+ * @endianness: Endianness type (0: little, 1: big).\n+ * @store: Whether it's a store operation.\n+ *\n+ * Memory access information.\n+ */\n+typedef struct QIMemInfo {\n+ union {\n+ struct {\n+ uint8_t size_shift : 2;\n+ bool sign_extend: 1;\n+ uint8_t endianness : 1;\n+ bool store : 1;\n+ };\n+ uint8_t raw;\n+ };\n+} QIMemInfo;\n+\n+/**\n+ * QITCGv_cpu:\n+ *\n+ * TCG register with QICPU.\n+ */\n+typedef struct QITCGv_cpu_d *QITCGv_cpu;\n+\n+/**\n+ * QITCGv:\n+ *\n+ * TCG register with data of architecture-specific length.\n+ */\n+typedef struct QITCGv_d *QITCGv;\n+\n+/**\n+ * QITCGv_i32:\n+ *\n+ * TCG register with 32-bit data.\n+ */\n+typedef struct QITCGv_i32_d *QITCGv_i32;\n+\n+/**\n+ * QITCGv_i64:\n+ *\n+ * TCG register with 64-bit data.\n+ */\n+typedef struct QITCGv_i64_d *QITCGv_i64;\n+\n+/*\n+ * QITCGv_ptr:\n+ *\n+ * TCG register with pointer of architecture-specific length.\n+ */\n+typedef struct QITCGv_ptr_d *QITCGv_ptr;\n+\n \n #include <qemu-instr/types.inc.h>\n \ndiff --git a/stubs/instrument.c b/stubs/instrument.c\nindex 74935975da..5e0d5150b5 100644\n--- a/stubs/instrument.c\n+++ b/stubs/instrument.c\n@@ -10,7 +10,9 @@\n #include \"instrument/control.h\"\n \n \n-__thread InstrState instr_cur_state;\n+__thread InstrInfo instr_cur_info;\n void (*instr_event__guest_cpu_enter)(QICPU *vcpu);\n void (*instr_event__guest_cpu_exit)(QICPU *vcpu);\n void (*instr_event__guest_cpu_reset)(QICPU *vcpu);\n+void (*instr_event__guest_mem_before_trans)(\n+ QICPU vcpu_trans, QITCGv_cpu vcpu_exec, QITCGv vaddr, QIMemInfo info);\ndiff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 234e300ede..40de61872e 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -26,6 +26,7 @@\n #include \"qemu-common.h\"\n #include \"cpu.h\"\n #include \"exec/exec-all.h\"\n+#include \"instrument/events.h\"\n #include \"tcg.h\"\n #include \"tcg-op.h\"\n #include \"trace-tcg.h\"\n@@ -2667,6 +2668,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n TraceMemInfo meminfo;\n memop = tcg_canonicalize_memop(memop, 0, 0);\n meminfo = trace_mem_get_info(memop, 0);\n+ instr_guest_mem_before_trans(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);\n }\n@@ -2676,6 +2678,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n TraceMemInfo meminfo;\n memop = tcg_canonicalize_memop(memop, 0, 1);\n meminfo = trace_mem_get_info(memop, 1);\n+ instr_guest_mem_before_trans(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);\n }\n@@ -2696,6 +2699,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n memop = tcg_canonicalize_memop(memop, 1, 0);\n meminfo = trace_mem_get_info(memop, 0);\n+ instr_guest_mem_before_trans(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);\n }\n@@ -2711,6 +2715,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n memop = tcg_canonicalize_memop(memop, 1, 1);\n meminfo = trace_mem_get_info(memop, 1);\n+ instr_guest_mem_before_trans(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, meminfo.raw);\n gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);\n }\ndiff --git a/trace/control.h b/trace/control.h\nindex 3e6da24c98..6b3fe9a28f 100644\n--- a/trace/control.h\n+++ b/trace/control.h\n@@ -20,6 +20,29 @@ typedef struct TraceEventIter {\n const char *pattern;\n } TraceEventIter;\n \n+/**\n+ * TraceMemInfo:\n+ * @size_shift: Memoy access size, interpreted as \"1 << size_shift\" bytes.\n+ * @sign_extend: Whether the access is sign-extended.\n+ * @endianness: Endinness type (0: little, 1: big).\n+ * @store: Whether it's a store operation.\n+ *\n+ * Memory access information.\n+ *\n+ * NOTE: Keep in sync with QIMemInfo.\n+ */\n+typedef struct TraceMemInfo {\n+ union {\n+ struct {\n+ uint8_t size_shift : 2;\n+ bool sign_extend: 1;\n+ uint8_t endianness : 1;\n+ bool store : 1;\n+ };\n+ uint8_t raw;\n+ };\n+} TraceMemInfo;\n+\n \n /**\n * trace_event_iter_init:\ndiff --git a/trace/mem.h b/trace/mem.h\nindex 9866b41401..bc89673272 100644\n--- a/trace/mem.h\n+++ b/trace/mem.h\n@@ -12,29 +12,6 @@\n \n #include \"tcg/tcg.h\"\n \n-/**\n- * TraceMemInfo:\n- * @size_shift: Memoy access size, interpreted as \"1 << size_shift\" bytes.\n- * @sign_extend: Whether the access is sign-extended.\n- * @endianness: Endinness type (0: little, 1: big).\n- * @store: Whether it's a store operation.\n- *\n- * Memory access information.\n- *\n- * NOTE: Keep in sync with QIMemInfo.\n- */\n-typedef struct TraceMemInfo {\n- union {\n- struct {\n- uint8_t size_shift : 2;\n- bool sign_extend: 1;\n- uint8_t endianness : 1;\n- bool store : 1;\n- };\n- uint8_t raw;\n- };\n-} TraceMemInfo;\n-\n \n /**\n * trace_mem_get_info:\n", "prefixes": [ "v4", "16/20" ] }