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GET /api/patches/810752/?format=api
{ "id": 810752, "url": "http://patchwork.ozlabs.org/api/patches/810752/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504721995-22267-2-git-send-email-mark.cave-ayland@ilande.co.uk/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504721995-22267-2-git-send-email-mark.cave-ayland@ilande.co.uk>", "list_archive_url": null, "date": "2017-09-06T18:19:55", "name": "[PATCHv2,1/1] net: Add SunGEM device emulation as found on Apple UniNorth", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2dd516ad977205a342b70684ecdea888e12dc188", "submitter": { "id": 12451, "url": "http://patchwork.ozlabs.org/api/people/12451/?format=api", "name": "Mark Cave-Ayland", "email": "mark.cave-ayland@ilande.co.uk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1504721995-22267-2-git-send-email-mark.cave-ayland@ilande.co.uk/mbox/", "series": [ { "id": 1863, "url": "http://patchwork.ozlabs.org/api/series/1863/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1863", "date": "2017-09-06T18:19:55", "name": "net: Add SunGEM device emulation as found on Apple UniNorth", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1863/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810752/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810752/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnX2n315Qz9sRY\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 04:21:05 +1000 (AEST)", "from localhost ([::1]:37410 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpewh-0004Bj-GU\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 14:21:03 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:50198)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <mark.cave-ayland@ilande.co.uk>) id 1dpew4-00047o-GW\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:20:29 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <mark.cave-ayland@ilande.co.uk>) id 1dpevv-0006GW-MT\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 14:20:24 -0400", "from chuckie.co.uk ([82.165.15.123]:47211\n\thelo=s16892447.onlinehome-server.info)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <mark.cave-ayland@ilande.co.uk>)\n\tid 1dpevv-0006G8-1R; Wed, 06 Sep 2017 14:20:15 -0400", "from host109-152-7-45.range109-152.btcentralplus.com\n\t([109.152.7.45]\n\thelo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa\n\t(TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76)\n\t(envelope-from <mark.cave-ayland@ilande.co.uk>)\n\tid 1dpevp-0000Vw-Ik; Wed, 06 Sep 2017 19:20:15 +0100" ], "From": "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>", "To": "qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, \n\tbenh@kernel.crashing.org", "Date": "Wed, 6 Sep 2017 19:19:55 +0100", "Message-Id": "<1504721995-22267-2-git-send-email-mark.cave-ayland@ilande.co.uk>", "X-Mailer": "git-send-email 1.7.10.4", "In-Reply-To": "<1504721995-22267-1-git-send-email-mark.cave-ayland@ilande.co.uk>", "References": "<1504721995-22267-1-git-send-email-mark.cave-ayland@ilande.co.uk>", "X-SA-Exim-Connect-IP": "109.152.7.45", "X-SA-Exim-Mail-From": "mark.cave-ayland@ilande.co.uk", "X-SA-Exim-Version": "4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000)", "X-SA-Exim-Scanned": "Yes (on s16892447.onlinehome-server.info)", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 3.x [fuzzy]", "X-Received-From": "82.165.15.123", "Subject": "[Qemu-devel] [PATCHv2 1/1] net: Add SunGEM device emulation as\n\tfound on Apple UniNorth", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Benjamin Herrenschmidt <benh@kernel.crashing.org>\n\nThis adds a simplistic emulation of the Sun GEM ethernet controller\nfound in Apple ASICs.\n\nCurrently we only support the Apple UniNorth 1.x variant, but the\nother Apple or Sun variants should mostly be a matter of adding\nPCI IDs options.\n\nWe have a very primitive emulation of a single Broadcom 5201 PHY\nwhich is supported by the MacOS driver.\n\nThis model brings out-of-the-box networking to MacOS 9, and all\nversions of OS X I tried with the mac99 platform.\n\nFurther improvements from Mark:\n- Remove sungem.h file, moving constants into sungem.c as required\n- Switch to using tracepoints for debugging\n- Split register blocks into separate memory regions\n- Use arrays in SunGEMState to hold register values\n- Add state-saving support\n\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>\n---\n default-configs/ppc-softmmu.mak | 1 +\n hw/net/Makefile.objs | 1 +\n hw/net/sungem.c | 1447 +++++++++++++++++++++++++++++++++++++++\n hw/net/trace-events | 44 ++\n hw/pci/pci.c | 2 +\n include/hw/pci/pci_ids.h | 1 +\n 6 files changed, 1496 insertions(+)\n create mode 100644 hw/net/sungem.c", "diff": "diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak\nindex 1f1cd85..c12ba9e 100644\n--- a/default-configs/ppc-softmmu.mak\n+++ b/default-configs/ppc-softmmu.mak\n@@ -17,6 +17,7 @@ CONFIG_PREP_PCI=y\n CONFIG_I82378=y\n CONFIG_PC87312=y\n CONFIG_MACIO=y\n+CONFIG_SUNGEM=y\n CONFIG_PCSPK=y\n CONFIG_CS4231A=y\n CONFIG_CUDA=y\ndiff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs\nindex 5ddaffe..7e87d01 100644\n--- a/hw/net/Makefile.objs\n+++ b/hw/net/Makefile.objs\n@@ -27,6 +27,7 @@ common-obj-$(CONFIG_CADENCE) += cadence_gem.o\n common-obj-$(CONFIG_STELLARIS_ENET) += stellaris_enet.o\n common-obj-$(CONFIG_LANCE) += lance.o\n common-obj-$(CONFIG_FTGMAC100) += ftgmac100.o\n+common-obj-$(CONFIG_SUNGEM) += sungem.o\n \n obj-$(CONFIG_ETRAXFS) += etraxfs_eth.o\n obj-$(CONFIG_COLDFIRE) += mcf_fec.o\ndiff --git a/hw/net/sungem.c b/hw/net/sungem.c\nnew file mode 100644\nindex 0000000..dffa0c9\n--- /dev/null\n+++ b/hw/net/sungem.c\n@@ -0,0 +1,1447 @@\n+/*\n+ * QEMU model of SUN GEM ethernet controller\n+ *\n+ * As found in Apple ASICs among others\n+ *\n+ * Copyright 2016 Ben Herrenschmidt\n+ * Copyright 2017 Mark Cave-Ayland\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"qemu/log.h\"\n+#include \"net/net.h\"\n+#include \"net/checksum.h\"\n+#include \"hw/net/mii.h\"\n+#include \"sysemu/sysemu.h\"\n+#include \"trace.h\"\n+/* For crc32 */\n+#include <zlib.h>\n+\n+#define TYPE_SUNGEM \"sungem\"\n+\n+#define SUNGEM(obj) OBJECT_CHECK(SunGEMState, (obj), TYPE_SUNGEM)\n+\n+#define MAX_PACKET_SIZE 9016\n+\n+#define SUNGEM_MMIO_SIZE 0x200000\n+\n+/* Global registers */\n+#define SUNGEM_MMIO_GREG_SIZE 0x2000\n+\n+#define GREG_SEBSTATE 0x0000UL /* SEB State Register */\n+\n+#define GREG_STAT 0x000CUL /* Status Register */\n+#define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */\n+#define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */\n+#define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */\n+#define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */\n+#define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */\n+#define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */\n+#define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */\n+#define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */\n+#define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */\n+#define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */\n+#define GREG_STAT_TXNR_SHIFT 19\n+\n+/* These interrupts are edge latches in the status register,\n+ * reading it (or writing the corresponding bit in IACK) will\n+ * clear them\n+ */\n+#define GREG_STAT_LATCH (GREG_STAT_TXALL | GREG_STAT_TXINTME | \\\n+ GREG_STAT_RXDONE | GREG_STAT_RXDONE | \\\n+ GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR)\n+\n+#define GREG_IMASK 0x0010UL /* Interrupt Mask Register */\n+#define GREG_IACK 0x0014UL /* Interrupt ACK Register */\n+#define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */\n+#define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */\n+#define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */\n+\n+#define GREG_SWRST 0x1010UL /* Software Reset Register */\n+#define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */\n+#define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */\n+#define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */\n+\n+/* TX DMA Registers */\n+#define SUNGEM_MMIO_TXDMA_SIZE 0x1000\n+\n+#define TXDMA_KICK 0x0000UL /* TX Kick Register */\n+\n+#define TXDMA_CFG 0x0004UL /* TX Configuration Register */\n+#define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */\n+#define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */\n+\n+#define TXDMA_DBLOW 0x0008UL /* TX Desc. Base Low */\n+#define TXDMA_DBHI 0x000CUL /* TX Desc. Base High */\n+#define TXDMA_PCNT 0x0024UL /* TX FIFO Packet Counter */\n+#define TXDMA_SMACHINE 0x0028UL /* TX State Machine Register */\n+#define TXDMA_DPLOW 0x0030UL /* TX Data Pointer Low */\n+#define TXDMA_DPHI 0x0034UL /* TX Data Pointer High */\n+#define TXDMA_TXDONE 0x0100UL /* TX Completion Register */\n+#define TXDMA_FTAG 0x0108UL /* TX FIFO Tag */\n+#define TXDMA_FSZ 0x0118UL /* TX FIFO Size */\n+\n+/* Receive DMA Registers */\n+#define SUNGEM_MMIO_RXDMA_SIZE 0x2000\n+\n+#define RXDMA_CFG 0x0000UL /* RX Configuration Register */\n+#define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */\n+#define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */\n+#define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */\n+#define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */\n+\n+#define RXDMA_DBLOW 0x0004UL /* RX Descriptor Base Low */\n+#define RXDMA_DBHI 0x0008UL /* RX Descriptor Base High */\n+#define RXDMA_PCNT 0x0018UL /* RX FIFO Packet Counter */\n+#define RXDMA_SMACHINE 0x001CUL /* RX State Machine Register */\n+#define RXDMA_PTHRESH 0x0020UL /* Pause Thresholds */\n+#define RXDMA_DPLOW 0x0024UL /* RX Data Pointer Low */\n+#define RXDMA_DPHI 0x0028UL /* RX Data Pointer High */\n+#define RXDMA_KICK 0x0100UL /* RX Kick Register */\n+#define RXDMA_DONE 0x0104UL /* RX Completion Register */\n+#define RXDMA_BLANK 0x0108UL /* RX Blanking Register */\n+#define RXDMA_FTAG 0x0110UL /* RX FIFO Tag */\n+#define RXDMA_FSZ 0x0120UL /* RX FIFO Size */\n+\n+/* MAC Registers */\n+#define SUNGEM_MMIO_MAC_SIZE 0x200\n+\n+#define MAC_TXRST 0x0000UL /* TX MAC Software Reset Command */\n+#define MAC_RXRST 0x0004UL /* RX MAC Software Reset Command */\n+#define MAC_TXSTAT 0x0010UL /* TX MAC Status Register */\n+#define MAC_RXSTAT 0x0014UL /* RX MAC Status Register */\n+\n+#define MAC_CSTAT 0x0018UL /* MAC Control Status Register */\n+#define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */\n+\n+#define MAC_TXMASK 0x0020UL /* TX MAC Mask Register */\n+#define MAC_RXMASK 0x0024UL /* RX MAC Mask Register */\n+#define MAC_MCMASK 0x0028UL /* MAC Control Mask Register */\n+\n+#define MAC_TXCFG 0x0030UL /* TX MAC Configuration Register */\n+#define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */\n+\n+#define MAC_RXCFG 0x0034UL /* RX MAC Configuration Register */\n+#define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */\n+#define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */\n+#define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */\n+#define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */\n+#define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */\n+\n+#define MAC_XIFCFG 0x003CUL /* XIF Configuration Register */\n+#define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */\n+\n+#define MAC_MINFSZ 0x0050UL /* MinFrameSize Register */\n+#define MAC_MAXFSZ 0x0054UL /* MaxFrameSize Register */\n+#define MAC_ADDR0 0x0080UL /* MAC Address 0 Register */\n+#define MAC_ADDR1 0x0084UL /* MAC Address 1 Register */\n+#define MAC_ADDR2 0x0088UL /* MAC Address 2 Register */\n+#define MAC_ADDR3 0x008CUL /* MAC Address 3 Register */\n+#define MAC_ADDR4 0x0090UL /* MAC Address 4 Register */\n+#define MAC_ADDR5 0x0094UL /* MAC Address 5 Register */\n+#define MAC_HASH0 0x00C0UL /* Hash Table 0 Register */\n+#define MAC_PATMPS 0x0114UL /* Peak Attempts Register */\n+#define MAC_SMACHINE 0x0134UL /* State Machine Register */\n+\n+/* MIF Registers */\n+#define SUNGEM_MMIO_MIF_SIZE 0x20\n+\n+#define MIF_FRAME 0x000CUL /* MIF Frame/Output Register */\n+#define MIF_FRAME_OP 0x30000000 /* OPcode */\n+#define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */\n+#define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */\n+#define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */\n+#define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */\n+\n+#define MIF_CFG 0x0010UL /* MIF Configuration Register */\n+#define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */\n+#define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */\n+\n+#define MIF_STATUS 0x0018UL /* MIF Status Register */\n+#define MIF_SMACHINE 0x001CUL /* MIF State Machine Register */\n+\n+/* PCS/Serialink Registers */\n+#define SUNGEM_MMIO_PCS_SIZE 0x60\n+#define PCS_MIISTAT 0x0004UL /* PCS MII Status Register */\n+#define PCS_ISTAT 0x0018UL /* PCS Interrupt Status Reg */\n+#define PCS_SSTATE 0x005CUL /* Serialink State Register */\n+\n+/* Descriptors */\n+struct gem_txd {\n+ uint64_t control_word;\n+ uint64_t buffer;\n+};\n+\n+#define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */\n+#define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */\n+#define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */\n+#define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */\n+#define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */\n+#define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */\n+#define TXDCTRL_INTME 0x0000000100000000ULL /* \"Interrupt Me\" */\n+\n+struct gem_rxd {\n+ uint64_t status_word;\n+ uint64_t buffer;\n+};\n+\n+#define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */\n+#define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */\n+\n+\n+typedef struct {\n+ PCIDevice pdev;\n+\n+ MemoryRegion sungem;\n+ MemoryRegion greg;\n+ MemoryRegion txdma;\n+ MemoryRegion rxdma;\n+ MemoryRegion mac;\n+ MemoryRegion mif;\n+ MemoryRegion pcs;\n+ NICState *nic;\n+ NICConf conf;\n+ uint32_t phy_addr;\n+\n+ uint32_t gregs[SUNGEM_MMIO_GREG_SIZE >> 2];\n+ uint32_t txdmaregs[SUNGEM_MMIO_TXDMA_SIZE >> 2];\n+ uint32_t rxdmaregs[SUNGEM_MMIO_RXDMA_SIZE >> 2];\n+ uint32_t macregs[SUNGEM_MMIO_MAC_SIZE >> 2];\n+ uint32_t mifregs[SUNGEM_MMIO_MIF_SIZE >> 2];\n+ uint32_t pcsregs[SUNGEM_MMIO_PCS_SIZE >> 2];\n+\n+ /* Cache some useful things */\n+ uint32_t rx_mask;\n+ uint32_t tx_mask;\n+\n+ /* Current tx packet */\n+ uint8_t tx_data[MAX_PACKET_SIZE];\n+ uint32_t tx_size;\n+ uint64_t tx_first_ctl;\n+} SunGEMState;\n+\n+\n+static void sungem_eval_irq(SunGEMState *s)\n+{\n+ uint32_t stat, mask;\n+\n+ mask = s->gregs[GREG_IMASK >> 2];\n+ stat = s->gregs[GREG_STAT >> 2] & ~GREG_STAT_TXNR;\n+ if (stat & ~mask) {\n+ pci_set_irq(PCI_DEVICE(s), 1);\n+ } else {\n+ pci_set_irq(PCI_DEVICE(s), 0);\n+ }\n+}\n+\n+static void sungem_update_status(SunGEMState *s, uint32_t bits, bool val)\n+{\n+ uint32_t stat;\n+\n+ stat = s->gregs[GREG_STAT >> 2];\n+ if (val) {\n+ stat |= bits;\n+ } else {\n+ stat &= ~bits;\n+ }\n+ s->gregs[GREG_STAT >> 2] = stat;\n+ sungem_eval_irq(s);\n+}\n+\n+static void sungem_eval_cascade_irq(SunGEMState *s)\n+{\n+ uint32_t stat, mask;\n+\n+ mask = s->macregs[MAC_TXSTAT >> 2];\n+ stat = s->macregs[MAC_TXMASK >> 2];\n+ if (stat & ~mask) {\n+ sungem_update_status(s, GREG_STAT_TXMAC, true);\n+ } else {\n+ sungem_update_status(s, GREG_STAT_TXMAC, false);\n+ }\n+\n+ mask = s->macregs[MAC_RXSTAT >> 2];\n+ stat = s->macregs[MAC_RXMASK >> 2];\n+ if (stat & ~mask) {\n+ sungem_update_status(s, GREG_STAT_RXMAC, true);\n+ } else {\n+ sungem_update_status(s, GREG_STAT_RXMAC, false);\n+ }\n+\n+ mask = s->macregs[MAC_CSTAT >> 2];\n+ stat = s->macregs[MAC_MCMASK >> 2] & ~MAC_CSTAT_PTR;\n+ if (stat & ~mask) {\n+ sungem_update_status(s, GREG_STAT_MAC, true);\n+ } else {\n+ sungem_update_status(s, GREG_STAT_MAC, false);\n+ }\n+}\n+\n+static void sungem_do_tx_csum(SunGEMState *s)\n+{\n+ uint16_t start, off;\n+ uint32_t csum;\n+\n+ start = (s->tx_first_ctl & TXDCTRL_CSTART) >> 15;\n+ off = (s->tx_first_ctl & TXDCTRL_COFF) >> 21;\n+\n+ trace_sungem_tx_checksum(start, off);\n+\n+ if (start > (s->tx_size - 2) || off > (s->tx_size - 2)) {\n+ trace_sungem_tx_checksum_oob();\n+ return;\n+ }\n+\n+ csum = net_raw_checksum(s->tx_data + start, s->tx_size - start);\n+ stw_be_p(s->tx_data + off, csum);\n+}\n+\n+static void sungem_send_packet(SunGEMState *s, const uint8_t *buf,\n+ int size)\n+{\n+ NetClientState *nc = qemu_get_queue(s->nic);\n+\n+ if (s->macregs[MAC_XIFCFG >> 2] & MAC_XIFCFG_LBCK) {\n+ nc->info->receive(nc, buf, size);\n+ } else {\n+ qemu_send_packet(nc, buf, size);\n+ }\n+}\n+\n+static void sungem_process_tx_desc(SunGEMState *s, struct gem_txd *desc)\n+{\n+ PCIDevice *d = PCI_DEVICE(s);\n+ uint32_t len;\n+\n+ /* If it's a start of frame, discard anything we had in the\n+ * buffer and start again. This should be an error condition\n+ * if we had something ... for now we ignore it\n+ */\n+ if (desc->control_word & TXDCTRL_SOF) {\n+ if (s->tx_first_ctl) {\n+ trace_sungem_tx_unfinished();\n+ }\n+ s->tx_size = 0;\n+ s->tx_first_ctl = desc->control_word;\n+ }\n+\n+ /* Grab data size */\n+ len = desc->control_word & TXDCTRL_BUFSZ;\n+\n+ /* Clamp it to our max size */\n+ if ((s->tx_size + len) > MAX_PACKET_SIZE) {\n+ trace_sungem_tx_overflow();\n+ len = MAX_PACKET_SIZE - s->tx_size;\n+ }\n+\n+ /* Read the data */\n+ pci_dma_read(d, desc->buffer, &s->tx_data[s->tx_size], len);\n+ s->tx_size += len;\n+\n+ /* If end of frame, send packet */\n+ if (desc->control_word & TXDCTRL_EOF) {\n+ trace_sungem_tx_finished(s->tx_size);\n+\n+ /* Handle csum */\n+ if (s->tx_first_ctl & TXDCTRL_CENAB) {\n+ sungem_do_tx_csum(s);\n+ }\n+\n+ /* Send it */\n+ sungem_send_packet(s, s->tx_data, s->tx_size);\n+\n+ /* No more pending packet */\n+ s->tx_size = 0;\n+ s->tx_first_ctl = 0;\n+ }\n+}\n+\n+static void sungem_tx_kick(SunGEMState *s)\n+{\n+ PCIDevice *d = PCI_DEVICE(s);\n+ uint32_t comp, kick;\n+ uint32_t txdma_cfg, txmac_cfg, ints;\n+ uint64_t dbase;\n+\n+ trace_sungem_tx_kick();\n+\n+ /* Check that both TX MAC and TX DMA are enabled. We don't\n+ * handle DMA-less direct FIFO operations (we don't emulate\n+ * the FIFO at all).\n+ *\n+ * A write to TXDMA_KICK while DMA isn't enabled can happen\n+ * when the driver is resetting the pointer.\n+ */\n+ txdma_cfg = s->txdmaregs[TXDMA_CFG >> 2];\n+ txmac_cfg = s->macregs[MAC_TXCFG >> 2];\n+ if (!(txdma_cfg & TXDMA_CFG_ENABLE) ||\n+ !(txmac_cfg & MAC_TXCFG_ENAB)) {\n+ trace_sungem_tx_disabled();\n+ return;\n+ }\n+\n+ /* XXX Test min frame size register ? */\n+ /* XXX Test max frame size register ? */\n+\n+ dbase = s->txdmaregs[TXDMA_DBHI >> 2];\n+ dbase = (dbase << 32) | s->txdmaregs[TXDMA_DBLOW >> 2];\n+\n+ comp = s->txdmaregs[TXDMA_TXDONE >> 2] & s->tx_mask;\n+ kick = s->txdmaregs[TXDMA_KICK >> 2] & s->tx_mask;\n+\n+ trace_sungem_tx_process(comp, kick, s->tx_mask + 1);\n+\n+ /* This is rather primitive for now, we just send everything we\n+ * can in one go, like e1000. Ideally we should do the sending\n+ * from some kind of background task\n+ */\n+ while (comp != kick) {\n+ struct gem_txd desc;\n+\n+ /* Read the next descriptor */\n+ pci_dma_read(d, dbase + comp * sizeof(desc), &desc, sizeof(desc));\n+\n+ /* Byteswap descriptor */\n+ desc.control_word = le64_to_cpu(desc.control_word);\n+ desc.buffer = le64_to_cpu(desc.buffer);\n+ trace_sungem_tx_desc(comp, desc.control_word, desc.buffer);\n+\n+ /* Send it for processing */\n+ sungem_process_tx_desc(s, &desc);\n+\n+ /* Interrupt */\n+ ints = GREG_STAT_TXDONE;\n+ if (desc.control_word & TXDCTRL_INTME) {\n+ ints |= GREG_STAT_TXINTME;\n+ }\n+ sungem_update_status(s, ints, true);\n+\n+ /* Next ! */\n+ comp = (comp + 1) & s->tx_mask;\n+ s->txdmaregs[TXDMA_TXDONE >> 2] = comp;\n+ }\n+\n+ /* We sent everything, set status/irq bit */\n+ sungem_update_status(s, GREG_STAT_TXALL, true);\n+}\n+\n+static bool sungem_rx_full(SunGEMState *s, uint32_t kick, uint32_t done)\n+{\n+ return kick == ((done + 1) & s->rx_mask);\n+}\n+\n+static int sungem_can_receive(NetClientState *nc)\n+{\n+ SunGEMState *s = qemu_get_nic_opaque(nc);\n+ uint32_t kick, done, rxdma_cfg, rxmac_cfg;\n+ bool full;\n+\n+ rxmac_cfg = s->macregs[MAC_RXCFG >> 2];\n+ rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];\n+\n+ /* If MAC disabled, can't receive */\n+ if ((rxmac_cfg & MAC_RXCFG_ENAB) == 0) {\n+ trace_sungem_rx_mac_disabled();\n+ return 0;\n+ }\n+ if ((rxdma_cfg & RXDMA_CFG_ENABLE) == 0) {\n+ trace_sungem_rx_txdma_disabled();\n+ return 0;\n+ }\n+\n+ /* Check RX availability */\n+ kick = s->rxdmaregs[RXDMA_KICK >> 2];\n+ done = s->rxdmaregs[RXDMA_DONE >> 2];\n+ full = sungem_rx_full(s, kick, done);\n+\n+ trace_sungem_rx_check(!full, kick, done);\n+\n+ return !full;\n+}\n+\n+enum {\n+ rx_no_match,\n+ rx_match_promisc,\n+ rx_match_bcast,\n+ rx_match_allmcast,\n+ rx_match_mcast,\n+ rx_match_mac,\n+ rx_match_altmac,\n+};\n+\n+static int sungem_check_rx_mac(SunGEMState *s, const uint8_t *mac, uint32_t crc)\n+{\n+ uint32_t rxcfg = s->macregs[MAC_RXCFG >> 2];\n+ uint32_t mac0, mac1, mac2;\n+\n+ /* Promisc enabled ? */\n+ if (rxcfg & MAC_RXCFG_PROM) {\n+ return rx_match_promisc;\n+ }\n+\n+ /* Format MAC address into dwords */\n+ mac0 = (mac[4] << 8) | mac[5];\n+ mac1 = (mac[2] << 8) | mac[3];\n+ mac2 = (mac[0] << 8) | mac[1];\n+\n+ trace_sungem_rx_mac_check(mac0, mac1, mac2);\n+\n+ /* Is this a broadcast frame ? */\n+ if (mac0 == 0xffff && mac1 == 0xffff && mac2 == 0xffff) {\n+ return rx_match_bcast;\n+ }\n+\n+ /* TODO: Implement address filter registers (or we don't care ?) */\n+\n+ /* Is this a multicast frame ? */\n+ if (mac[0] & 1) {\n+ trace_sungem_rx_mac_multicast();\n+\n+ /* Promisc group enabled ? */\n+ if (rxcfg & MAC_RXCFG_PGRP) {\n+ return rx_match_allmcast;\n+ }\n+\n+ /* TODO: Check MAC control frames (or we don't care) ? */\n+\n+ /* Check hash filter (somebody check that's correct ?) */\n+ if (rxcfg & MAC_RXCFG_HFE) {\n+ uint32_t hash, idx;\n+\n+ crc >>= 24;\n+ idx = (crc >> 2) & 0x3c;\n+ hash = s->macregs[(MAC_HASH0 + idx) >> 2];\n+ if (hash & (1 << (15 - (crc & 0xf)))) {\n+ return rx_match_mcast;\n+ }\n+ }\n+ return rx_no_match;\n+ }\n+\n+ /* Main MAC check */\n+ trace_sungem_rx_mac_compare(s->macregs[MAC_ADDR0 >> 2],\n+ s->macregs[MAC_ADDR1 >> 2],\n+ s->macregs[MAC_ADDR2 >> 2]);\n+\n+ if (mac0 == s->macregs[MAC_ADDR0 >> 2] &&\n+ mac1 == s->macregs[MAC_ADDR1 >> 2] &&\n+ mac2 == s->macregs[MAC_ADDR2 >> 2]) {\n+ return rx_match_mac;\n+ }\n+\n+ /* Alt MAC check */\n+ if (mac0 == s->macregs[MAC_ADDR3 >> 2] &&\n+ mac1 == s->macregs[MAC_ADDR4 >> 2] &&\n+ mac2 == s->macregs[MAC_ADDR5 >> 2]) {\n+ return rx_match_altmac;\n+ }\n+\n+ return rx_no_match;\n+}\n+\n+static ssize_t sungem_receive(NetClientState *nc, const uint8_t *buf,\n+ size_t size)\n+{\n+ SunGEMState *s = qemu_get_nic_opaque(nc);\n+ PCIDevice *d = PCI_DEVICE(s);\n+ uint32_t mac_crc, done, kick, max_fsize;\n+ uint32_t fcs_size, ints, rxdma_cfg, rxmac_cfg, csum, coff;\n+ uint8_t smallbuf[60];\n+ struct gem_rxd desc;\n+ uint64_t dbase, baddr;\n+ unsigned int rx_cond;\n+\n+ trace_sungem_rx_packet(size);\n+\n+ rxmac_cfg = s->macregs[MAC_RXCFG >> 2];\n+ rxdma_cfg = s->rxdmaregs[RXDMA_CFG >> 2];\n+ max_fsize = s->macregs[MAC_MAXFSZ >> 2] & 0x7fff;\n+\n+ /* If MAC or DMA disabled, can't receive */\n+ if (!(rxdma_cfg & RXDMA_CFG_ENABLE) ||\n+ !(rxmac_cfg & MAC_RXCFG_ENAB)) {\n+ trace_sungem_rx_disabled();\n+ return 0;\n+ }\n+\n+ /* Size adjustment for FCS */\n+ if (rxmac_cfg & MAC_RXCFG_SFCS) {\n+ fcs_size = 0;\n+ } else {\n+ fcs_size = 4;\n+ }\n+\n+ /* Discard frame smaller than a MAC or larger than max frame size\n+ * (when accounting for FCS)\n+ */\n+ if (size < 6 || (size + 4) > max_fsize) {\n+ trace_sungem_rx_bad_frame_size(size);\n+ /* XXX Increment error statistics ? */\n+ return size;\n+ }\n+\n+ /* We don't drop too small frames since we get them in qemu, we pad\n+ * them instead. We should probably use the min frame size register\n+ * but I don't want to use a variable size staging buffer and I\n+ * know both MacOS and Linux use the default 64 anyway. We use 60\n+ * here to account for the non-existent FCS.\n+ */\n+ if (size < 60) {\n+ memcpy(smallbuf, buf, size);\n+ memset(&smallbuf[size], 0, 60 - size);\n+ buf = smallbuf;\n+ size = 60;\n+ }\n+\n+ /* Get MAC crc */\n+ mac_crc = crc32(~0, buf, 6);\n+\n+ /* Packet isn't for me ? */\n+ rx_cond = sungem_check_rx_mac(s, buf, mac_crc);\n+ if (rx_cond == rx_no_match) {\n+ /* Just drop it */\n+ trace_sungem_rx_unmatched();\n+ return size;\n+ }\n+\n+ /* Get ring pointers */\n+ kick = s->rxdmaregs[RXDMA_KICK >> 2] & s->rx_mask;\n+ done = s->rxdmaregs[RXDMA_DONE >> 2] & s->rx_mask;\n+\n+ trace_sungem_rx_process(done, kick, s->rx_mask + 1);\n+\n+ /* Ring full ? Can't receive */\n+ if (sungem_rx_full(s, kick, done)) {\n+ trace_sungem_rx_ringfull();\n+ return 0;\n+ }\n+\n+ /* Note: The real GEM will fetch descriptors in blocks of 4,\n+ * for now we handle them one at a time, I think the driver will\n+ * cope\n+ */\n+\n+ dbase = s->rxdmaregs[RXDMA_DBHI >> 2];\n+ dbase = (dbase << 32) | s->rxdmaregs[RXDMA_DBLOW >> 2];\n+\n+ /* Read the next descriptor */\n+ pci_dma_read(d, dbase + done * sizeof(desc), &desc, sizeof(desc));\n+\n+ trace_sungem_rx_desc(le64_to_cpu(desc.status_word),\n+ le64_to_cpu(desc.buffer));\n+\n+ /* Effective buffer address */\n+ baddr = le64_to_cpu(desc.buffer) & ~7ull;\n+ baddr |= (rxdma_cfg & RXDMA_CFG_FBOFF) >> 10;\n+\n+ /* Write buffer out */\n+ pci_dma_write(d, baddr, buf, size);\n+\n+ if (fcs_size) {\n+ /* Should we add an FCS ? Linux doesn't ask us to strip it,\n+ * however I believe nothing checks it... For now we just\n+ * do nothing. It's faster this way.\n+ */\n+ }\n+\n+ /* Calculate the checksum */\n+ coff = (rxdma_cfg & RXDMA_CFG_CSUMOFF) >> 13;\n+ csum = net_raw_checksum((uint8_t *)buf + coff, size - coff);\n+\n+ /* Build the updated descriptor */\n+ desc.status_word = (size + fcs_size) << 16;\n+ desc.status_word |= ((uint64_t)(mac_crc >> 16)) << 44;\n+ desc.status_word |= csum;\n+ if (rx_cond == rx_match_mcast) {\n+ desc.status_word |= RXDCTRL_HPASS;\n+ }\n+ if (rx_cond == rx_match_altmac) {\n+ desc.status_word |= RXDCTRL_ALTMAC;\n+ }\n+ desc.status_word = cpu_to_le64(desc.status_word);\n+\n+ pci_dma_write(d, dbase + done * sizeof(desc), &desc, sizeof(desc));\n+\n+ done = (done + 1) & s->rx_mask;\n+ s->rxdmaregs[RXDMA_DONE >> 2] = done;\n+\n+ /* XXX Unconditionally set RX interrupt for now. The interrupt\n+ * mitigation timer might well end up adding more overhead than\n+ * helping here...\n+ */\n+ ints = GREG_STAT_RXDONE;\n+ if (sungem_rx_full(s, kick, done)) {\n+ ints |= GREG_STAT_RXNOBUF;\n+ }\n+ sungem_update_status(s, ints, true);\n+\n+ return size;\n+}\n+\n+static void sungem_set_link_status(NetClientState *nc)\n+{\n+ /* We don't do anything for now as I believe none of the OSes\n+ * drivers use the MIF autopoll feature nor the PHY interrupt\n+ */\n+}\n+\n+static void sungem_update_masks(SunGEMState *s)\n+{\n+ uint32_t sz;\n+\n+ sz = 1 << (((s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_RINGSZ) >> 1) + 5);\n+ s->rx_mask = sz - 1;\n+\n+ sz = 1 << (((s->txdmaregs[TXDMA_CFG >> 2] & TXDMA_CFG_RINGSZ) >> 1) + 5);\n+ s->tx_mask = sz - 1;\n+}\n+\n+static void sungem_reset_rx(SunGEMState *s)\n+{\n+ trace_sungem_rx_reset();\n+\n+ /* XXX Do RXCFG */\n+ /* XXX Check value */\n+ s->rxdmaregs[RXDMA_FSZ >> 2] = 0x140;\n+ s->rxdmaregs[RXDMA_DONE >> 2] = 0;\n+ s->rxdmaregs[RXDMA_KICK >> 2] = 0;\n+ s->rxdmaregs[RXDMA_CFG >> 2] = 0x1000010;\n+ s->rxdmaregs[RXDMA_PTHRESH >> 2] = 0xf8;\n+ s->rxdmaregs[RXDMA_BLANK >> 2] = 0;\n+\n+ sungem_update_masks(s);\n+}\n+\n+static void sungem_reset_tx(SunGEMState *s)\n+{\n+ trace_sungem_tx_reset();\n+\n+ /* XXX Do TXCFG */\n+ /* XXX Check value */\n+ s->txdmaregs[TXDMA_FSZ >> 2] = 0x90;\n+ s->txdmaregs[TXDMA_TXDONE >> 2] = 0;\n+ s->txdmaregs[TXDMA_KICK >> 2] = 0;\n+ s->txdmaregs[TXDMA_CFG >> 2] = 0x118010;\n+\n+ sungem_update_masks(s);\n+\n+ s->tx_size = 0;\n+ s->tx_first_ctl = 0;\n+}\n+\n+static void sungem_reset_all(SunGEMState *s, bool pci_reset)\n+{\n+ trace_sungem_reset(pci_reset);\n+\n+ sungem_reset_rx(s);\n+ sungem_reset_tx(s);\n+\n+ s->gregs[GREG_IMASK >> 2] = 0xFFFFFFF;\n+ s->gregs[GREG_STAT >> 2] = 0;\n+ if (pci_reset) {\n+ uint8_t *ma = s->conf.macaddr.a;\n+\n+ s->gregs[GREG_SWRST >> 2] = 0;\n+ s->macregs[MAC_ADDR0 >> 2] = (ma[4] << 8) | ma[5];\n+ s->macregs[MAC_ADDR1 >> 2] = (ma[2] << 8) | ma[3];\n+ s->macregs[MAC_ADDR2 >> 2] = (ma[0] << 8) | ma[1];\n+ } else {\n+ s->gregs[GREG_SWRST >> 2] &= GREG_SWRST_RSTOUT;\n+ }\n+ s->mifregs[MIF_CFG >> 2] = MIF_CFG_MDI0;\n+}\n+\n+static void sungem_mii_write(SunGEMState *s, uint8_t phy_addr,\n+ uint8_t reg_addr, uint16_t val)\n+{\n+ trace_sungem_mii_write(phy_addr, reg_addr, val);\n+\n+ /* XXX TODO */\n+}\n+\n+static uint16_t __sungem_mii_read(SunGEMState *s, uint8_t phy_addr,\n+ uint8_t reg_addr)\n+{\n+ if (phy_addr != s->phy_addr) {\n+ return 0xffff;\n+ }\n+ /* Primitive emulation of a BCM5201 to please the driver,\n+ * ID is 0x00406210. TODO: Do a gigabit PHY like BCM5400\n+ */\n+ switch (reg_addr) {\n+ case MII_BMCR:\n+ return 0;\n+ case MII_PHYID1:\n+ return 0x0040;\n+ case MII_PHYID2:\n+ return 0x6210;\n+ case MII_BMSR:\n+ if (qemu_get_queue(s->nic)->link_down) {\n+ return MII_BMSR_100TX_FD | MII_BMSR_AUTONEG;\n+ } else {\n+ return MII_BMSR_100TX_FD | MII_BMSR_AN_COMP |\n+ MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;\n+ }\n+ case MII_ANLPAR:\n+ case MII_ANAR:\n+ return MII_ANLPAR_TXFD;\n+ case 0x18: /* 5201 AUX status */\n+ return 3; /* 100FD */\n+ default:\n+ return 0;\n+ };\n+}\n+static uint16_t sungem_mii_read(SunGEMState *s, uint8_t phy_addr,\n+ uint8_t reg_addr)\n+{\n+ uint16_t val;\n+\n+ val = __sungem_mii_read(s, phy_addr, reg_addr);\n+\n+ trace_sungem_mii_read(phy_addr, reg_addr, val);\n+\n+ return val;\n+}\n+\n+static uint32_t sungem_mii_op(SunGEMState *s, uint32_t val)\n+{\n+ uint8_t phy_addr, reg_addr, op;\n+\n+ /* Ignore not start of frame */\n+ if ((val >> 30) != 1) {\n+ trace_sungem_mii_invalid_sof(val >> 30);\n+ return 0xffff;\n+ }\n+ phy_addr = (val & MIF_FRAME_PHYAD) >> 23;\n+ reg_addr = (val & MIF_FRAME_REGAD) >> 18;\n+ op = (val & MIF_FRAME_OP) >> 28;\n+ switch (op) {\n+ case 1:\n+ sungem_mii_write(s, phy_addr, reg_addr, val & MIF_FRAME_DATA);\n+ return val | MIF_FRAME_TALSB;\n+ case 2:\n+ return sungem_mii_read(s, phy_addr, reg_addr) | MIF_FRAME_TALSB;\n+ default:\n+ trace_sungem_mii_invalid_op(op);\n+ }\n+ return 0xffff | MIF_FRAME_TALSB;\n+}\n+\n+static void sungem_mmio_greg_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown GREG register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_greg_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case GREG_SEBSTATE:\n+ case GREG_STAT:\n+ case GREG_STAT2:\n+ case GREG_PCIESTAT:\n+ return; /* No actual write */\n+ case GREG_IACK:\n+ val &= GREG_STAT_LATCH;\n+ s->gregs[GREG_STAT >> 2] &= ~val;\n+ sungem_eval_irq(s);\n+ return; /* No actual write */\n+ case GREG_PCIEMASK:\n+ val &= 0x7;\n+ break;\n+ }\n+\n+ s->gregs[addr >> 2] = val;\n+\n+ /* Post write action */\n+ switch (addr) {\n+ case GREG_IMASK:\n+ /* Re-evaluate interrupt */\n+ sungem_eval_irq(s);\n+ break;\n+ case GREG_SWRST:\n+ switch (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)) {\n+ case GREG_SWRST_RXRST:\n+ sungem_reset_rx(s);\n+ break;\n+ case GREG_SWRST_TXRST:\n+ sungem_reset_tx(s);\n+ break;\n+ case GREG_SWRST_RXRST | GREG_SWRST_TXRST:\n+ sungem_reset_all(s, false);\n+ }\n+ break;\n+ }\n+}\n+\n+static uint64_t sungem_mmio_greg_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr < 0x20) && !(addr >= 0x1000 && addr <= 0x1010)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown GREG register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->gregs[addr >> 2];\n+\n+ trace_sungem_mmio_greg_read(addr, val);\n+\n+ switch (addr) {\n+ case GREG_STAT:\n+ /* Side effect, clear bottom 7 bits */\n+ s->gregs[GREG_STAT >> 2] &= ~GREG_STAT_LATCH;\n+ sungem_eval_irq(s);\n+\n+ /* Inject TX completion in returned value */\n+ val = (val & ~GREG_STAT_TXNR) |\n+ (s->txdmaregs[TXDMA_TXDONE >> 2] << GREG_STAT_TXNR_SHIFT);\n+ break;\n+ case GREG_STAT2:\n+ /* Return the status reg without side effect\n+ * (and inject TX completion in returned value)\n+ */\n+ val = (s->gregs[GREG_STAT >> 2] & ~GREG_STAT_TXNR) |\n+ (s->txdmaregs[TXDMA_TXDONE >> 2] << GREG_STAT_TXNR_SHIFT);\n+ break;\n+ }\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_greg_ops = {\n+ .read = sungem_mmio_greg_read,\n+ .write = sungem_mmio_greg_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_mmio_txdma_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown TXDMA register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_txdma_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case TXDMA_TXDONE:\n+ case TXDMA_PCNT:\n+ case TXDMA_SMACHINE:\n+ case TXDMA_DPLOW:\n+ case TXDMA_DPHI:\n+ case TXDMA_FSZ:\n+ case TXDMA_FTAG:\n+ return; /* No actual write */\n+ }\n+\n+ s->txdmaregs[addr >> 2] = val;\n+\n+ /* Post write action */\n+ switch (addr) {\n+ case TXDMA_KICK:\n+ sungem_tx_kick(s);\n+ break;\n+ case TXDMA_CFG:\n+ sungem_update_masks(s);\n+ break;\n+ }\n+}\n+\n+static uint64_t sungem_mmio_txdma_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr < 0x38) && !(addr >= 0x100 && addr <= 0x118)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown TXDMA register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->txdmaregs[addr >> 2];\n+\n+ trace_sungem_mmio_txdma_read(addr, val);\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_txdma_ops = {\n+ .read = sungem_mmio_txdma_read,\n+ .write = sungem_mmio_txdma_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_mmio_rxdma_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown RXDMA register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_rxdma_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case RXDMA_DONE:\n+ case RXDMA_PCNT:\n+ case RXDMA_SMACHINE:\n+ case RXDMA_DPLOW:\n+ case RXDMA_DPHI:\n+ case RXDMA_FSZ:\n+ case RXDMA_FTAG:\n+ return; /* No actual write */\n+ }\n+\n+ s->rxdmaregs[addr >> 2] = val;\n+\n+ /* Post write action */\n+ switch (addr) {\n+ case RXDMA_KICK:\n+ trace_sungem_rx_kick(val);\n+ break;\n+ case RXDMA_CFG:\n+ sungem_update_masks(s);\n+ if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 &&\n+ (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {\n+ qemu_flush_queued_packets(qemu_get_queue(s->nic));\n+ }\n+ break;\n+ }\n+}\n+\n+static uint64_t sungem_mmio_rxdma_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr <= 0x28) && !(addr >= 0x100 && addr <= 0x120)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown RXDMA register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->rxdmaregs[addr >> 2];\n+\n+ trace_sungem_mmio_rxdma_read(addr, val);\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_rxdma_ops = {\n+ .read = sungem_mmio_rxdma_read,\n+ .write = sungem_mmio_rxdma_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_mmio_mac_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr <= 0x134)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown MAC register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_mac_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case MAC_TXRST: /* Not technically read-only but will do for now */\n+ case MAC_RXRST: /* Not technically read-only but will do for now */\n+ case MAC_TXSTAT:\n+ case MAC_RXSTAT:\n+ case MAC_CSTAT:\n+ case MAC_PATMPS:\n+ case MAC_SMACHINE:\n+ return; /* No actual write */\n+ case MAC_MINFSZ:\n+ /* 10-bits implemented */\n+ val &= 0x3ff;\n+ break;\n+ }\n+\n+ s->macregs[addr >> 2] = val;\n+\n+ /* Post write action */\n+ switch (addr) {\n+ case MAC_TXMASK:\n+ case MAC_RXMASK:\n+ case MAC_MCMASK:\n+ sungem_eval_cascade_irq(s);\n+ break;\n+ case MAC_RXCFG:\n+ sungem_update_masks(s);\n+ if ((s->macregs[MAC_RXCFG >> 2] & MAC_RXCFG_ENAB) != 0 &&\n+ (s->rxdmaregs[RXDMA_CFG >> 2] & RXDMA_CFG_ENABLE) != 0) {\n+ qemu_flush_queued_packets(qemu_get_queue(s->nic));\n+ }\n+ break;\n+ }\n+}\n+\n+static uint64_t sungem_mmio_mac_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr <= 0x134)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown MAC register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->macregs[addr >> 2];\n+\n+ trace_sungem_mmio_mac_read(addr, val);\n+\n+ switch (addr) {\n+ case MAC_TXSTAT:\n+ /* Side effect, clear all */\n+ s->macregs[addr >> 2] = 0;\n+ sungem_update_status(s, GREG_STAT_TXMAC, false);\n+ break;\n+ case MAC_RXSTAT:\n+ /* Side effect, clear all */\n+ s->macregs[addr >> 2] = 0;\n+ sungem_update_status(s, GREG_STAT_RXMAC, false);\n+ break;\n+ case MAC_CSTAT:\n+ /* Side effect, interrupt bits */\n+ s->macregs[addr >> 2] &= MAC_CSTAT_PTR;\n+ sungem_update_status(s, GREG_STAT_MAC, false);\n+ break;\n+ }\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_mac_ops = {\n+ .read = sungem_mmio_mac_read,\n+ .write = sungem_mmio_mac_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_mmio_mif_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr <= 0x1c)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown MIF register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_mif_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case MIF_STATUS:\n+ case MIF_SMACHINE:\n+ return; /* No actual write */\n+ case MIF_CFG:\n+ /* Maintain the RO MDI bits to advertize an MDIO PHY on MDI0 */\n+ val &= ~MIF_CFG_MDI1;\n+ val |= MIF_CFG_MDI0;\n+ break;\n+ }\n+\n+ s->mifregs[addr >> 2] = val;\n+\n+ /* Post write action */\n+ switch (addr) {\n+ case MIF_FRAME:\n+ s->mifregs[addr >> 2] = sungem_mii_op(s, val);\n+ break;\n+ }\n+}\n+\n+static uint64_t sungem_mmio_mif_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr <= 0x1c)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown MIF register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->mifregs[addr >> 2];\n+\n+ trace_sungem_mmio_mif_read(addr, val);\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_mif_ops = {\n+ .read = sungem_mmio_mif_read,\n+ .write = sungem_mmio_mif_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_mmio_pcs_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+\n+ if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Write to unknown PCS register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return;\n+ }\n+\n+ trace_sungem_mmio_pcs_write(addr, val);\n+\n+ /* Pre-write filter */\n+ switch (addr) {\n+ /* Read only registers */\n+ case PCS_MIISTAT:\n+ case PCS_ISTAT:\n+ case PCS_SSTATE:\n+ return; /* No actual write */\n+ }\n+\n+ s->pcsregs[addr >> 2] = val;\n+}\n+\n+static uint64_t sungem_mmio_pcs_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ SunGEMState *s = opaque;\n+ uint32_t val;\n+\n+ if (!(addr <= 0x18) && !(addr >= 0x50 && addr <= 0x5c)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"Read from unknown PCS register 0x%\"HWADDR_PRIx\"\\n\",\n+ addr);\n+ return 0;\n+ }\n+\n+ val = s->pcsregs[addr >> 2];\n+\n+ trace_sungem_mmio_pcs_read(addr, val);\n+\n+ return val;\n+}\n+\n+static const MemoryRegionOps sungem_mmio_pcs_ops = {\n+ .read = sungem_mmio_pcs_read,\n+ .write = sungem_mmio_pcs_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n+static void sungem_uninit(PCIDevice *dev)\n+{\n+ SunGEMState *s = SUNGEM(dev);\n+\n+ qemu_del_nic(s->nic);\n+}\n+\n+static NetClientInfo net_sungem_info = {\n+ .type = NET_CLIENT_DRIVER_NIC,\n+ .size = sizeof(NICState),\n+ .can_receive = sungem_can_receive,\n+ .receive = sungem_receive,\n+ .link_status_changed = sungem_set_link_status,\n+};\n+\n+static void sungem_realize(PCIDevice *pci_dev, Error **errp)\n+{\n+ DeviceState *dev = DEVICE(pci_dev);\n+ SunGEMState *s = SUNGEM(pci_dev);\n+ uint8_t *pci_conf;\n+\n+ pci_conf = pci_dev->config;\n+\n+ pci_set_word(pci_conf + PCI_STATUS,\n+ PCI_STATUS_FAST_BACK |\n+ PCI_STATUS_DEVSEL_MEDIUM |\n+ PCI_STATUS_66MHZ);\n+\n+ pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);\n+ pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);\n+\n+ pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */\n+ pci_conf[PCI_MIN_GNT] = 0x40;\n+ pci_conf[PCI_MAX_LAT] = 0x40;\n+\n+ sungem_reset_all(s, true);\n+ memory_region_init(&s->sungem, OBJECT(s), \"sungem\", SUNGEM_MMIO_SIZE);\n+\n+ memory_region_init_io(&s->greg, OBJECT(s), &sungem_mmio_greg_ops, s,\n+ \"sungem.greg\", SUNGEM_MMIO_GREG_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0, &s->greg);\n+\n+ memory_region_init_io(&s->txdma, OBJECT(s), &sungem_mmio_txdma_ops, s,\n+ \"sungem.txdma\", SUNGEM_MMIO_TXDMA_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0x2000, &s->txdma);\n+\n+ memory_region_init_io(&s->rxdma, OBJECT(s), &sungem_mmio_rxdma_ops, s,\n+ \"sungem.rxdma\", SUNGEM_MMIO_RXDMA_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0x4000, &s->rxdma);\n+\n+ memory_region_init_io(&s->mac, OBJECT(s), &sungem_mmio_mac_ops, s,\n+ \"sungem.mac\", SUNGEM_MMIO_MAC_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0x6000, &s->mac);\n+\n+ memory_region_init_io(&s->mif, OBJECT(s), &sungem_mmio_mif_ops, s,\n+ \"sungem.mif\", SUNGEM_MMIO_MIF_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0x6200, &s->mif);\n+\n+ memory_region_init_io(&s->pcs, OBJECT(s), &sungem_mmio_pcs_ops, s,\n+ \"sungem.pcs\", SUNGEM_MMIO_PCS_SIZE);\n+ memory_region_add_subregion(&s->sungem, 0x9000, &s->pcs);\n+\n+ pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->sungem);\n+\n+ qemu_macaddr_default_if_unset(&s->conf.macaddr);\n+ s->nic = qemu_new_nic(&net_sungem_info, &s->conf,\n+ object_get_typename(OBJECT(dev)),\n+ dev->id, s);\n+ qemu_format_nic_info_str(qemu_get_queue(s->nic),\n+ s->conf.macaddr.a);\n+}\n+\n+static void sungem_reset(DeviceState *dev)\n+{\n+ SunGEMState *s = SUNGEM(dev);\n+\n+ sungem_reset_all(s, true);\n+}\n+\n+static void sungem_instance_init(Object *obj)\n+{\n+ SunGEMState *s = SUNGEM(obj);\n+\n+ device_add_bootindex_property(obj, &s->conf.bootindex,\n+ \"bootindex\", \"/ethernet-phy@0\",\n+ DEVICE(obj), NULL);\n+}\n+\n+static Property sungem_properties[] = {\n+ DEFINE_NIC_PROPERTIES(SunGEMState, conf),\n+ /* Phy address should be 0 for most Apple machines except\n+ * for K2 in which case it's 1. Will be set by a machine\n+ * override.\n+ */\n+ DEFINE_PROP_UINT32(\"phy_addr\", SunGEMState, phy_addr, 0),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static const VMStateDescription vmstate_sungem = {\n+ .name = \"sungem\",\n+ .version_id = 0,\n+ .minimum_version_id = 0,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_PCI_DEVICE(pdev, SunGEMState),\n+ VMSTATE_MACADDR(conf.macaddr, SunGEMState),\n+ VMSTATE_UINT32(phy_addr, SunGEMState),\n+ VMSTATE_UINT32_ARRAY(gregs, SunGEMState, (SUNGEM_MMIO_GREG_SIZE >> 2)),\n+ VMSTATE_UINT32_ARRAY(txdmaregs, SunGEMState,\n+ (SUNGEM_MMIO_TXDMA_SIZE >> 2)),\n+ VMSTATE_UINT32_ARRAY(rxdmaregs, SunGEMState,\n+ (SUNGEM_MMIO_RXDMA_SIZE >> 2)),\n+ VMSTATE_UINT32_ARRAY(macregs, SunGEMState, (SUNGEM_MMIO_MAC_SIZE >> 2)),\n+ VMSTATE_UINT32_ARRAY(mifregs, SunGEMState, (SUNGEM_MMIO_MIF_SIZE >> 2)),\n+ VMSTATE_UINT32_ARRAY(pcsregs, SunGEMState, (SUNGEM_MMIO_PCS_SIZE >> 2)),\n+ VMSTATE_UINT32(rx_mask, SunGEMState),\n+ VMSTATE_UINT32(tx_mask, SunGEMState),\n+ VMSTATE_UINT8_ARRAY(tx_data, SunGEMState, MAX_PACKET_SIZE),\n+ VMSTATE_UINT32(tx_size, SunGEMState),\n+ VMSTATE_UINT64(tx_first_ctl, SunGEMState),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void sungem_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);\n+\n+ k->realize = sungem_realize;\n+ k->exit = sungem_uninit;\n+ k->vendor_id = PCI_VENDOR_ID_APPLE;\n+ k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_GMAC;\n+ k->revision = 0x01;\n+ k->class_id = PCI_CLASS_NETWORK_ETHERNET;\n+ dc->vmsd = &vmstate_sungem;\n+ dc->reset = sungem_reset;\n+ dc->props = sungem_properties;\n+ set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);\n+}\n+\n+static const TypeInfo sungem_info = {\n+ .name = TYPE_SUNGEM,\n+ .parent = TYPE_PCI_DEVICE,\n+ .instance_size = sizeof(SunGEMState),\n+ .class_init = sungem_class_init,\n+ .instance_init = sungem_instance_init,\n+};\n+\n+static void sungem_register_types(void)\n+{\n+ type_register_static(&sungem_info);\n+}\n+\n+type_init(sungem_register_types)\ndiff --git a/hw/net/trace-events b/hw/net/trace-events\nindex 27e5482..5f816ef 100644\n--- a/hw/net/trace-events\n+++ b/hw/net/trace-events\n@@ -278,3 +278,47 @@ spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) \"H_SEND_LOG\n spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) \"rxbufs = %\"PRIu32\n spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) \" buf desc: 0x%\"PRIx64\n spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) \"%d buffers, total length 0x%x\"\n+\n+# hw/net/sungem.c\n+sungem_tx_checksum(uint16_t start, uint16_t off) \"TX checksumming from byte %d, inserting at %d\"\n+sungem_tx_checksum_oob(void) \"TX checksum out of packet bounds\"\n+sungem_tx_unfinished(void) \"TX packet started without finishing the previous one\"\n+sungem_tx_overflow(void) \"TX packet queue overflow\"\n+sungem_tx_finished(uint32_t size) \"TX completing %\"PRIu32 \" bytes packet\"\n+sungem_tx_kick(void) \"TX Kick...\"\n+sungem_tx_disabled(void) \"TX not enabled\"\n+sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) \"TX processing comp=%\"PRIu32\", kick=%\"PRIu32\" out of %\"PRIu32\n+sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) \"TX desc %\"PRIu32 \": 0x%\"PRIx64\" 0x%\"PRIx64\n+sungem_tx_reset(void) \"TX reset\"\n+sungem_rx_mac_disabled(void) \"Check RX MAC disabled\"\n+sungem_rx_txdma_disabled(void) \"Check RX TXDMA disabled\"\n+sungem_rx_check(bool full, uint32_t kick, uint32_t done) \"Check RX %d (kick=%\"PRIu32\", done=%\"PRIu32\")\"\n+sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) \"Word MAC: 0x%\"PRIx32\" 0x%\"PRIx32\" 0x%\"PRIx32\n+sungem_rx_mac_multicast(void) \"Multicast\"\n+sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) \"Compare MAC to 0x%\"PRIx32\" 0x%\"PRIx32\" 0x%\"PRIx32\"..\"\n+sungem_rx_packet(size_t size) \"RX got %zu bytes packet\"\n+sungem_rx_disabled(void) \"RX not enabled\"\n+sungem_rx_bad_frame_size(size_t size) \"RX bad frame size %zu, dropped\"\n+sungem_rx_unmatched(void) \"No match, dropped\"\n+sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) \"RX processing done=%\"PRIu32\", kick=%\"PRIu32\" out of %\"PRIu32\n+sungem_rx_ringfull(void) \"RX ring full\"\n+sungem_rx_desc(uint64_t control, uint64_t buffer) \"RX desc: 0x%\"PRIx64\" 0x%\"PRIx64\n+sungem_rx_reset(void) \"RX reset\"\n+sungem_rx_kick(uint64_t val) \"RXDMA_KICK written to %\"PRIu64\n+sungem_reset(bool pci_reset) \"Full reset (PCI:%d)\"\n+sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) \"MII write addr 0x%x reg 0x%02x val 0x%04x\"\n+sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) \"MII read addr 0x%x reg 0x%02x val 0x%04x\"\n+sungem_mii_invalid_sof(uint32_t val) \"MII op, invalid SOF field 0x%\"PRIx32\n+sungem_mii_invalid_op(uint8_t op) \"MII op, invalid op field 0x%x\"\n+sungem_mmio_greg_write(uint64_t addr, uint64_t val) \"MMIO greg write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_greg_read(uint64_t addr, uint64_t val) \"MMIO greg read from 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_txdma_write(uint64_t addr, uint64_t val) \"MMIO txdma write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_txdma_read(uint64_t addr, uint64_t val) \"MMIO txdma read from 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) \"MMIO rxdma write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) \"MMIO rxdma read from 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_mac_write(uint64_t addr, uint64_t val) \"MMIO mac write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_mac_read(uint64_t addr, uint64_t val) \"MMIO mac read from 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_mif_write(uint64_t addr, uint64_t val) \"MMIO mif write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_mif_read(uint64_t addr, uint64_t val) \"MMIO mif read from 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_pcs_write(uint64_t addr, uint64_t val) \"MMIO pcs write to 0x%\"PRIx64\" val=0x%\"PRIx64\n+sungem_mmio_pcs_read(uint64_t addr, uint64_t val) \"MMIO pcs read from 0x%\"PRIx64\" val=0x%\"PRIx64\ndiff --git a/hw/pci/pci.c b/hw/pci/pci.c\nindex 26f346d..9947fc5 100644\n--- a/hw/pci/pci.c\n+++ b/hw/pci/pci.c\n@@ -1803,6 +1803,7 @@ static const char * const pci_nic_models[] = {\n \"e1000\",\n \"pcnet\",\n \"virtio\",\n+ \"sungem\",\n NULL\n };\n \n@@ -1815,6 +1816,7 @@ static const char * const pci_nic_names[] = {\n \"e1000\",\n \"pcnet\",\n \"virtio-net-pci\",\n+ \"sungem\",\n NULL\n };\n \ndiff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h\nindex 3752ddc..b9c2bad 100644\n--- a/include/hw/pci/pci_ids.h\n+++ b/include/hw/pci/pci_ids.h\n@@ -183,6 +183,7 @@\n #define PCI_VENDOR_ID_APPLE 0x106b\n #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020\n #define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b\n+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021\n \n #define PCI_VENDOR_ID_SUN 0x108e\n #define PCI_DEVICE_ID_SUN_EBUS 0x1000\n", "prefixes": [ "PATCHv2", "1/1" ] }