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GET /api/patches/810721/?format=api
{ "id": 810721, "url": "http://patchwork.ozlabs.org/api/patches/810721/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-22-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-22-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:01", "name": "[PULL,21/32] target/arm: [tcg, a64] Port to breakpoint_check", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2fb53dd1d422e7ea19cb16222999e4f266f16aec", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-22-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810721/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810721/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"hETCc4cw\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTf260V6z9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:32:58 +1000 (AEST)", "from localhost ([::1]:37080 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpdG4-0005Oo-OA\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:32:56 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41906)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqm-0000LW-Qf\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:58 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqi-0002cX-CW\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400", "from mail-pf0-x234.google.com ([2607:f8b0:400e:c00::234]:34783)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqi-0002bQ-6n\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:44 -0400", "by mail-pf0-x234.google.com with SMTP id m1so13485760pfk.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:44 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.41\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=iQeSsig0LrUqKt2taUtiV4ym+Ibb3h0DSczL0zy/jlI=;\n\tb=hETCc4cw7yVmnPV8rZJwmsDQtApG2o8yEaFLh4XeHkHvM4aL+7k/O7DjcO2POnhINF\n\tmbpua6C7x4p/g5cZtt7GQUrgN1DxwggNrUT5zlcU1uydyf2ft8Mlp1cP2HUKZLAAOzKo\n\tvSWLgphpWlApLM7yXkGQa4EfL9rJPvv1gal+4=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=iQeSsig0LrUqKt2taUtiV4ym+Ibb3h0DSczL0zy/jlI=;\n\tb=d+hVqhNTckxK9OqTuUR6zv3a4ZUEmaOKO7zhAZGH+Ics/GXafaTkiIqMh1qWmcLibT\n\tiV7KkvkV+ZMjWHS+LhfGWimVO3yrKcJrMHntzdTqWu6xMlxVzuz4WUJJyYslhUMkWpVZ\n\tRm5ylIZNapxyT5G4vcm0IFzw1U6RSBx+Lt816OnZkb5F5PmbqvMBGlLg0lHOuMNr+eXn\n\tFIWth8Le6hG1rfmeuP138DkoPIPOgp5Mp9ATBht0I1dmeDRglaUTC55hw9Ubx+ezFys+\n\tPgzprg7mr4kMZJH8FeWq1yYOOi5HN40bucC3RkyzA0Jfp5zsmHfHIHBDJEn9BGjP/1Kt\n\tDMEA==", "X-Gm-Message-State": "AHPjjUgKD+O9X5UMYFNh06ipK9dtQzCzpGhNM+iG/XMFUXElMqFl2tk5\n\tzJEXKD5w1/NFlqf13YoH2w==", "X-Google-Smtp-Source": "ADKCNb7CnWHxlRZxLds7i6fJCeqa632A5C1gR7kMrb5beaXuP8lI7FrdGKC7lIsM1W9nNVr/6YcGFw==", "X-Received": "by 10.99.109.142 with SMTP id i136mr8073200pgc.353.1504714003003;\n\tWed, 06 Sep 2017 09:06:43 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:01 -0700", "Message-Id": "<20170906160612.22769-22-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::234", "Subject": "[Qemu-devel] [PULL 21/32] target/arm: [tcg,\n\ta64] Port to breakpoint_check", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nMessage-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan>\n[rth: Use DISAS_TOO_MANY for \"execute only one more\" after bp.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++----------------\n 1 file changed, 31 insertions(+), 17 deletions(-)", "diff": "diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex 1eab10696c..e94198280d 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11267,6 +11267,30 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n tcg_gen_insn_start(dc->pc, 0, 0);\n }\n \n+static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+ if (bp->flags & BP_CPU) {\n+ gen_a64_set_pc_im(dc->pc);\n+ gen_helper_check_breakpoints(cpu_env);\n+ /* End the TB early; it likely won't be executed */\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else {\n+ gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n+ /* The address covered by the breakpoint must be\n+ included in [tb->pc, tb->pc + tb->size) in order\n+ to for it to be properly cleared -- thus we\n+ increment the PC here so that the logic setting\n+ tb->size below does the right thing. */\n+ dc->pc += 4;\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ }\n+\n+ return true;\n+}\n+\n void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n TranslationBlock *tb)\n {\n@@ -11303,25 +11327,15 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\n QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->pc) {\n- if (bp->flags & BP_CPU) {\n- gen_a64_set_pc_im(dc->pc);\n- gen_helper_check_breakpoints(cpu_env);\n- /* End the TB early; it likely won't be executed */\n- dc->base.is_jmp = DISAS_UPDATE;\n- } else {\n- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n- /* The address covered by the breakpoint must be\n- included in [dc->base.tb->pc, dc->base.tb->pc + dc->base.tb->size) in order\n- to for it to be properly cleared -- thus we\n- increment the PC here so that the logic setting\n- dc->base.tb->size below does the right thing. */\n- dc->pc += 4;\n- goto done_generating;\n+ if (bp->pc == dc->base.pc_next) {\n+ if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n }\n- break;\n }\n }\n+ if (dc->base.is_jmp > DISAS_TOO_MANY) {\n+ break;\n+ }\n }\n \n if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) {\n@@ -11392,6 +11406,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n } else {\n switch (dc->base.is_jmp) {\n case DISAS_NEXT:\n+ case DISAS_TOO_MANY:\n gen_goto_tb(dc, 1, dc->pc);\n break;\n case DISAS_JUMP:\n@@ -11429,7 +11444,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n }\n }\n \n-done_generating:\n gen_tb_end(tb, dc->base.num_insns);\n \n #ifdef DEBUG_DISAS\n", "prefixes": [ "PULL", "21/32" ] }