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GET /api/patches/810720/?format=api
{ "id": 810720, "url": "http://patchwork.ozlabs.org/api/patches/810720/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-23-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-23-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:02", "name": "[PULL,22/32] target/arm: [tcg] Port to translate_insn", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5f02cf339732e618413bb4bed355b112c12d1473", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-23-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810720/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810720/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"XCaqWd0/\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTbd60Mgz9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:30:53 +1000 (AEST)", "from localhost ([::1]:37068 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpdE3-0003qn-SH\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:30:51 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41915)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqn-0000MH-BZ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:55 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqk-0002fj-0s\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:49 -0400", "from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:35580)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqj-0002dc-Ml\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:45 -0400", "by mail-pg0-x22d.google.com with SMTP id 188so12738604pgb.2\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:45 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=Tmhd7lJTCptCpYf1L1lrkBjfQN41pZppSXIWh62yW1E=;\n\tb=XCaqWd0/hr5vjFWUqqmiVMsr9ot7IdCA+NTNNeHf/6Oo5WvqEd1bRxYraEVzf2wVOz\n\tEOj9XTa5ZlZKVLu1eDy1j5gxy+q2//O3Koxdh5hnZLVgG3QG3DrNZJH+C6/QC3nC2II3\n\t3IJ1e+W9iYNl7rrUWmh4hU0jW3DHc0H+KklxM=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=Tmhd7lJTCptCpYf1L1lrkBjfQN41pZppSXIWh62yW1E=;\n\tb=ljTnK1lF/py/drcXvuVLLgZ0e8yOORWyheqPpsdsgzlsvWX1XhEnTCGFRuyjBuJJaM\n\tFOGUobCDib1PHFyBc25sL6qSxjEEAdxfn/PVhqqhQEiKeqK5hBa9PHzM8Uypmsxxy4f5\n\tROylJQMxqDaKYl8VQZhB/7Hdb10ShqDPS71iNaBSkvr/zQ6mxy0IBZFwF2La4Wi89pWd\n\tNSegH9yqKzc9BppcJe+BXeWL9gHJi8GIL/6qVwI9kX/wKJf01AcP5uWZFs8Hzq+X8ehr\n\tvMBXP1lKgMvZMMcJ6Oj0eLzBCB8HSyIYrdiLDwmaCnu0ZVZmmw/0hauwFPMNEQ67i/3W\n\tWHpQ==", "X-Gm-Message-State": "AHPjjUgqYgXsSW7AL2+tgYrEjFkEgY0F7vgA0nbwFTk5kJJ1OzL5488r\n\tf3WuyIJUYt1EQGLafv8yfw==", "X-Google-Smtp-Source": "ADKCNb7tLq93Qz5aZWCd8RbFy9EJa6dJTf2LfOxrdUVMHoDwiUw3ifHE2p6EhjduMmkwSVFmd0Z9hA==", "X-Received": "by 10.98.35.210 with SMTP id q79mr7817950pfj.340.1504714004230; \n\tWed, 06 Sep 2017 09:06:44 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:02 -0700", "Message-Id": "<20170906160612.22769-23-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22d", "Subject": "[Qemu-devel] [PULL 22/32] target/arm: [tcg] Port to translate_insn", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nMessage-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan>\n[rth: Adjust for translate_insn interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.h | 1 +\n target/arm/translate.c | 165 +++++++++++++++++++++++++++----------------------\n 2 files changed, 91 insertions(+), 75 deletions(-)", "diff": "diff --git a/target/arm/translate.h b/target/arm/translate.h\nindex a804ff65ac..e8dcec51ac 100644\n--- a/target/arm/translate.h\n+++ b/target/arm/translate.h\n@@ -9,6 +9,7 @@ typedef struct DisasContext {\n DisasContextBase base;\n \n target_ulong pc;\n+ target_ulong next_page_start;\n uint32_t insn;\n /* Nonzero if this instruction has been conditionally skipped. */\n int condjmp;\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 2f5f65310d..5737299943 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11880,6 +11880,8 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,\n dc->is_ldex = false;\n dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */\n \n+ dc->next_page_start =\n+ (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n \n cpu_F0s = tcg_temp_new_i32();\n cpu_F1s = tcg_temp_new_i32();\n@@ -11973,14 +11975,93 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n return true;\n }\n \n+static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUARMState *env = cpu->env_ptr;\n+\n+#ifdef CONFIG_USER_ONLY\n+ /* Intercept jump to the magic kernel page. */\n+ if (dc->pc >= 0xffff0000) {\n+ /* We always get here via a jump, so know we are not in a\n+ conditional execution block. */\n+ gen_exception_internal(EXCP_KERNEL_TRAP);\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ return;\n+ }\n+#endif\n+\n+ if (dc->ss_active && !dc->pstate_ss) {\n+ /* Singlestep state is Active-pending.\n+ * If we're in this state at the start of a TB then either\n+ * a) we just took an exception to an EL which is being debugged\n+ * and this is the first insn in the exception handler\n+ * b) debug exceptions were masked and we just unmasked them\n+ * without changing EL (eg by clearing PSTATE.D)\n+ * In either case we're going to take a swstep exception in the\n+ * \"did not step an insn\" case, and so the syndrome ISV and EX\n+ * bits should be zero.\n+ */\n+ assert(dc->base.num_insns == 1);\n+ gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n+ default_exception_el(dc));\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ return;\n+ }\n+\n+ if (dc->thumb) {\n+ disas_thumb_insn(env, dc);\n+ if (dc->condexec_mask) {\n+ dc->condexec_cond = (dc->condexec_cond & 0xe)\n+ | ((dc->condexec_mask >> 4) & 1);\n+ dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;\n+ if (dc->condexec_mask == 0) {\n+ dc->condexec_cond = 0;\n+ }\n+ }\n+ } else {\n+ unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);\n+ dc->pc += 4;\n+ disas_arm_insn(dc, insn);\n+ }\n+\n+ if (dc->condjmp && !dc->base.is_jmp) {\n+ gen_set_label(dc->condlabel);\n+ dc->condjmp = 0;\n+ }\n+\n+ if (dc->base.is_jmp == DISAS_NEXT) {\n+ /* Translation stops when a conditional branch is encountered.\n+ * Otherwise the subsequent code could get translated several times.\n+ * Also stop translation when a page boundary is reached. This\n+ * ensures prefetch aborts occur at the right place. */\n+\n+ if (is_singlestepping(dc)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ } else if ((dc->pc >= dc->next_page_start) ||\n+ ((dc->pc >= dc->next_page_start - 3) &&\n+ insn_crosses_page(env, dc))) {\n+ /* We want to stop the TB if the next insn starts in a new page,\n+ * or if it spans between this page and the next. This means that\n+ * if we're looking at the last halfword in the page we need to\n+ * see if it's a 16-bit Thumb insn (which will fit in this TB)\n+ * or a 32-bit Thumb insn (which won't).\n+ * This is to avoid generating a silly TB with a single 16-bit insn\n+ * in it at the end of this page (which would execute correctly\n+ * but isn't very efficient).\n+ */\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ }\n+\n+ dc->base.pc_next = dc->pc;\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n- CPUARMState *env = cs->env_ptr;\n DisasContext dc1, *dc = &dc1;\n- target_ulong next_page_start;\n int max_insns;\n- bool end_of_page;\n \n /* generate intermediate code */\n \n@@ -11999,7 +12080,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->base.num_insns = 0;\n dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n- next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -12036,83 +12116,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_io_start();\n }\n \n-#ifdef CONFIG_USER_ONLY\n- /* Intercept jump to the magic kernel page. */\n- if (dc->pc >= 0xffff0000) {\n- /* We always get here via a jump, so know we are not in a\n- conditional execution block. */\n- gen_exception_internal(EXCP_KERNEL_TRAP);\n- dc->base.is_jmp = DISAS_NORETURN;\n- break;\n- }\n-#endif\n-\n- if (dc->ss_active && !dc->pstate_ss) {\n- /* Singlestep state is Active-pending.\n- * If we're in this state at the start of a TB then either\n- * a) we just took an exception to an EL which is being debugged\n- * and this is the first insn in the exception handler\n- * b) debug exceptions were masked and we just unmasked them\n- * without changing EL (eg by clearing PSTATE.D)\n- * In either case we're going to take a swstep exception in the\n- * \"did not step an insn\" case, and so the syndrome ISV and EX\n- * bits should be zero.\n- */\n- assert(dc->base.num_insns == 1);\n- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n- default_exception_el(dc));\n- dc->base.is_jmp = DISAS_NORETURN;\n- break;\n- }\n-\n- if (dc->thumb) {\n- disas_thumb_insn(env, dc);\n- if (dc->condexec_mask) {\n- dc->condexec_cond = (dc->condexec_cond & 0xe)\n- | ((dc->condexec_mask >> 4) & 1);\n- dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;\n- if (dc->condexec_mask == 0) {\n- dc->condexec_cond = 0;\n- }\n- }\n- } else {\n- unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);\n- dc->pc += 4;\n- disas_arm_insn(dc, insn);\n- }\n-\n- if (dc->condjmp && !dc->base.is_jmp) {\n- gen_set_label(dc->condlabel);\n- dc->condjmp = 0;\n- }\n+ arm_tr_translate_insn(&dc->base, cs);\n \n if (tcg_check_temp_count()) {\n fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n dc->pc);\n }\n \n- /* Translation stops when a conditional branch is encountered.\n- * Otherwise the subsequent code could get translated several times.\n- * Also stop translation when a page boundary is reached. This\n- * ensures prefetch aborts occur at the right place. */\n-\n- /* We want to stop the TB if the next insn starts in a new page,\n- * or if it spans between this page and the next. This means that\n- * if we're looking at the last halfword in the page we need to\n- * see if it's a 16-bit Thumb insn (which will fit in this TB)\n- * or a 32-bit Thumb insn (which won't).\n- * This is to avoid generating a silly TB with a single 16-bit insn\n- * in it at the end of this page (which would execute correctly\n- * but isn't very efficient).\n- */\n- end_of_page = (dc->pc >= next_page_start) ||\n- ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));\n-\n- } while (!dc->base.is_jmp && !tcg_op_buf_full() &&\n- !is_singlestepping(dc) &&\n- !singlestep &&\n- !end_of_page &&\n- dc->base.num_insns < max_insns);\n+ if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n+ dc->base.num_insns >= max_insns)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ } while (!dc->base.is_jmp);\n \n if (tb->cflags & CF_LAST_IO) {\n if (dc->condjmp) {\n", "prefixes": [ "PULL", "22/32" ] }