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GET /api/patches/810719/?format=api
{ "id": 810719, "url": "http://patchwork.ozlabs.org/api/patches/810719/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-17-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-17-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:56", "name": "[PULL,16/32] target/arm: [tcg] Port to init_disas_context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "678734f25b9c47b6b2d076eefdadd44d3261b9e4", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-17-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810719/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810719/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"dceGHqUz\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTY95vz9z9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:28:45 +1000 (AEST)", "from localhost ([::1]:37052 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpdBz-00029L-Q8\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:28:43 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41807)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqi-0000Hn-AN\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:52 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqb-0002Kd-RD\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:44 -0400", "from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:37872)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqb-0002Js-J7\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:37 -0400", "by mail-pg0-x230.google.com with SMTP id d8so15975225pgt.4\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:37 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.35\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=Nw/N7XFADUQ4cz+yLiuI9eEsEgwzSGmakMAgbO2x7d4=;\n\tb=dceGHqUzBwaApPXbAl744O7m8yyVGmmEYfK2tf+rMUxxpPdcb+5FnsmFY8N7hXJJX0\n\tq2+4w7GkJvcfn2xBNwsnKaMOm+bAxKxqwvei4fjVs6zzUiQIyDrBFNfqMP/VoHiqROYP\n\tLdWVKt72UMSWjF2+cdIrYGZ+MyrNs7V0Wp7/0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=Nw/N7XFADUQ4cz+yLiuI9eEsEgwzSGmakMAgbO2x7d4=;\n\tb=jOhEh2UTSXqwwPkn4cDsrCd8s8e0sZo1aVK+oKkGfoH62JeOMrdaPz4Yv2GDAHGn4/\n\tUNqXGS+0NvXmy1E7GxVUrgUYvSQ5g/fnuiYcbqqiGiXzmRluKYf26wbEzQC3J7u7/BLa\n\tMP1alCVZZJUflhiGUiTWWKKWMcKTnIuYqjMhv0VdeErafdqdDKJ4d8o2pqQSJs4ic26B\n\tGBVNzzmcb7V+vubJCMqHglM6gv6bIFe2R1AJ9BcMC5wp9woPT2YovpPxoxERz4p+DCCQ\n\t8UzmhE79YSUpJ8YA3yIq875cVoj2dG0XpMR0YquCPITFA8G/v4trUEVzDdpvfWg2viyG\n\thkiQ==", "X-Gm-Message-State": "AHPjjUjxFm4UXLH4VIvA29p6JTZjo5wBp9Z6xBJd3jlIjx4XWxwOKRcG\n\tTGeItPcQqt0aQTgtY8gLrQ==", "X-Google-Smtp-Source": "ADKCNb7se6GWoPC7BcS+c3voJXIa2sBFTmWaMXWzc7SuBAu1Wpu8Lja+0imVEea56CsIm27O62xDFw==", "X-Received": "by 10.84.240.129 with SMTP id z1mr8836159plk.219.1504713996419; \n\tWed, 06 Sep 2017 09:06:36 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:56 -0700", "Message-Id": "<20170906160612.22769-17-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::230", "Subject": "[Qemu-devel] [PULL 16/32] target/arm: [tcg] Port to\n\tinit_disas_context", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan>\n[rth: Adjust for max_insns interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 88 ++++++++++++++++++++++++++++----------------------\n 1 file changed, 50 insertions(+), 38 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 4db8978a93..a95c183cee 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11824,32 +11824,12 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)\n return false;\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+static int arm_tr_init_disas_context(DisasContextBase *dcbase,\n+ CPUState *cs, int max_insns)\n {\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n CPUARMState *env = cs->env_ptr;\n ARMCPU *cpu = arm_env_get_cpu(env);\n- DisasContext dc1, *dc = &dc1;\n- target_ulong next_page_start;\n- int max_insns;\n- bool end_of_page;\n-\n- /* generate intermediate code */\n-\n- /* The A64 decoder has its own top level loop, because it doesn't need\n- * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n- */\n- if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n- gen_intermediate_code_a64(&dc->base, cs, tb);\n- return;\n- }\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n dc->pc = dc->base.pc_first;\n dc->condjmp = 0;\n@@ -11860,23 +11840,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n */\n dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&\n !arm_el_is_aa64(env, 3);\n- dc->thumb = ARM_TBFLAG_THUMB(tb->flags);\n- dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);\n- dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;\n- dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;\n- dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;\n- dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));\n+ dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags);\n+ dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags);\n+ dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE;\n+ dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1;\n+ dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4;\n+ dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags));\n dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);\n #if !defined(CONFIG_USER_ONLY)\n dc->user = (dc->current_el == 0);\n #endif\n- dc->ns = ARM_TBFLAG_NS(tb->flags);\n- dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);\n- dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);\n- dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);\n- dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);\n- dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);\n- dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);\n+ dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags);\n+ dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);\n+ dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags);\n+ dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags);\n+ dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags);\n+ dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags);\n+ dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags);\n dc->cp_regs = cpu->cp_regs;\n dc->features = env->features;\n \n@@ -11895,11 +11875,12 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n * emit code to generate a software step exception\n * end the TB\n */\n- dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);\n- dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);\n+ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags);\n+ dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags);\n dc->is_ldex = false;\n dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */\n \n+\n cpu_F0s = tcg_temp_new_i32();\n cpu_F1s = tcg_temp_new_i32();\n cpu_F0d = tcg_temp_new_i64();\n@@ -11908,6 +11889,36 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n cpu_V1 = cpu_F1d;\n /* FIXME: cpu_M0 can probably be the same as cpu_V0. */\n cpu_M0 = tcg_temp_new_i64();\n+\n+ return max_insns;\n+}\n+\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+{\n+ CPUARMState *env = cs->env_ptr;\n+ DisasContext dc1, *dc = &dc1;\n+ target_ulong next_page_start;\n+ int max_insns;\n+ bool end_of_page;\n+\n+ /* generate intermediate code */\n+\n+ /* The A64 decoder has its own top level loop, because it doesn't need\n+ * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n+ */\n+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n+ gen_intermediate_code_a64(&dc->base, cs, tb);\n+ return;\n+ }\n+\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+\n next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n@@ -11916,6 +11927,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n if (max_insns > TCG_MAX_INSNS) {\n max_insns = TCG_MAX_INSNS;\n }\n+ max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n \n gen_tb_start(tb);\n \n", "prefixes": [ "PULL", "16/32" ] }