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GET /api/patches/810718/?format=api
{ "id": 810718, "url": "http://patchwork.ozlabs.org/api/patches/810718/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-16-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-16-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:55", "name": "[PULL,15/32] target/arm: [tcg] Port to DisasContextBase", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "32b5f6c6afd8544482220f062129bafa6afa3036", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-16-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810718/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810718/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"VSm6HNOa\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTVh0dpjz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:26:35 +1000 (AEST)", "from localhost ([::1]:37035 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd9p-0008Q4-Fm\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:26:29 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41795)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqh-0000G4-Id\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:51 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqb-0002Jv-5b\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:43 -0400", "from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37872)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqa-0002IS-P9\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:37 -0400", "by mail-pg0-x22c.google.com with SMTP id d8so15975123pgt.4\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:36 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.33\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=kyTRkJwFuA3Qacic/EBTpNf7SPJB42Dv4aek8t3omQ8=;\n\tb=VSm6HNOauVeyX2hUL1azgQk1b75UCuKxGxzYM2a/n+e7PaMM0DEOnKaPN1p5yG6fx9\n\tR5C6CIz2zkgnsB4KO+9Szf1yoXdcbVYX5ZfcfJVuAAyVziaYeQd1K4ip2ynz6yjtqfSi\n\tdKbN4cbDC4fqCoMtgt+H+irrvCxRmTzePxrWA=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=kyTRkJwFuA3Qacic/EBTpNf7SPJB42Dv4aek8t3omQ8=;\n\tb=UGup2f756uxxIuxMOyizP0PgD31LX2KogPlMrsl5rRjvyTK6wFLLnuNrh3ib8ch0Uj\n\tsZlE8aRUXAXa9YvtngWsgFLLv473NJGTQ2PnbByvAL0q/lcGpsKE26g+hfC3EC+pcYPz\n\tkaJYxtXFc8rRuXRDqI+1UH2M3Wbkv/wgJwhhDAL7wbu2mnEq3L1iovxt6Gt+Jj83d4hb\n\tl8FuMCr52i6geoTpYmYwjbWfqGG2ISlJzDpQ2dgPis3LQexEpKigHMEWatoE/c+SLnTn\n\tntI4FoAeaSvAXz1cLHSzZBqi1mvUsA0mIQV66zG+M+KrEkoee7Y8O7Tp4ZXy3ZKT1Qiz\n\tQqnA==", "X-Gm-Message-State": "AHPjjUhHhyBK4J93OG8Ag+FB5WTTOYbfsStVL1HTF9zuVVjsZu57v3z6\n\thMzTsXt+rWUpdapaD4DxUA==", "X-Google-Smtp-Source": "ADKCNb6/bBO0OrjWW3frpuiyfDYqwqUW0RyJW4eXMbpYsKiAHVJfC4pl63iMMUnKryxrq2QLRAchKA==", "X-Received": "by 10.99.151.73 with SMTP id d9mr8117818pgo.13.1504713995084;\n\tWed, 06 Sep 2017 09:06:35 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:55 -0700", "Message-Id": "<20170906160612.22769-16-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22c", "Subject": "[Qemu-devel] [PULL 15/32] target/arm: [tcg] Port to DisasContextBase", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic\ninstruction translation loop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.h | 11 +++--\n target/arm/translate-a64.c | 113 ++++++++++++++++++++++---------------------\n target/arm/translate.c | 117 ++++++++++++++++++++++-----------------------\n 3 files changed, 120 insertions(+), 121 deletions(-)", "diff": "diff --git a/target/arm/translate.h b/target/arm/translate.h\nindex 1eb432dc2c..a804ff65ac 100644\n--- a/target/arm/translate.h\n+++ b/target/arm/translate.h\n@@ -6,9 +6,10 @@\n \n /* internal defines */\n typedef struct DisasContext {\n+ DisasContextBase base;\n+\n target_ulong pc;\n uint32_t insn;\n- int is_jmp;\n /* Nonzero if this instruction has been conditionally skipped. */\n int condjmp;\n /* The label that will be jumped to when the instruction is skipped. */\n@@ -16,8 +17,6 @@ typedef struct DisasContext {\n /* Thumb-2 conditional execution bits. */\n int condexec_mask;\n int condexec_cond;\n- struct TranslationBlock *tb;\n- int singlestep_enabled;\n int thumb;\n int sctlr_b;\n TCGMemOp be_data;\n@@ -150,7 +149,8 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)\n \n #ifdef TARGET_AARCH64\n void a64_translate_init(void);\n-void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);\n+void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,\n+ TranslationBlock *tb);\n void gen_a64_set_pc_im(uint64_t val);\n void aarch64_cpu_dump_state(CPUState *cs, FILE *f,\n fprintf_function cpu_fprintf, int flags);\n@@ -159,7 +159,8 @@ static inline void a64_translate_init(void)\n {\n }\n \n-static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)\n+static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,\n+ TranslationBlock *tb)\n {\n }\n \ndiff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex 881d3c0cbb..f5c678ef25 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)\n {\n gen_a64_set_pc_im(s->pc - offset);\n gen_exception_internal(excp);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_exception_insn(DisasContext *s, int offset, int excp,\n@@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,\n {\n gen_a64_set_pc_im(s->pc - offset);\n gen_exception(excp, syndrome, target_el);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_ss_advance(DisasContext *s)\n@@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s)\n gen_ss_advance(s);\n gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),\n default_exception_el(s));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)\n@@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)\n /* No direct tb linking with singlestep (either QEMU's or the ARM\n * debug architecture kind) or deterministic io\n */\n- if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) {\n+ if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags & CF_LAST_IO)) {\n return false;\n }\n \n #ifndef CONFIG_USER_ONLY\n /* Only link tbs from inside the same guest page */\n- if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {\n+ if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {\n return false;\n }\n #endif\n@@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)\n {\n TranslationBlock *tb;\n \n- tb = s->tb;\n+ tb = s->base.tb;\n if (use_goto_tb(s, n, dest)) {\n tcg_gen_goto_tb(n);\n gen_a64_set_pc_im(dest);\n tcg_gen_exit_tb((intptr_t)tb + n);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n } else {\n gen_a64_set_pc_im(dest);\n if (s->ss_active) {\n gen_step_complete_exception(s);\n- } else if (s->singlestep_enabled) {\n+ } else if (s->base.singlestep_enabled) {\n gen_exception_internal(EXCP_DEBUG);\n } else {\n tcg_gen_lookup_and_goto_ptr(cpu_pc);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n }\n }\n@@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t insn,\n case 0: /* NOP */\n return;\n case 3: /* WFI */\n- s->is_jmp = DISAS_WFI;\n+ s->base.is_jmp = DISAS_WFI;\n return;\n case 1: /* YIELD */\n if (!parallel_cpus) {\n- s->is_jmp = DISAS_YIELD;\n+ s->base.is_jmp = DISAS_YIELD;\n }\n return;\n case 2: /* WFE */\n if (!parallel_cpus) {\n- s->is_jmp = DISAS_WFE;\n+ s->base.is_jmp = DISAS_WFE;\n }\n return;\n case 4: /* SEV */\n@@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,\n tcg_temp_free_i32(tcg_op);\n /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */\n gen_a64_set_pc_im(s->pc);\n- s->is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP);\n+ s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP);\n break;\n }\n default:\n@@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,\n break;\n }\n \n- if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n+ if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n gen_io_start();\n }\n \n@@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,\n }\n }\n \n- if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n+ if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n /* I/O operations must end the TB here (whether read or write) */\n gen_io_end();\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {\n /* We default to ending the TB on a coprocessor register write,\n * but allow this to be suppressed by the register definition\n * (usually only necessary to work around guest bugs).\n */\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n }\n \n@@ -1789,7 +1789,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)\n }\n gen_helper_exception_return(cpu_env);\n /* Must exit loop to check un-masked IRQs */\n- s->is_jmp = DISAS_EXIT;\n+ s->base.is_jmp = DISAS_EXIT;\n return;\n case 5: /* DRPS */\n if (rn != 0x1f) {\n@@ -1803,7 +1803,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)\n return;\n }\n \n- s->is_jmp = DISAS_JUMP;\n+ s->base.is_jmp = DISAS_JUMP;\n }\n \n /* C3.2 Branches, exception generating and system instructions */\n@@ -11200,23 +11200,23 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)\n free_tmp_a64(s);\n }\n \n-void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n+void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n+ TranslationBlock *tb)\n {\n CPUARMState *env = cs->env_ptr;\n ARMCPU *cpu = arm_env_get_cpu(env);\n- DisasContext dc1, *dc = &dc1;\n- target_ulong pc_start;\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n target_ulong next_page_start;\n- int num_insns;\n int max_insns;\n \n- pc_start = tb->pc;\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n- dc->tb = tb;\n-\n- dc->is_jmp = DISAS_NEXT;\n- dc->pc = pc_start;\n- dc->singlestep_enabled = cs->singlestep_enabled;\n+ dc->pc = dc->base.pc_first;\n dc->condjmp = 0;\n \n dc->aarch64 = 1;\n@@ -11227,17 +11227,17 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n !arm_el_is_aa64(env, 3);\n dc->thumb = 0;\n dc->sctlr_b = 0;\n- dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;\n+ dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE;\n dc->condexec_mask = 0;\n dc->condexec_cond = 0;\n- dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));\n- dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags);\n- dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags);\n+ dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags));\n+ dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags);\n+ dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags);\n dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);\n #if !defined(CONFIG_USER_ONLY)\n dc->user = (dc->current_el == 0);\n #endif\n- dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);\n+ dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);\n dc->vec_len = 0;\n dc->vec_stride = 0;\n dc->cp_regs = cpu->cp_regs;\n@@ -11258,16 +11258,15 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n * emit code to generate a software step exception\n * end the TB\n */\n- dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);\n- dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);\n+ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags);\n+ dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags);\n dc->is_ldex = false;\n dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);\n \n init_tmp_a64_array(dc);\n \n- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n- num_insns = 0;\n- max_insns = tb->cflags & CF_COUNT_MASK;\n+ next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n+ max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n }\n@@ -11280,9 +11279,9 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n tcg_clear_temp_count();\n \n do {\n+ dc->base.num_insns++;\n dc->insn_start_idx = tcg_op_buf_count();\n tcg_gen_insn_start(dc->pc, 0, 0);\n- num_insns++;\n \n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\n@@ -11292,14 +11291,14 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n gen_a64_set_pc_im(dc->pc);\n gen_helper_check_breakpoints(cpu_env);\n /* End the TB early; it likely won't be executed */\n- dc->is_jmp = DISAS_UPDATE;\n+ dc->base.is_jmp = DISAS_UPDATE;\n } else {\n gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n /* The address covered by the breakpoint must be\n- included in [tb->pc, tb->pc + tb->size) in order\n+ included in [dc->base.tb->pc, dc->base.tb->pc + dc->base.tb->size) in order\n to for it to be properly cleared -- thus we\n increment the PC here so that the logic setting\n- tb->size below does the right thing. */\n+ dc->base.tb->size below does the right thing. */\n dc->pc += 4;\n goto done_generating;\n }\n@@ -11308,7 +11307,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n }\n }\n \n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n+ if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) {\n gen_io_start();\n }\n \n@@ -11323,10 +11322,10 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n * \"did not step an insn\" case, and so the syndrome ISV and EX\n * bits should be zero.\n */\n- assert(num_insns == 1);\n+ assert(dc->base.num_insns == 1);\n gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n default_exception_el(dc));\n- dc->is_jmp = DISAS_NORETURN;\n+ dc->base.is_jmp = DISAS_NORETURN;\n break;\n }\n \n@@ -11342,14 +11341,14 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n * Also stop translation when a page boundary is reached. This\n * ensures prefetch aborts occur at the right place.\n */\n- } while (!dc->is_jmp && !tcg_op_buf_full() &&\n+ } while (!dc->base.is_jmp && !tcg_op_buf_full() &&\n !cs->singlestep_enabled &&\n !singlestep &&\n !dc->ss_active &&\n dc->pc < next_page_start &&\n- num_insns < max_insns);\n+ dc->base.num_insns < max_insns);\n \n- if (tb->cflags & CF_LAST_IO) {\n+ if (dc->base.tb->cflags & CF_LAST_IO) {\n gen_io_end();\n }\n \n@@ -11359,7 +11358,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n * gen_goto_tb() has already handled emitting the debug exception\n * (and thus a tb-jump is not possible when singlestepping).\n */\n- switch (dc->is_jmp) {\n+ switch (dc->base.is_jmp) {\n default:\n gen_a64_set_pc_im(dc->pc);\n /* fall through */\n@@ -11374,7 +11373,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n break;\n }\n } else {\n- switch (dc->is_jmp) {\n+ switch (dc->base.is_jmp) {\n case DISAS_NEXT:\n gen_goto_tb(dc, 1, dc->pc);\n break;\n@@ -11414,20 +11413,20 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)\n }\n \n done_generating:\n- gen_tb_end(tb, num_insns);\n+ gen_tb_end(tb, dc->base.num_insns);\n \n #ifdef DEBUG_DISAS\n if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&\n- qemu_log_in_addr_range(pc_start)) {\n+ qemu_log_in_addr_range(dc->base.pc_first)) {\n qemu_log_lock();\n qemu_log(\"----------------\\n\");\n- qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));\n- log_target_disas(cs, pc_start, dc->pc - pc_start,\n+ qemu_log(\"IN: %s\\n\", lookup_symbol(dc->base.pc_first));\n+ log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first,\n 4 | (bswap_code(dc->sctlr_b) ? 2 : 0));\n qemu_log(\"\\n\");\n qemu_log_unlock();\n }\n #endif\n- tb->size = dc->pc - pc_start;\n- tb->icount = num_insns;\n+ dc->base.tb->size = dc->pc - dc->base.pc_first;\n+ dc->base.tb->icount = dc->base.num_insns;\n }\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 746193eebc..4db8978a93 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i32 var)\n * We choose to ignore [1:0] in ARM mode for all architecture versions.\n */\n tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);\n- s->is_jmp = DISAS_JUMP;\n+ s->base.is_jmp = DISAS_JUMP;\n }\n tcg_gen_mov_i32(cpu_R[reg], var);\n tcg_temp_free_i32(var);\n@@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s)\n gen_ss_advance(s);\n gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),\n default_exception_el(s));\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_singlestep_exception(DisasContext *s)\n@@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s)\n * misnamed as it only means \"one instruction per TB\" and doesn't\n * affect the code we generate.\n */\n- return s->singlestep_enabled || s->ss_active;\n+ return s->base.singlestep_enabled || s->ss_active;\n }\n \n static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)\n@@ -930,7 +930,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr)\n {\n TCGv_i32 tmp;\n \n- s->is_jmp = DISAS_JUMP;\n+ s->base.is_jmp = DISAS_JUMP;\n if (s->thumb != (addr & 1)) {\n tmp = tcg_temp_new_i32();\n tcg_gen_movi_i32(tmp, addr & 1);\n@@ -943,7 +943,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr)\n /* Set PC and Thumb state from var. var is marked as dead. */\n static inline void gen_bx(DisasContext *s, TCGv_i32 var)\n {\n- s->is_jmp = DISAS_JUMP;\n+ s->base.is_jmp = DISAS_JUMP;\n tcg_gen_andi_i32(cpu_R[15], var, ~1);\n tcg_gen_andi_i32(var, var, 1);\n store_cpu_field(var, thumb);\n@@ -957,11 +957,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)\n static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)\n {\n /* Generate the same code here as for a simple bx, but flag via\n- * s->is_jmp that we need to do the rest of the work later.\n+ * s->base.is_jmp that we need to do the rest of the work later.\n */\n gen_bx(s, var);\n if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {\n- s->is_jmp = DISAS_BX_EXCRET;\n+ s->base.is_jmp = DISAS_BX_EXCRET;\n }\n }\n \n@@ -1161,7 +1161,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)\n */\n s->svc_imm = imm16;\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_HVC;\n+ s->base.is_jmp = DISAS_HVC;\n }\n \n static inline void gen_smc(DisasContext *s)\n@@ -1176,7 +1176,7 @@ static inline void gen_smc(DisasContext *s)\n gen_helper_pre_smc(cpu_env, tmp);\n tcg_temp_free_i32(tmp);\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_SMC;\n+ s->base.is_jmp = DISAS_SMC;\n }\n \n static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)\n@@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)\n gen_set_condexec(s);\n gen_set_pc_im(s, s->pc - offset);\n gen_exception_internal(excp);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static void gen_exception_insn(DisasContext *s, int offset, int excp,\n@@ -1193,14 +1193,14 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,\n gen_set_condexec(s);\n gen_set_pc_im(s, s->pc - offset);\n gen_exception(excp, syn, target_el);\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n /* Force a TB lookup after an instruction that changes the CPU state. */\n static inline void gen_lookup_tb(DisasContext *s)\n {\n tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);\n- s->is_jmp = DISAS_EXIT;\n+ s->base.is_jmp = DISAS_EXIT;\n }\n \n static inline void gen_hlt(DisasContext *s, int imm)\n@@ -4145,7 +4145,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)\n static inline bool use_goto_tb(DisasContext *s, target_ulong dest)\n {\n #ifndef CONFIG_USER_ONLY\n- return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||\n+ return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||\n ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);\n #else\n return true;\n@@ -4169,12 +4169,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)\n if (use_goto_tb(s, dest)) {\n tcg_gen_goto_tb(n);\n gen_set_pc_im(s, dest);\n- tcg_gen_exit_tb((uintptr_t)s->tb + n);\n+ tcg_gen_exit_tb((uintptr_t)s->base.tb + n);\n } else {\n gen_set_pc_im(s, dest);\n gen_goto_ptr();\n }\n- s->is_jmp = DISAS_NORETURN;\n+ s->base.is_jmp = DISAS_NORETURN;\n }\n \n static inline void gen_jmp (DisasContext *s, uint32_t dest)\n@@ -4436,7 +4436,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)\n tcg_temp_free_i32(tcg_tgtmode);\n tcg_temp_free_i32(tcg_regno);\n tcg_temp_free_i32(tcg_reg);\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n \n static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)\n@@ -4458,7 +4458,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)\n tcg_temp_free_i32(tcg_tgtmode);\n tcg_temp_free_i32(tcg_regno);\n store_reg(s, rn, tcg_reg);\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n \n /* Store value to PC as for an exception return (ie don't\n@@ -4482,7 +4482,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)\n gen_helper_cpsr_write_eret(cpu_env, cpsr);\n tcg_temp_free_i32(cpsr);\n /* Must exit loop to check un-masked IRQs */\n- s->is_jmp = DISAS_EXIT;\n+ s->base.is_jmp = DISAS_EXIT;\n }\n \n /* Generate an old-style exception return. Marks pc as dead. */\n@@ -4505,17 +4505,17 @@ static void gen_nop_hint(DisasContext *s, int val)\n case 1: /* yield */\n if (!parallel_cpus) {\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_YIELD;\n+ s->base.is_jmp = DISAS_YIELD;\n }\n break;\n case 3: /* wfi */\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_WFI;\n+ s->base.is_jmp = DISAS_WFI;\n break;\n case 2: /* wfe */\n if (!parallel_cpus) {\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_WFE;\n+ s->base.is_jmp = DISAS_WFE;\n }\n break;\n case 4: /* sev */\n@@ -7654,13 +7654,13 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)\n return 1;\n }\n gen_set_pc_im(s, s->pc);\n- s->is_jmp = DISAS_WFI;\n+ s->base.is_jmp = DISAS_WFI;\n return 0;\n default:\n break;\n }\n \n- if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n+ if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n gen_io_start();\n }\n \n@@ -7751,7 +7751,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)\n }\n }\n \n- if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n+ if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {\n /* I/O operations must end the TB here (whether read or write) */\n gen_io_end();\n gen_lookup_tb(s);\n@@ -8065,7 +8065,7 @@ static void gen_srs(DisasContext *s,\n tcg_temp_free_i32(tmp);\n }\n tcg_temp_free_i32(addr);\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n \n static void disas_arm_insn(DisasContext *s, unsigned int insn)\n@@ -8153,7 +8153,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)\n /* setend */\n if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {\n gen_helper_setend(cpu_env);\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n return;\n } else if ((insn & 0x0fffff00) == 0x057ff000) {\n@@ -9527,7 +9527,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)\n gen_helper_cpsr_write_eret(cpu_env, tmp);\n tcg_temp_free_i32(tmp);\n /* Must exit loop to check un-masked IRQs */\n- s->is_jmp = DISAS_EXIT;\n+ s->base.is_jmp = DISAS_EXIT;\n }\n }\n break;\n@@ -9565,7 +9565,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)\n /* swi */\n gen_set_pc_im(s, s->pc);\n s->svc_imm = extract32(insn, 0, 24);\n- s->is_jmp = DISAS_SWI;\n+ s->base.is_jmp = DISAS_SWI;\n break;\n default:\n illegal_op:\n@@ -11657,7 +11657,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n ARCH(6);\n if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) {\n gen_helper_setend(cpu_env);\n- s->is_jmp = DISAS_UPDATE;\n+ s->base.is_jmp = DISAS_UPDATE;\n }\n break;\n case 3:\n@@ -11751,7 +11751,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)\n /* swi */\n gen_set_pc_im(s, s->pc);\n s->svc_imm = extract32(insn, 0, 8);\n- s->is_jmp = DISAS_SWI;\n+ s->base.is_jmp = DISAS_SWI;\n break;\n }\n /* generate a conditional jump to next instruction */\n@@ -11830,9 +11830,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n CPUARMState *env = cs->env_ptr;\n ARMCPU *cpu = arm_env_get_cpu(env);\n DisasContext dc1, *dc = &dc1;\n- target_ulong pc_start;\n target_ulong next_page_start;\n- int num_insns;\n int max_insns;\n bool end_of_page;\n \n@@ -11842,17 +11840,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n */\n if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n- gen_intermediate_code_a64(cs, tb);\n+ gen_intermediate_code_a64(&dc->base, cs, tb);\n return;\n }\n \n- pc_start = tb->pc;\n+ dc->base.tb = tb;\n+ dc->base.pc_first = tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n- dc->tb = tb;\n-\n- dc->is_jmp = DISAS_NEXT;\n- dc->pc = pc_start;\n- dc->singlestep_enabled = cs->singlestep_enabled;\n+ dc->pc = dc->base.pc_first;\n dc->condjmp = 0;\n \n dc->aarch64 = 0;\n@@ -11909,8 +11908,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n cpu_V1 = cpu_F1d;\n /* FIXME: cpu_M0 can probably be the same as cpu_V0. */\n cpu_M0 = tcg_temp_new_i64();\n- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n- num_insns = 0;\n+ next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -11962,11 +11960,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n store_cpu_field(tmp, condexec_bits);\n }\n do {\n+ dc->base.num_insns++;\n dc->insn_start_idx = tcg_op_buf_count();\n tcg_gen_insn_start(dc->pc,\n (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),\n 0);\n- num_insns++;\n \n if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n CPUBreakpoint *bp;\n@@ -11977,7 +11975,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_set_pc_im(dc, dc->pc);\n gen_helper_check_breakpoints(cpu_env);\n /* End the TB early; it's likely not going to be executed */\n- dc->is_jmp = DISAS_UPDATE;\n+ dc->base.is_jmp = DISAS_UPDATE;\n } else {\n gen_exception_internal_insn(dc, 0, EXCP_DEBUG);\n /* The address covered by the breakpoint must be\n@@ -11995,7 +11993,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n }\n }\n \n- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n+ if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n gen_io_start();\n }\n \n@@ -12005,7 +12003,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n /* We always get here via a jump, so know we are not in a\n conditional execution block. */\n gen_exception_internal(EXCP_KERNEL_TRAP);\n- dc->is_jmp = DISAS_NORETURN;\n+ dc->base.is_jmp = DISAS_NORETURN;\n break;\n }\n #endif\n@@ -12021,10 +12019,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n * \"did not step an insn\" case, and so the syndrome ISV and EX\n * bits should be zero.\n */\n- assert(num_insns == 1);\n+ assert(dc->base.num_insns == 1);\n gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n default_exception_el(dc));\n- goto done_generating;\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ break;\n }\n \n if (dc->thumb) {\n@@ -12043,7 +12042,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n disas_arm_insn(dc, insn);\n }\n \n- if (dc->condjmp && !dc->is_jmp) {\n+ if (dc->condjmp && !dc->base.is_jmp) {\n gen_set_label(dc->condlabel);\n dc->condjmp = 0;\n }\n@@ -12070,11 +12069,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n end_of_page = (dc->pc >= next_page_start) ||\n ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));\n \n- } while (!dc->is_jmp && !tcg_op_buf_full() &&\n+ } while (!dc->base.is_jmp && !tcg_op_buf_full() &&\n !is_singlestepping(dc) &&\n !singlestep &&\n !end_of_page &&\n- num_insns < max_insns);\n+ dc->base.num_insns < max_insns);\n \n if (tb->cflags & CF_LAST_IO) {\n if (dc->condjmp) {\n@@ -12089,7 +12088,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n instruction was a conditional branch or trap, and the PC has\n already been written. */\n gen_set_condexec(dc);\n- if (dc->is_jmp == DISAS_BX_EXCRET) {\n+ if (dc->base.is_jmp == DISAS_BX_EXCRET) {\n /* Exception return branches need some special case code at the\n * end of the TB, which is complex enough that it has to\n * handle the single-step vs not and the condition-failed\n@@ -12098,7 +12097,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_bx_excret_final_code(dc);\n } else if (unlikely(is_singlestepping(dc))) {\n /* Unconditional and \"condition passed\" instruction codepath. */\n- switch (dc->is_jmp) {\n+ switch (dc->base.is_jmp) {\n case DISAS_SWI:\n gen_ss_advance(dc);\n gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),\n@@ -12132,7 +12131,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n - Hardware watchpoints.\n Hardware breakpoints have already been handled and skip this code.\n */\n- switch(dc->is_jmp) {\n+ switch(dc->base.is_jmp) {\n case DISAS_NEXT:\n gen_goto_tb(dc, 1, dc->pc);\n break;\n@@ -12188,22 +12187,22 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n }\n \n done_generating:\n- gen_tb_end(tb, num_insns);\n+ gen_tb_end(tb, dc->base.num_insns);\n \n #ifdef DEBUG_DISAS\n if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&\n- qemu_log_in_addr_range(pc_start)) {\n+ qemu_log_in_addr_range(dc->base.pc_first)) {\n qemu_log_lock();\n qemu_log(\"----------------\\n\");\n- qemu_log(\"IN: %s\\n\", lookup_symbol(pc_start));\n- log_target_disas(cs, pc_start, dc->pc - pc_start,\n+ qemu_log(\"IN: %s\\n\", lookup_symbol(dc->base.pc_first));\n+ log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first,\n dc->thumb | (dc->sctlr_b << 1));\n qemu_log(\"\\n\");\n qemu_log_unlock();\n }\n #endif\n- tb->size = dc->pc - pc_start;\n- tb->icount = num_insns;\n+ tb->size = dc->pc - dc->base.pc_first;\n+ tb->icount = dc->base.num_insns;\n }\n \n static const char *cpu_mode_names[16] = {\n", "prefixes": [ "PULL", "15/32" ] }