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GET /api/patches/810714/?format=api
{ "id": 810714, "url": "http://patchwork.ozlabs.org/api/patches/810714/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-24-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-24-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:03", "name": "[PULL,23/32] target/arm: [tcg, a64] Port to translate_insn", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1d8b2d728628f508884929bf819a2bd974eb44f4", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-24-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810714/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810714/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"OEq4M0Y3\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTPm1dmKz9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:22:20 +1000 (AEST)", "from localhost ([::1]:37017 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd5m-0004TL-8n\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:22:18 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41941)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqp-0000Pg-3Q\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:57 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqk-0002jS-Nu\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:51 -0400", "from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34784)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqk-0002g9-GF\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:46 -0400", "by mail-pf0-x22a.google.com with SMTP id m1so13485921pfk.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:46 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.44\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=xElHN/zfdPbhnMF3R21WRLSn0KBWPuHQqnySWytQRsM=;\n\tb=OEq4M0Y3GNXnaooOb9izY3AxbUALVbVgEJP0ZFGWFCTuuLMwDk9nHN3fOERsvB5wic\n\t/vF24fUxXYDmF8g9E1plHUrEOWlw+WjkvCpG1DQ4vT8jTK4WRXc9dBIJTyOhOxv6oLLE\n\twe4tep2AxCLHWx6biSJErfToFQwHfq8RX3cpc=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=xElHN/zfdPbhnMF3R21WRLSn0KBWPuHQqnySWytQRsM=;\n\tb=IgnHoKkOx5OvV07nT0GZdowwFp9660ctaNSQRiLi1jbATbI6wFbhL4uJj3C1CarYhW\n\tIPkb0Tqd7bbOdCxPn0OLaS5mph2xF3ei/GyhWVpLZgg0dVkH/oFbAKXbbmKKTF9l61FX\n\t0KaXBG61xqv7PRL18ccSKBo0ce9yNxJzkBBdxjqoI7jY1eMGI7sslCdJJ29ZBf8DZf5x\n\tTi/bx7bUQR4vbkRFZlBRup4fJ6aPth+BpiYCFDy+nOyjMQW+w196aS0sw2/d7s9OesF0\n\tMNzYcl762r4mEzevCOkMk0tyMHTGCxTYHdePdBioxgAm3p6zbOsPKCzbTU1fYiW3mnoY\n\tx+aw==", "X-Gm-Message-State": "AHPjjUhndRIBs4weD45jlcuvHx8t7B5qjTJuRYbAnjcnP1h4EqLr72O7\n\tIoCHNBTJsIkGpVP0NQHS6g==", "X-Google-Smtp-Source": "ADKCNb6sV6V5nGz89otRgPFmobQosMDHBLs2SMUZ9N0B2abvHqpj4/vChMZvxvmQ/YcqvZ7n29g/bg==", "X-Received": "by 10.84.234.197 with SMTP id i5mr8829617plt.184.1504714005315; \n\tWed, 06 Sep 2017 09:06:45 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:03 -0700", "Message-Id": "<20170906160612.22769-24-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22a", "Subject": "[Qemu-devel] [PULL 23/32] target/arm: [tcg,\n\ta64] Port to translate_insn", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nMessage-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan>\n[rth: Adjust for translate_insn interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++------------------\n 1 file changed, 43 insertions(+), 28 deletions(-)", "diff": "diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex e94198280d..f959f4469a 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->is_ldex = false;\n dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);\n \n+ dc->next_page_start =\n+ (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n+\n init_tmp_a64_array(dc);\n \n return max_insns;\n@@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n return true;\n }\n \n+static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUARMState *env = cpu->env_ptr;\n+\n+ if (dc->ss_active && !dc->pstate_ss) {\n+ /* Singlestep state is Active-pending.\n+ * If we're in this state at the start of a TB then either\n+ * a) we just took an exception to an EL which is being debugged\n+ * and this is the first insn in the exception handler\n+ * b) debug exceptions were masked and we just unmasked them\n+ * without changing EL (eg by clearing PSTATE.D)\n+ * In either case we're going to take a swstep exception in the\n+ * \"did not step an insn\" case, and so the syndrome ISV and EX\n+ * bits should be zero.\n+ */\n+ assert(dc->base.num_insns == 1);\n+ gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n+ default_exception_el(dc));\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ } else {\n+ disas_a64_insn(env, dc);\n+ }\n+\n+ if (dc->base.is_jmp == DISAS_NEXT) {\n+ if (dc->ss_active || dc->pc >= dc->next_page_start) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ }\n+\n+ dc->base.pc_next = dc->pc;\n+}\n+\n void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n TranslationBlock *tb)\n {\n- CPUARMState *env = cs->env_ptr;\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- target_ulong next_page_start;\n int max_insns;\n \n dc->base.tb = tb;\n@@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n dc->base.num_insns = 0;\n dc->base.singlestep_enabled = cs->singlestep_enabled;\n \n- next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n gen_io_start();\n }\n \n- if (dc->ss_active && !dc->pstate_ss) {\n- /* Singlestep state is Active-pending.\n- * If we're in this state at the start of a TB then either\n- * a) we just took an exception to an EL which is being debugged\n- * and this is the first insn in the exception handler\n- * b) debug exceptions were masked and we just unmasked them\n- * without changing EL (eg by clearing PSTATE.D)\n- * In either case we're going to take a swstep exception in the\n- * \"did not step an insn\" case, and so the syndrome ISV and EX\n- * bits should be zero.\n- */\n- assert(dc->base.num_insns == 1);\n- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n- default_exception_el(dc));\n- dc->base.is_jmp = DISAS_NORETURN;\n- break;\n- }\n-\n- disas_a64_insn(env, dc);\n+ aarch64_tr_translate_insn(&dc->base, cs);\n \n if (tcg_check_temp_count()) {\n fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n dc->pc);\n }\n \n+ if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled ||\n+ singlestep || dc->base.num_insns >= max_insns)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+\n /* Translation stops when a conditional branch is encountered.\n * Otherwise the subsequent code could get translated several times.\n * Also stop translation when a page boundary is reached. This\n * ensures prefetch aborts occur at the right place.\n */\n- } while (!dc->base.is_jmp && !tcg_op_buf_full() &&\n- !cs->singlestep_enabled &&\n- !singlestep &&\n- !dc->ss_active &&\n- dc->pc < next_page_start &&\n- dc->base.num_insns < max_insns);\n+ } while (!dc->base.is_jmp);\n \n if (dc->base.tb->cflags & CF_LAST_IO) {\n gen_io_end();\n", "prefixes": [ "PULL", "23/32" ] }