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GET /api/patches/810713/?format=api
{ "id": 810713, "url": "http://patchwork.ozlabs.org/api/patches/810713/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-18-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-18-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:57", "name": "[PULL,17/32] target/arm: [tcg, a64] Port to init_disas_context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "38f93e4e31e1d7b088a03eb9dea6808f97cd78b0", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-18-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810713/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810713/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"TCBhE9C3\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTNT6xFqz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:21:13 +1000 (AEST)", "from localhost ([::1]:37013 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd4h-0003cu-SU\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:21:11 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41885)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcql-0000Je-IF\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:53 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqd-0002Qu-EG\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:47 -0400", "from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:34782)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqd-0002Mh-4r\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400", "by mail-pf0-x230.google.com with SMTP id m1so13485441pfk.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:39 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.36\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=uZN6Az7gZPVb4WSjnLDcTNF9gV7xLS6OAi0/yMa5ABU=;\n\tb=TCBhE9C3L4eNvhojKApqPnrXy5uoOqLGYEEqYBUnYzRg7T55eep2nReK4TiTe+UhQZ\n\tICeR0fmA4cL9WrRBlbr0LTNx3SyJ59rBuY1yOd2ZWdMZgoQhEXUjlV4hyWiT2rJyWtg9\n\tTnJJ/5NAx+Y/Uo7jj0ejuaDXuxepjg2HkwiIQ=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=uZN6Az7gZPVb4WSjnLDcTNF9gV7xLS6OAi0/yMa5ABU=;\n\tb=oloO2X+cH/XFN632OioSDd9hqPoLXGaVY1OOxQBJxa/ewdNL6MEkMxC9Dk1aZdnOCD\n\tXxv1QK5zZfUANWRa1jub4XO3xRWkWudllJkTjD4TarZjDCi9BQ+mqknWAHkj+OYL76jw\n\tqHJq1yS+tWolECCs0RxP+hFMV8bzVeAvPsrQfoHmUlXC8jXDJNSteme2Km0V+MFPxlI4\n\tWhErCuOnY6TVFJD96CyaWYPgJdziu11FyyOazbt6CvOFD7UNGQ1GXsQz6v1B+zLw1TWW\n\tnf0SzmZXPCecrpmavG0BpgBUciisKQQNX3HJf1sVYYa71780q2jTLuf38QZ4vf9LxX1V\n\tMlIA==", "X-Gm-Message-State": "AHPjjUj/TwwTvJtq03RShRRA+Hv6pbdSPLr9wa8rfBhfcYQlduoBWr+b\n\tT0CxnEpGsnuctc/eQau3xQ==", "X-Google-Smtp-Source": "ADKCNb4grL0UBTs6Z0NyJgJ2zN4YFUOlDzDzSUyHjL7GEWBWDfj/AfpeMsdq5lm14esRMetHU+ic8w==", "X-Received": "by 10.84.130.97 with SMTP id 88mr9072991plc.138.1504713997938;\n\tWed, 06 Sep 2017 09:06:37 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:57 -0700", "Message-Id": "<20170906160612.22769-18-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::230", "Subject": "[Qemu-devel] [PULL 17/32] target/arm: [tcg,\n\ta64] Port to init_disas_context", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan>\n[rth: Adjust for max_insns interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate-a64.c | 38 ++++++++++++++++++++++++--------------\n 1 file changed, 24 insertions(+), 14 deletions(-)", "diff": "diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex f5c678ef25..e8dc96c28a 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)\n free_tmp_a64(s);\n }\n \n-void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n- TranslationBlock *tb)\n+static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n+ CPUState *cpu, int max_insns)\n {\n- CPUARMState *env = cs->env_ptr;\n- ARMCPU *cpu = arm_env_get_cpu(env);\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n- target_ulong next_page_start;\n- int max_insns;\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n+ CPUARMState *env = cpu->env_ptr;\n+ ARMCPU *arm_cpu = arm_env_get_cpu(env);\n \n dc->pc = dc->base.pc_first;\n dc->condjmp = 0;\n@@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);\n dc->vec_len = 0;\n dc->vec_stride = 0;\n- dc->cp_regs = cpu->cp_regs;\n+ dc->cp_regs = arm_cpu->cp_regs;\n dc->features = env->features;\n \n /* Single step state. The code-generation logic here is:\n@@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n \n init_tmp_a64_array(dc);\n \n+ return max_insns;\n+}\n+\n+void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n+ TranslationBlock *tb)\n+{\n+ CPUARMState *env = cs->env_ptr;\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ target_ulong next_page_start;\n+ int max_insns;\n+\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+\n next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n@@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n if (max_insns > TCG_MAX_INSNS) {\n max_insns = TCG_MAX_INSNS;\n }\n+ max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);\n \n gen_tb_start(tb);\n \n", "prefixes": [ "PULL", "17/32" ] }