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GET /api/patches/810712/?format=api
{ "id": 810712, "url": "http://patchwork.ozlabs.org/api/patches/810712/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-32-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-32-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:11", "name": "[PULL,31/32] target/arm: Split out thumb_tr_translate_insn", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3ae6d25d42486751ccb20105c0653db8b3582773", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-32-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810712/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810712/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"SCVQNdcJ\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTNK0WMBz9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:21:05 +1000 (AEST)", "from localhost ([::1]:37012 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd4Z-0003TL-4Z\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:21:03 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:42059)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcr5-0000mL-KJ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:11 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqv-00038L-HJ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:07 -0400", "from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:34785)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqv-00037z-8x\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:57 -0400", "by mail-pf0-x22d.google.com with SMTP id m1so13486557pfk.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:57 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.54\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:54 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=;\n\tb=SCVQNdcJQoF/1YSCk3mBFhe6jUTH9iTXprE7kt11wdnEpAWsIQfgHh0Ui2HZI7qlZ5\n\tlElbolg7SM0GWIvQH6X6wTnJs8xiCLfewt0hEC24kL22DKr9Fj2xY7+JQ/Xa/cmjuRY3\n\tqW40RzRgygpEzW9xhlLdZ1kTUBH6R4ARAS23k=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=;\n\tb=GYnC9p4MZ9DJgKMHkfizQYm+1PB43JL5DYNtH6YcXhpSCwxwGGgaj/XREj/2IWoBwH\n\tPcALJ4H2e55N8N2ly/N2rJBWIkCEiN9W7b11R8L8zHU3fWMFL9cNxBoGD8UU6cku/EIe\n\tEJ1/cBk5Nq88FAPBcryAoZVyOYG/QN+OcBQpEv000AQdrWhLvYIfFim9UWyNgA3t9Ncb\n\tUAIz3N/H0IM35esXSA09RpzlYWyu+nbkH5qD0dSQVZXdhwSAU8gTXQsZ6bEbCd6vJ5Jn\n\tbGHXcEoXd6dFAGJ5S20NFkeEgNI7uvravvCw9HxHuMg4jzx8GG6Jq6rbbq2JlNYMS6RZ\n\tKrIg==", "X-Gm-Message-State": "AHPjjUglZREOhZVxHNxd6pUgQiHgjsRSrVkkPLzXIxNyE7CS+wm5Q5Mn\n\tJihu2Z6f0cp+Vl/DlZ9hHg==", "X-Google-Smtp-Source": "ADKCNb6FEjNUMgTTJy1+VTQksaUiFoKkx9f4vQixkgwuPJ0mj+rupkL8gQzA3qL+jWqbVaBk96aWVg==", "X-Received": "by 10.99.104.6 with SMTP id d6mr8232156pgc.168.1504714015929;\n\tWed, 06 Sep 2017 09:06:55 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:11 -0700", "Message-Id": "<20170906160612.22769-32-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22d", "Subject": "[Qemu-devel] [PULL 31/32] target/arm: Split out\n\tthumb_tr_translate_insn", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nWe need not check for ARM vs Thumb state in order to dispatch\ndisassembly of every instruction.\n\nTested-by: Emilio G. Cota <cota@braap.org>\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 121 ++++++++++++++++++++++++++++++++-----------------\n 1 file changed, 80 insertions(+), 41 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 0dd24aad90..9e7bfbcf0c 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11981,11 +11981,8 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n return true;\n }\n \n-static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+static bool arm_pre_translate_insn(DisasContext *dc)\n {\n- DisasContext *dc = container_of(dcbase, DisasContext, base);\n- CPUARMState *env = cpu->env_ptr;\n-\n #ifdef CONFIG_USER_ONLY\n /* Intercept jump to the magic kernel page. */\n if (dc->pc >= 0xffff0000) {\n@@ -11993,7 +11990,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n conditional execution block. */\n gen_exception_internal(EXCP_KERNEL_TRAP);\n dc->base.is_jmp = DISAS_NORETURN;\n- return;\n+ return true;\n }\n #endif\n \n@@ -12012,56 +12009,85 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),\n default_exception_el(dc));\n dc->base.is_jmp = DISAS_NORETURN;\n- return;\n+ return true;\n }\n \n- if (dc->thumb) {\n- disas_thumb_insn(env, dc);\n- if (dc->condexec_mask) {\n- dc->condexec_cond = (dc->condexec_cond & 0xe)\n- | ((dc->condexec_mask >> 4) & 1);\n- dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;\n- if (dc->condexec_mask == 0) {\n- dc->condexec_cond = 0;\n- }\n- }\n- } else {\n- unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);\n- dc->pc += 4;\n- disas_arm_insn(dc, insn);\n- }\n+ return false;\n+}\n \n+static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc)\n+{\n if (dc->condjmp && !dc->base.is_jmp) {\n gen_set_label(dc->condlabel);\n dc->condjmp = 0;\n }\n \n- if (dc->base.is_jmp == DISAS_NEXT) {\n- /* Translation stops when a conditional branch is encountered.\n- * Otherwise the subsequent code could get translated several times.\n- * Also stop translation when a page boundary is reached. This\n- * ensures prefetch aborts occur at the right place. */\n-\n- if (dc->pc >= dc->next_page_start ||\n- (dc->pc >= dc->next_page_start - 3 &&\n- insn_crosses_page(env, dc))) {\n- /* We want to stop the TB if the next insn starts in a new page,\n- * or if it spans between this page and the next. This means that\n- * if we're looking at the last halfword in the page we need to\n- * see if it's a 16-bit Thumb insn (which will fit in this TB)\n- * or a 32-bit Thumb insn (which won't).\n- * This is to avoid generating a silly TB with a single 16-bit insn\n- * in it at the end of this page (which would execute correctly\n- * but isn't very efficient).\n- */\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n+ /* Translation stops when a conditional branch is encountered.\n+ * Otherwise the subsequent code could get translated several times.\n+ * Also stop translation when a page boundary is reached. This\n+ * ensures prefetch aborts occur at the right place.\n+ *\n+ * We want to stop the TB if the next insn starts in a new page,\n+ * or if it spans between this page and the next. This means that\n+ * if we're looking at the last halfword in the page we need to\n+ * see if it's a 16-bit Thumb insn (which will fit in this TB)\n+ * or a 32-bit Thumb insn (which won't).\n+ * This is to avoid generating a silly TB with a single 16-bit insn\n+ * in it at the end of this page (which would execute correctly\n+ * but isn't very efficient).\n+ */\n+ if (dc->base.is_jmp == DISAS_NEXT\n+ && (dc->pc >= dc->next_page_start\n+ || (dc->pc >= dc->next_page_start - 3\n+ && insn_crosses_page(env, dc)))) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n }\n \n dc->base.pc_next = dc->pc;\n translator_loop_temp_check(&dc->base);\n }\n \n+static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUARMState *env = cpu->env_ptr;\n+ unsigned int insn;\n+\n+ if (arm_pre_translate_insn(dc)) {\n+ return;\n+ }\n+\n+ insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);\n+ dc->pc += 4;\n+ disas_arm_insn(dc, insn);\n+\n+ arm_post_translate_insn(env, dc);\n+}\n+\n+static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUARMState *env = cpu->env_ptr;\n+\n+ if (arm_pre_translate_insn(dc)) {\n+ return;\n+ }\n+\n+ disas_thumb_insn(env, dc);\n+\n+ /* Advance the Thumb condexec condition. */\n+ if (dc->condexec_mask) {\n+ dc->condexec_cond = ((dc->condexec_cond & 0xe) |\n+ ((dc->condexec_mask >> 4) & 1));\n+ dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;\n+ if (dc->condexec_mask == 0) {\n+ dc->condexec_cond = 0;\n+ }\n+ }\n+\n+ arm_post_translate_insn(env, dc);\n+}\n+\n static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n@@ -12198,12 +12224,25 @@ static const TranslatorOps arm_translator_ops = {\n .disas_log = arm_tr_disas_log,\n };\n \n+static const TranslatorOps thumb_translator_ops = {\n+ .init_disas_context = arm_tr_init_disas_context,\n+ .tb_start = arm_tr_tb_start,\n+ .insn_start = arm_tr_insn_start,\n+ .breakpoint_check = arm_tr_breakpoint_check,\n+ .translate_insn = thumb_tr_translate_insn,\n+ .tb_stop = arm_tr_tb_stop,\n+ .disas_log = arm_tr_disas_log,\n+};\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)\n {\n DisasContext dc;\n const TranslatorOps *ops = &arm_translator_ops;\n \n+ if (ARM_TBFLAG_THUMB(tb->flags)) {\n+ ops = &thumb_translator_ops;\n+ }\n #ifdef TARGET_AARCH64\n if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n ops = &aarch64_translator_ops;\n", "prefixes": [ "PULL", "31/32" ] }