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GET /api/patches/810706/?format=api
{ "id": 810706, "url": "http://patchwork.ozlabs.org/api/patches/810706/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-25-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-25-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:04", "name": "[PULL,24/32] target/arm: [tcg] Port to tb_stop", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0db7dd341b178b9bbcb399456f873312fefa7eaf", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-25-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810706/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810706/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"XLrOqJql\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTHG2w6sz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:16:42 +1000 (AEST)", "from localhost ([::1]:36995 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd0K-0008My-EW\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:16:40 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41973)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqr-0000Uc-DQ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqm-0002k9-4b\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:53 -0400", "from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:34481)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcql-0002jr-T8\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400", "by mail-pg0-x235.google.com with SMTP id q68so158773pgq.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:47 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=udUFVDShR2S/ublVBwFZxFSZzoHnpVkH6YgeO1JXXp4=;\n\tb=XLrOqJqlYaim7/bUYgt6j+tYAP+oG0MMShSn/NCaN4LrhZLd4HGsgIp6BCARIrJ5rb\n\tUNhCkGBAIuUoCPMdZmf901+czVxeMCO1oSBk6DmfI1I1ibt0NKsGO2gIzsR5z7OXWUDK\n\tKZcrn3sbmSQRzYyuY4xPeqhlPzjH0Cxr2jIWE=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=udUFVDShR2S/ublVBwFZxFSZzoHnpVkH6YgeO1JXXp4=;\n\tb=B67ryNT1puuz9HRj7/0nrU5Lo29YCbPlRynCviboyGl5fpBFrg2EKvY7m1J+3kDFi3\n\t0jc8KRPwb+SKp/cgkJ+K6eaRHVFYCQPspY44DlF8sKt7XJKZF/ENLbLaDkm/Ounsr1Op\n\t9H2zctcGd0W1oTqDtSKtiFde5cRFvzQg7FXupMr2A03SNjPLHz1E6PlQg+yyr4ED4Qde\n\ttB4E3C9cKL30Fgmc3UPMEWtIlZKsJY1PL7LMSl8aofa/0t8njBGMa5Sfsoq6XgwROZRf\n\tSijOiB2A5WzFjHawTu12iODr3HQ7hBGyrnQ8ew8YulD90u7LgSirDX6BmZw2qIIfBzxO\n\tridg==", "X-Gm-Message-State": "AHPjjUjT0LV2pP3JoVDsPIv8p1lYgpmYyMpmHMkRkayBRKtuLK5YXwOv\n\tHydMhsyaV7ay5OSbcvG1Tw==", "X-Google-Smtp-Source": "ADKCNb4zHeSs4rgl2PkXxdtg8hVWMceurk7I0fENU9aF3tzh0mAdXFIH9VkpRGA1YVuFAyjOyCLOkw==", "X-Received": "by 10.98.69.137 with SMTP id n9mr6788038pfi.164.1504714006495;\n\tWed, 06 Sep 2017 09:06:46 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:04 -0700", "Message-Id": "<20170906160612.22769-25-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::235", "Subject": "[Qemu-devel] [PULL 24/32] target/arm: [tcg] Port to tb_stop", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nMessage-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 161 ++++++++++++++++++++++++++-----------------------\n 1 file changed, 84 insertions(+), 77 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 5737299943..10527b50c8 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -12057,85 +12057,13 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n dc->base.pc_next = dc->pc;\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n {\n- DisasContext dc1, *dc = &dc1;\n- int max_insns;\n-\n- /* generate intermediate code */\n-\n- /* The A64 decoder has its own top level loop, because it doesn't need\n- * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n- */\n- if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n- gen_intermediate_code_a64(&dc->base, cs, tb);\n- return;\n- }\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- gen_tb_start(tb);\n-\n- tcg_clear_temp_count();\n- arm_tr_tb_start(&dc->base, cs);\n-\n- do {\n- dc->base.num_insns++;\n- arm_tr_insn_start(&dc->base, cs);\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n- if (dc->base.is_jmp > DISAS_TOO_MANY) {\n- break;\n- }\n- }\n-\n- if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- arm_tr_translate_insn(&dc->base, cs);\n-\n- if (tcg_check_temp_count()) {\n- fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n- dc->pc);\n- }\n-\n- if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n- dc->base.num_insns >= max_insns)) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n- } while (!dc->base.is_jmp);\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n \n- if (tb->cflags & CF_LAST_IO) {\n- if (dc->condjmp) {\n- /* FIXME: This can theoretically happen with self-modifying\n- code. */\n- cpu_abort(cs, \"IO on conditional branch instruction\");\n- }\n- gen_io_end();\n+ if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) {\n+ /* FIXME: This can theoretically happen with self-modifying code. */\n+ cpu_abort(cpu, \"IO on conditional branch instruction\");\n }\n \n /* At this stage dc->condjmp will only be set when the skipped\n@@ -12241,6 +12169,85 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n gen_goto_tb(dc, 1, dc->pc);\n }\n }\n+}\n+\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+{\n+ DisasContext dc1, *dc = &dc1;\n+ int max_insns;\n+\n+ /* generate intermediate code */\n+\n+ /* The A64 decoder has its own top level loop, because it doesn't need\n+ * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n+ */\n+ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n+ gen_intermediate_code_a64(&dc->base, cs, tb);\n+ return;\n+ }\n+\n+ dc->base.tb = tb;\n+ dc->base.pc_first = dc->base.tb->pc;\n+ dc->base.pc_next = dc->base.pc_first;\n+ dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.num_insns = 0;\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+\n+ max_insns = tb->cflags & CF_COUNT_MASK;\n+ if (max_insns == 0) {\n+ max_insns = CF_COUNT_MASK;\n+ }\n+ if (max_insns > TCG_MAX_INSNS) {\n+ max_insns = TCG_MAX_INSNS;\n+ }\n+ max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n+\n+ gen_tb_start(tb);\n+\n+ tcg_clear_temp_count();\n+ arm_tr_tb_start(&dc->base, cs);\n+\n+ do {\n+ dc->base.num_insns++;\n+ arm_tr_insn_start(&dc->base, cs);\n+\n+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n+ CPUBreakpoint *bp;\n+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n+ if (bp->pc == dc->base.pc_next) {\n+ if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n+ }\n+ }\n+ }\n+ if (dc->base.is_jmp > DISAS_TOO_MANY) {\n+ break;\n+ }\n+ }\n+\n+ if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n+ gen_io_start();\n+ }\n+\n+ arm_tr_translate_insn(&dc->base, cs);\n+\n+ if (tcg_check_temp_count()) {\n+ fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n+ dc->pc);\n+ }\n+\n+ if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n+ dc->base.num_insns >= max_insns)) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n+ } while (!dc->base.is_jmp);\n+\n+ if (dc->base.tb->cflags & CF_LAST_IO) {\n+ gen_io_end();\n+ }\n+\n+ arm_tr_tb_stop(&dc->base, cs);\n \n gen_tb_end(tb, dc->base.num_insns);\n \n", "prefixes": [ "PULL", "24/32" ] }