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GET /api/patches/810696/?format=api
{ "id": 810696, "url": "http://patchwork.ozlabs.org/api/patches/810696/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-9-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-9-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:05:48", "name": "[PULL,08/32] target/i386: [tcg] Port to init_disas_context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ebf711f4fbc986d112e92535d3b9a6516b6e8085", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-9-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810696/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810696/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"j6epNIpB\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnT7Y0mZvz9s76\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:10:00 +1000 (AEST)", "from localhost ([::1]:36966 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpctq-0002Xy-BU\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:09:58 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:41658)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqX-0008SC-7u\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:34 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqQ-0001p8-WD\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400", "from mail-pg0-x231.google.com ([2607:f8b0:400e:c05::231]:33605)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqQ-0001oG-NQ\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:26 -0400", "by mail-pg0-x231.google.com with SMTP id t3so16078080pgt.0\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:26 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.23\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=0yLW7ctcPD/DWG7PrJMW3lLrukj18jAqXKN1J9zeHP8=;\n\tb=j6epNIpBJPws696wzHJeQSNm0013QBV4JxNZ4PSB0lTNEJGYSMq9js8R/Ski8n1ltQ\n\tocunFyDXZLNU1I9gA7oaBbphGu3we0zmbb6FCvt5fUuYeDghQdhNGN22WEmrzGpdbFGw\n\tsvh44ahdhoswWEtlZmSi22flB+6rUqT5F5vsg=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=0yLW7ctcPD/DWG7PrJMW3lLrukj18jAqXKN1J9zeHP8=;\n\tb=lz7DLUwddkUOULRaMCMVIECUyoNGu0tQBABdDdUDTzHlav+LEZRl3Bjy3sc4ejD+sR\n\tDmdfWO04dIK4SVzXeT8iYJH9rWPTFimV3tDaysGzCT0VOBcbkqIhuqbv2e1q+AtJ0PD3\n\tn468elWw98uzwHSjOKuQiJkkXO2C9OCbspFah9tYDxMCj0Xk8RZrgX460JdFP6gHTeQr\n\tkHN9iMc6Y52yz1BEgWA2ywRMLxLfW8AFajReV468pmvmiUkUkaRfXok+y+aBUrTq2fSW\n\tE2kDBV6ESqfp2g07RxkGp0EQvONfshYJpxmoGqcEgyNQEwFJWn9ky8DF/bKvNDuj5hZ1\n\tho7Q==", "X-Gm-Message-State": "AHPjjUhxxvvKuUD5PimUK1iZa3V/deFIx6a8nR5vLHAeFxOAnho6QKND\n\tZsGb5qrEsHWMIQSKkHQupQ==", "X-Google-Smtp-Source": "ADKCNb4aMrf5UWcX8z4WvPP0srlrpSR5Hoi14MGmnxTRApX2oZFz4Z6bZvUKCC6N3HdLL6JfHSGu4g==", "X-Received": "by 10.99.143.89 with SMTP id r25mr8067193pgn.224.1504713985475; \n\tWed, 06 Sep 2017 09:06:25 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:05:48 -0700", "Message-Id": "<20170906160612.22769-9-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::231", "Subject": "[Qemu-devel] [PULL 08/32] target/i386: [tcg] Port to\n\tinit_disas_context", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nMessage-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan>\n[rth: Adjust for max_insns interface change.]\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/i386/translate.c | 46 +++++++++++++++++++++++++++-------------------\n 1 file changed, 27 insertions(+), 19 deletions(-)", "diff": "diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex 3a3d91c4d7..4281e9bc56 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8377,20 +8377,13 @@ void tcg_x86_init(void)\n }\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,\n+ int max_insns)\n {\n- CPUX86State *env = cs->env_ptr;\n- DisasContext dc1, *dc = &dc1;\n- uint32_t flags;\n- target_ulong cs_base;\n- int num_insns;\n- int max_insns;\n-\n- /* generate intermediate code */\n- dc->base.pc_first = tb->pc;\n- cs_base = tb->cs_base;\n- flags = tb->flags;\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUX86State *env = cpu->env_ptr;\n+ uint32_t flags = dc->base.tb->flags;\n+ target_ulong cs_base = dc->base.tb->cs_base;\n \n dc->pe = (flags >> HF_PE_SHIFT) & 1;\n dc->code32 = (flags >> HF_CS32_SHIFT) & 1;\n@@ -8401,11 +8394,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->cpl = (flags >> HF_CPL_SHIFT) & 3;\n dc->iopl = (flags >> IOPL_SHIFT) & 3;\n dc->tf = (flags >> TF_SHIFT) & 1;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n dc->cc_op = CC_OP_DYNAMIC;\n dc->cc_op_dirty = false;\n dc->cs_base = cs_base;\n- dc->base.tb = tb;\n dc->popl_esp_hack = 0;\n /* select memory access functions */\n dc->mem_index = 0;\n@@ -8423,7 +8414,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->code64 = (flags >> HF_CS64_SHIFT) & 1;\n #endif\n dc->flags = flags;\n- dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||\n+ dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled ||\n (flags & HF_INHIBIT_IRQ_MASK));\n /* Do not optimize repz jumps at all in icount mode, because\n rep movsS instructions are execured with different paths\n@@ -8435,7 +8426,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n record/replay modes and there will always be an\n additional step for ecx=0 when icount is enabled.\n */\n- dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT);\n+ dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT);\n #if 0\n /* check addseg logic */\n if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))\n@@ -8455,9 +8446,24 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n cpu_ptr1 = tcg_temp_new_ptr();\n cpu_cc_srcT = tcg_temp_local_new();\n \n+ return max_insns;\n+}\n+\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+{\n+ CPUX86State *env = cs->env_ptr;\n+ DisasContext dc1, *dc = &dc1;\n+ int num_insns;\n+ int max_insns;\n+\n+ /* generate intermediate code */\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+ dc->base.tb = tb;\n dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.pc_first = tb->pc;\n dc->base.pc_next = dc->base.pc_first;\n- num_insns = 0;\n+\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -8465,7 +8471,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n if (max_insns > TCG_MAX_INSNS) {\n max_insns = TCG_MAX_INSNS;\n }\n+ max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns);\n \n+ num_insns = 0;\n gen_tb_start(tb);\n for(;;) {\n tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);\n@@ -8498,7 +8506,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n the flag and abort the translation to give the irqs a\n change to be happen */\n if (dc->tf || dc->base.singlestep_enabled ||\n- (flags & HF_INHIBIT_IRQ_MASK)) {\n+ (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {\n gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n", "prefixes": [ "PULL", "08/32" ] }