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GET /api/patches/810668/?format=api
{ "id": 810668, "url": "http://patchwork.ozlabs.org/api/patches/810668/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/c96478e6-f637-36b6-b92f-ca034ef3df9f@foss.arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<c96478e6-f637-36b6-b92f-ca034ef3df9f@foss.arm.com>", "list_archive_url": null, "date": "2017-09-06T15:16:56", "name": "[arm-embedded,3/3,GCC/ARM] Add support for ARM Cortex-R52 processor", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "82dc2b9f086b2e3133cf31706c99dd704a0c2db9", "submitter": { "id": 67886, "url": "http://patchwork.ozlabs.org/api/people/67886/?format=api", "name": "Thomas Preudhomme", "email": "thomas.preudhomme@foss.arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/c96478e6-f637-36b6-b92f-ca034ef3df9f@foss.arm.com/mbox/", "series": [ { "id": 1831, "url": "http://patchwork.ozlabs.org/api/series/1831/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=1831", "date": "2017-09-06T15:12:44", "name": "[arm-embedded,1/3,GCC/ARM,ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1831/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810668/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810668/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461620-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461620-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"BT4J0u1Q\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRyY50Lvz9t2R\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 01:17:09 +1000 (AEST)", "(qmail 5495 invoked by alias); 6 Sep 2017 15:17:02 -0000", "(qmail 5485 invoked by uid 89); 6 Sep 2017 15:17:01 -0000", "from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 06 Sep 2017 15:16:59 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\t513A315AD\tfor <gcc-patches@gcc.gnu.org>;\n\tWed, 6 Sep 2017 08:16:58 -0700 (PDT)", "from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id F09023F578\tfor <gcc-patches@gcc.gnu.org>;\n\tWed, 6 Sep 2017 08:16:57 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; q=dns; s=default; b=NGLiEFNDwKwRjnGtW\n\tmc9zl9Xv+03xLMSQvA/XBD8soGN2UPmXGNUWi3ukXvttKg/k++IZJFBtBWF4XQq5\n\tQulancU+mFcaKXpZWrK7NcHesnaaL1ctGAeep4GXWDOVi4jY2yqt/oWe2NiUGrJv\n\t/05n4u/odX3PEfEoVS497I/b/0=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:references:subject:to:from:message-id:date:mime-version\n\t:in-reply-to:content-type; s=default; bh=07tcRJRjCx3DqWJ9qayJDK6\n\tGP8c=; b=BT4J0u1QBlMm9O2TxgYrDwcu0STt6MzP1SHt4pSLBPToUQTU1rGPST6\n\tZ5wiQH4df0hFhc1KeecuNjKVYkTFzDsQV5/DAyGt8RY9SEZrZSGXqk6OL+cIr/yx\n\tm2SpLnqG/ynKvXxq0NN4YEUAPQVPLuPRGTAPqKcaUB3kro5eIq34=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-25.7 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=", "X-HELO": "foss.arm.com", "References": "<cc66a32d-803f-d1f4-b29e-b98e742c02d9@foss.arm.com>", "Subject": "[arm-embedded] [PATCH 3/3,\n\tGCC/ARM] Add support for ARM Cortex-R52 processor", "To": "\"gcc-patches@gcc.gnu.org\" <gcc-patches@gcc.gnu.org>", "From": "Thomas Preudhomme <thomas.preudhomme@foss.arm.com>", "X-Forwarded-Message-Id": "<cc66a32d-803f-d1f4-b29e-b98e742c02d9@foss.arm.com>", "Message-ID": "<c96478e6-f637-36b6-b92f-ca034ef3df9f@foss.arm.com>", "Date": "Wed, 6 Sep 2017 16:16:56 +0100", "User-Agent": "Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.2.1", "MIME-Version": "1.0", "In-Reply-To": "<cc66a32d-803f-d1f4-b29e-b98e742c02d9@foss.arm.com>", "Content-Type": "multipart/mixed;\n\tboundary=\"------------F2C27993724916AD9EE4E710\"", "X-IsSubscribed": "yes" }, "content": "Hi,\n\nWe have decided to apply the following patch to the embedded-7-branch to enable \nArm Cortex-R52 support.\n\n*** gcc/ChangeLog.arm ***\n\n2017-09-04 Thomas Preud'homme <thomas.preudhomme@arm.com>\n\n Backport from mainline\n 2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>\n\n * config/arm/arm-cpus.in (cortex-r52): Add new entry.\n (armv8-r): Set ARM Cortex-R52 as default CPU.\n * config/arm/arm-tables.opt: Regenerate.\n * config/arm/arm-tune.md: Regenerate.\n * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM\n Cortex-R52.\n * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp\n extension for -mcpu=cortex-r52.\n\nBest regards,\n\nThomas\nHi,\n\nOn 29/06/17 16:13, Thomas Preudhomme wrote:\n> Please ignore this patch. I'll respin the patch on a more recent GCC.\n\nPlease find an updated patch in attachment.\n\nThis patch adds support for the ARM Cortex-R52 processor rencently\nannounced.\n\n[1] https://developer.arm.com/products/processors/cortex-r/cortex-r52\n\nChangeLog entry is as follows:\n\n*** gcc/ChangeLog ***\n\n2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>\n\n\t* config/arm/arm-cpus.in (cortex-r52): Add new entry.\n\t(armv8-r): Set ARM Cortex-R52 as default CPU.\n\t* config/arm/arm-tables.opt: Regenerate.\n\t* config/arm/arm-tune.md: Regenerate.\n\t* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM\n\tCortex-R52.\n\t* doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp\n\textension for -mcpu=cortex-r52.\n\nTested by building an arm-none-eabi GCC cross-compiler targeting Cortex-R52 and \nbuilding an hello world with it. Also checked that the .fpu option created by \nGCC for -mcpu=cortex-r52 and -mcpu=cortex-r52+nofp.dp is as expected \n(respectively .fpu neon-fp-armv8 and .fpu fpv5-sp-d16\n\nIs this ok for trunk?\n\nBest regards,\n\nThomas", "diff": "diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\nindex e2ff297aed7514073dbb3bf5ee86964f202e5a14..d009a9e18acb093aefe0f9d8d6de49489fc2325c 100644\n--- a/gcc/config/arm/arm-cpus.in\n+++ b/gcc/config/arm/arm-cpus.in\n@@ -381,7 +381,7 @@ begin arch armv8-m.main\n end arch armv8-m.main\n \n begin arch armv8-r\n- tune for cortex-r4\n+ tune for cortex-r52\n tune flags CO_PROC\n base 8R\n profile R\n@@ -1315,6 +1315,16 @@ begin cpu cortex-m33\n costs v7m\n end cpu cortex-m33\n \n+# V8 R-profile implementations.\n+begin cpu cortex-r52\n+ cname cortexr52\n+ tune flags LDSCHED\n+ architecture armv8-r+crc+simd\n+ fpu neon-fp-armv8\n+ option nofp.dp remove FP_DBL ALL_SIMD\n+ costs cortex\n+end cpu cortex-r52\n+\n # FPU entries\n # format:\n # begin fpu <name>\ndiff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt\nindex 51678c2566e841894c5c0e9c613c8c0f832e9988..4e508b1555a77628ff6e7cfea39c98b87caa840a 100644\n--- a/gcc/config/arm/arm-tables.opt\n+++ b/gcc/config/arm/arm-tables.opt\n@@ -357,6 +357,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)\n EnumValue\n Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)\n \n+EnumValue\n+Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)\n+\n Enum\n Name(arm_arch) Type(int)\n Known ARM architectures (for use with the -march= option):\ndiff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md\nindex ba2c7d8ecfdbf6966ebf04b680d587a0e057b161..1b3f7a94cc78fac8abf1042ef60c81a74eaf24eb 100644\n--- a/gcc/config/arm/arm-tune.md\n+++ b/gcc/config/arm/arm-tune.md\n@@ -57,5 +57,6 @@\n \tcortexa73,exynosm1,xgene1,\n \tcortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,\n \tcortexa73cortexa53,cortexa55,cortexa75,\n-\tcortexa75cortexa55,cortexm23,cortexm33\"\n+\tcortexa75cortexa55,cortexm23,cortexm33,\n+\tcortexr52\"\n \t(const (symbol_ref \"((enum attr_tune) arm_tune)\")))\ndiff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c\nindex 16171d4e801af46ad549314d1f376e90d5bff57c..5c29b94caaba4ff6f89a191f1d8edcf10431c0b3 100644\n--- a/gcc/config/arm/driver-arm.c\n+++ b/gcc/config/arm/driver-arm.c\n@@ -58,6 +58,7 @@ static struct vendor_cpu arm_cpu_table[] = {\n {\"0xc15\", \"armv7-r\", \"cortex-r5\"},\n {\"0xc17\", \"armv7-r\", \"cortex-r7\"},\n {\"0xc18\", \"armv7-r\", \"cortex-r8\"},\n+ {\"0xd13\", \"armv8-r+crc\", \"cortex-r52\"},\n {\"0xc20\", \"armv6-m\", \"cortex-m0\"},\n {\"0xc21\", \"armv6-m\", \"cortex-m1\"},\n {\"0xc23\", \"armv7-m\", \"cortex-m3\"},\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex e60edcae53ef3c995054b9b0229b5f0fccbb8462..a093b9bcf77b1f4b40992516e853826bb7d528d4 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -15538,7 +15538,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},\n @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},\n @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},\n @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7},\n-@samp{cortex-r8},\n+@samp{cortex-r8}, @samp{cortex-r52},\n @samp{cortex-m33},\n @samp{cortex-m23},\n @samp{cortex-m7},\n@@ -15628,7 +15628,7 @@ Disables the floating-point and SIMD instructions on\n \n @item +nofp.dp\n Disables the double-precision component of the floating-point instructions\n-on @samp{cortex-r5} and @samp{cortex-m7}.\n+on @samp{cortex-r5}, @samp{cortex-r52} and @samp{cortex-m7}.\n \n @item +nosimd\n Disables the SIMD (but not floating-point) instructions on\n", "prefixes": [ "arm-embedded", "3/3", "GCC/ARM" ] }