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GET /api/patches/810660/?format=api
{ "id": 810660, "url": "http://patchwork.ozlabs.org/api/patches/810660/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-13-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906144940.30880-13-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T14:49:38", "name": "[PULL,12/14] tcg/s390: Use distinct-operands facility", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "800c98cfac233bc882b1c8f1982872d057afda7c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-13-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1829, "url": "http://patchwork.ozlabs.org/api/series/1829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829", "date": "2017-09-06T14:49:28", "name": "[PULL,01/14] tcg: Remove support for ia64 as host", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810660/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"cBl9zFHo\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRbg31dxz9t50\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 01:00:47 +1000 (AEST)", "from localhost ([::1]:36568 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpboq-00069r-JZ\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 11:00:44 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:40046)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeT-0005Z9-Ip\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:50:08 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeR-0000QK-Rf\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:50:01 -0400", "from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:36411)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpbeR-0000O0-Iw\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:59 -0400", "by mail-pg0-x22d.google.com with SMTP id m9so15676489pgd.3\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 07:49:59 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th1sm3467646pfg.153.2017.09.06.07.49.56\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 07:49:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=qJj+qUFr6Zo+1Hg8zub+yjh+o26KIADSrmy0Op1uN0M=;\n\tb=cBl9zFHo4GVQcWUxXrEZ/zkxOYkr1NG9oXvW3NNWpxCcfhv3uYzZmIYAdlbFXEpx0z\n\t68G4je/5KxoPjDnJXSOHM4dI2jje2tTOKUIM1sIrAwWfgxU3GbypxSKXSwihoSEzsjIj\n\tib3Sf5wLOSKa0Gqvd0UipBmFF3GGiiVydOv+s=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=qJj+qUFr6Zo+1Hg8zub+yjh+o26KIADSrmy0Op1uN0M=;\n\tb=Azl5YgdeaHq5QNMm6XAj8jsPA8G3i5QrihtLZATd3Z0ujDGh6hQo9r5CHJkH9lZqT6\n\tyTi7p4oVasJl27KhxJjOspcVii0UTj+BQngykKzk8yWVhqbBxgRKZAmU6sEXYTWNDmok\n\t7BopwzoFPfQR17EEJF0bniccVqm2QLZm23tODjilt4u1FE7+QEvgiAX5JrMjo/Pd5VJz\n\tkO+2p5+I3rbi1AJiIhzk7k7wftEu8C1+DeGU8qm3vMTIh8VB5p6t9V5zq00XqI/5LV89\n\titE8pQFqFSOwPA0bGcjAc58JbB9FlvgXRp75fVc5PGxKow+pojZvFWwl/T6WTGlERnyZ\n\tQWFw==", "X-Gm-Message-State": "AHPjjUivgdpgOgrFWS0tTapDXUBZY3AD34yjmys7GLG6kzp+sUdtl4e1\n\tg7059rd7pgKhOVFCYU6Xrg==", "X-Google-Smtp-Source": "ADKCNb7+oYerAq/kwPivIGAj+WUkBumVbPn5aIuy+UEQHpJ6A7JuaSZRrpJ2GhZBDhzT+kTIGRdHSw==", "X-Received": "by 10.101.81.195 with SMTP id i3mr8153842pgq.246.1504709398290; \n\tWed, 06 Sep 2017 07:49:58 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 07:49:38 -0700", "Message-Id": "<20170906144940.30880-13-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906144940.30880-1-richard.henderson@linaro.org>", "References": "<20170906144940.30880-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22d", "Subject": "[Qemu-devel] [PULL 12/14] tcg/s390: Use distinct-operands facility", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nThis allows using a 3-operand insn form for some arithmetic,\nlogicals and shifts.\n\nAcked-by: Cornelia Huck <cohuck@redhat.com>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.h | 1 +\n tcg/s390/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++-----------\n 2 files changed, 91 insertions(+), 28 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h\nindex dc0e59193c..f7619a9ef1 100644\n--- a/tcg/s390/tcg-target.h\n+++ b/tcg/s390/tcg-target.h\n@@ -58,6 +58,7 @@ typedef enum TCGReg {\n #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))\n #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))\n #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND\n+#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND\n \n extern uint64_t s390_facilities;\n \ndiff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 5414c9d879..a80b07db65 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -159,6 +159,16 @@ typedef enum S390Opcode {\n \n RRF_LOCR = 0xb9f2,\n RRF_LOCGR = 0xb9e2,\n+ RRF_NRK = 0xb9f4,\n+ RRF_NGRK = 0xb9e4,\n+ RRF_ORK = 0xb9f6,\n+ RRF_OGRK = 0xb9e6,\n+ RRF_SRK = 0xb9f9,\n+ RRF_SGRK = 0xb9e9,\n+ RRF_SLRK = 0xb9fb,\n+ RRF_SLGRK = 0xb9eb,\n+ RRF_XRK = 0xb9f7,\n+ RRF_XGRK = 0xb9e7,\n \n RR_AR = 0x1a,\n RR_ALR = 0x1e,\n@@ -179,8 +189,11 @@ typedef enum S390Opcode {\n RSY_RLL = 0xeb1d,\n RSY_RLLG = 0xeb1c,\n RSY_SLLG = 0xeb0d,\n+ RSY_SLLK = 0xebdf,\n RSY_SRAG = 0xeb0a,\n+ RSY_SRAK = 0xebdc,\n RSY_SRLG = 0xeb0c,\n+ RSY_SRLK = 0xebde,\n \n RS_SLL = 0x89,\n RS_SRA = 0x8a,\n@@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,\n case TCG_COND_GEU:\n do_geu:\n /* We need \"real\" carry semantics, so use SUBTRACT LOGICAL\n- instead of COMPARE LOGICAL. This needs an extra move. */\n- tcg_out_mov(s, type, TCG_TMP0, c1);\n+ instead of COMPARE LOGICAL. This may need an extra move. */\n if (c2const) {\n- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n+ tcg_out_mov(s, type, TCG_TMP0, c1);\n if (type == TCG_TYPE_I32) {\n tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2);\n } else {\n tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2);\n }\n+ } else if (s390_facilities & FACILITY_DISTINCT_OPS) {\n+ if (type == TCG_TYPE_I32) {\n+ tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2);\n+ } else {\n+ tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2);\n+ }\n } else {\n+ tcg_out_mov(s, type, TCG_TMP0, c1);\n if (type == TCG_TYPE_I32) {\n tcg_out_insn(s, RR, SLR, TCG_TMP0, c2);\n } else {\n tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2);\n }\n- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n }\n+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);\n tcg_out_insn(s, RRE, ALCGR, dest, dest);\n return;\n \n@@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,\n static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n const TCGArg *args, const int *const_args)\n {\n- S390Opcode op;\n+ S390Opcode op, op2;\n TCGArg a0, a1, a2;\n \n switch (opc) {\n@@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (const_args[2]) {\n a2 = -a2;\n goto do_addi_32;\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, SR, a0, a2);\n+ } else {\n+ tcg_out_insn(s, RRF, SRK, a0, a1, a2);\n }\n- tcg_out_insn(s, RR, SR, args[0], args[2]);\n break;\n \n case INDEX_op_and_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen_andi(s, TCG_TYPE_I32, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen_andi(s, TCG_TYPE_I32, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, NR, a0, a2);\n } else {\n- tcg_out_insn(s, RR, NR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, NRK, a0, a1, a2);\n }\n break;\n case INDEX_op_or_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen64_ori(s, args[0], args[2] & 0xffffffff);\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen64_ori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RR, OR, a0, a2);\n } else {\n- tcg_out_insn(s, RR, OR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, ORK, a0, a1, a2);\n }\n break;\n case INDEX_op_xor_i32:\n+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n- tgen64_xori(s, args[0], args[2] & 0xffffffff);\n- } else {\n+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n+ tgen64_xori(s, a0, a2);\n+ } else if (a0 == a1) {\n tcg_out_insn(s, RR, XR, args[0], args[2]);\n+ } else {\n+ tcg_out_insn(s, RRF, XRK, a0, a1, a2);\n }\n break;\n \n@@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n \n case INDEX_op_shl_i32:\n op = RS_SLL;\n+ op2 = RSY_SLLK;\n do_shift32:\n- if (const_args[2]) {\n- tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]);\n+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];\n+ if (a0 == a1) {\n+ if (const_args[2]) {\n+ tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);\n+ } else {\n+ tcg_out_sh32(s, op, a0, a2, 0);\n+ }\n } else {\n- tcg_out_sh32(s, op, args[0], args[2], 0);\n+ /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */\n+ if (const_args[2]) {\n+ tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);\n+ } else {\n+ tcg_out_sh64(s, op2, a0, a1, a2, 0);\n+ }\n }\n break;\n case INDEX_op_shr_i32:\n op = RS_SRL;\n+ op2 = RSY_SRLK;\n goto do_shift32;\n case INDEX_op_sar_i32:\n op = RS_SRA;\n+ op2 = RSY_SRAK;\n goto do_shift32;\n \n case INDEX_op_rotl_i32:\n@@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (const_args[2]) {\n a2 = -a2;\n goto do_addi_64;\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, SGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, SGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, SGRK, a0, a1, a2);\n }\n break;\n \n case INDEX_op_and_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);\n- } else {\n+ } else if (a0 == a1) {\n tcg_out_insn(s, RRE, NGR, args[0], args[2]);\n+ } else {\n+ tcg_out_insn(s, RRF, NGRK, a0, a1, a2);\n }\n break;\n case INDEX_op_or_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n- tgen64_ori(s, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n+ tgen64_ori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, OGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, OGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, OGRK, a0, a1, a2);\n }\n break;\n case INDEX_op_xor_i64:\n+ a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n- tgen64_xori(s, args[0], args[2]);\n+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n+ tgen64_xori(s, a0, a2);\n+ } else if (a0 == a1) {\n+ tcg_out_insn(s, RRE, XGR, a0, a2);\n } else {\n- tcg_out_insn(s, RRE, XGR, args[0], args[2]);\n+ tcg_out_insn(s, RRF, XGRK, a0, a1, a2);\n }\n break;\n \n@@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_r_rM = { .args_ct_str = { \"r\", \"r\", \"rM\" } };\n static const TCGTargetOpDef r_0_r = { .args_ct_str = { \"r\", \"0\", \"r\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n@@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r_ri;\n case INDEX_op_sub_i32:\n case INDEX_op_sub_i64:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_mul_i32:\n /* If we have the general-instruction-extensions, then we have\n@@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n OI[LH][LH] instructions. By rejecting certain negative ranges,\n the immediate load plus the reg-reg OR is smaller. */\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_ri\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n : &r_0_rN);\n case INDEX_op_or_i64:\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_rM\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n : &r_0_rN);\n \n case INDEX_op_xor_i32:\n /* Without EXT_IMM, no immediates are supported. Otherwise,\n rejecting certain negative ranges leads to smaller code. */\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_ri\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n : &r_0_r);\n case INDEX_op_xor_i64:\n return (s390_facilities & FACILITY_EXT_IMM\n- ? &r_0_rM\n+ ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n : &r_0_r);\n \n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_shl_i32:\n case INDEX_op_shr_i32:\n case INDEX_op_sar_i32:\n- return &r_0_ri;\n+ return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_shl_i64:\n case INDEX_op_shr_i64:\n", "prefixes": [ "PULL", "12/14" ] }