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GET /api/patches/810657/?format=api
{ "id": 810657, "url": "http://patchwork.ozlabs.org/api/patches/810657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-8-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906144940.30880-8-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T14:49:33", "name": "[PULL,07/14] tcg/s390: Fully convert tcg_target_op_def", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbbfc374892634ee245dec24b5dbb2d533d24965", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-8-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1829, "url": "http://patchwork.ozlabs.org/api/series/1829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829", "date": "2017-09-06T14:49:28", "name": "[PULL,01/14] tcg: Remove support for ia64 as host", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810657/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DevstUMG\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRWG2Bt7z9s7C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 00:56:58 +1000 (AEST)", "from localhost ([::1]:36551 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpblA-0002YJ-Cp\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 10:56:56 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:39965)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeN-0005SG-CS\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:57 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeL-0000I5-PS\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:55 -0400", "from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:38096)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpbeL-0000Hn-Gp\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:53 -0400", "by mail-pg0-x233.google.com with SMTP id v66so15522895pgb.5\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 07:49:53 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th1sm3467646pfg.153.2017.09.06.07.49.51\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 07:49:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=p+fm15EhqRyfu1rpg+TS09ifjIYF4eyU99atv4ps14o=;\n\tb=DevstUMGsCHMFRxETi/tZzR99L2aE7B9qGONjGwqjqAueAUO5qZbT4VcLdtHcJieto\n\toSHO+R03fljUtDQsDDR+/nJbfYSf+X5WqxbzDjNlNBdeSIfEfSKYVvc+g6ExubVzQ3oC\n\t9y5PZDqfxIZKejNGFZFk7nbc1djM1Gg1UYs3I=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=p+fm15EhqRyfu1rpg+TS09ifjIYF4eyU99atv4ps14o=;\n\tb=IiZyWCR8F4QfBoRHK6Bjh/mCRMMhBD9BJnlogSkVcmUaznI6px2FRDALLNVa08kSJV\n\tnRHGgiIrId91wQCigdYvZHCyJ6FrMbW0Lq/hvkXm5Rkh2IkhS3GeZwkYy/07T68fHIlW\n\tCkkISvd5ge397IArY+15qF4avNJBq8Tm2ULhHMqdUYVMmUFb61pCVSwR+V4Y0641gY1x\n\tx7RunHNE0xLbr4fxa4/ndJb0idAdzE2EeDR5AEkgyyA2BX5o4vwJuKiPoKVuPFU97hdc\n\ts7Inh7eIpTfZA8rmtZVYWMjmXLHjSUKNTT1hbSPhDBTFlUWG7ImsuUJNRYViekyA59Tx\n\t124A==", "X-Gm-Message-State": "AHPjjUjBgz+YqI9ijhfQlnwvv7oUgBp6eACKaPaiqRXMm8FyIkpwulTf\n\tmIXFX1beI0epGCs99qoXAA==", "X-Google-Smtp-Source": "ADKCNb5Io6tNAE87qOU4M0cfRGeo6T0Avv/vMdWciUBXWjGgx5lCfQ+wxu2fegnz65r87GFxysjI4g==", "X-Received": "by 10.99.181.23 with SMTP id y23mr7721360pge.177.1504709392100; \n\tWed, 06 Sep 2017 07:49:52 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 07:49:33 -0700", "Message-Id": "<20170906144940.30880-8-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906144940.30880-1-richard.henderson@linaro.org>", "References": "<20170906144940.30880-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::233", "Subject": "[Qemu-devel] [PULL 07/14] tcg/s390: Fully convert tcg_target_op_def", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nUse a switch instead of searching a table.\n\nAcked-by: Cornelia Huck <cohuck@redhat.com>\nReviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 278 +++++++++++++++++++++++++---------------------\n 1 file changed, 154 insertions(+), 124 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 5d7083e90c..d34649eb13 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n }\n }\n \n-static const TCGTargetOpDef s390_op_defs[] = {\n- { INDEX_op_exit_tb, { } },\n- { INDEX_op_goto_tb, { } },\n- { INDEX_op_br, { } },\n- { INDEX_op_goto_ptr, { \"r\" } },\n-\n- { INDEX_op_ld8u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld8s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld16u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld16s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ld_i32, { \"r\", \"r\" } },\n- { INDEX_op_st8_i32, { \"r\", \"r\" } },\n- { INDEX_op_st16_i32, { \"r\", \"r\" } },\n- { INDEX_op_st_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_add_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_sub_i32, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_mul_i32, { \"r\", \"0\", \"rK\" } },\n-\n- { INDEX_op_div2_i32, { \"b\", \"a\", \"0\", \"1\", \"r\" } },\n- { INDEX_op_divu2_i32, { \"b\", \"a\", \"0\", \"1\", \"r\" } },\n-\n- { INDEX_op_and_i32, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_or_i32, { \"r\", \"0\", \"rO\" } },\n- { INDEX_op_xor_i32, { \"r\", \"0\", \"rX\" } },\n-\n- { INDEX_op_neg_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_shl_i32, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_shr_i32, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_sar_i32, { \"r\", \"0\", \"ri\" } },\n-\n- { INDEX_op_rotl_i32, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotr_i32, { \"r\", \"r\", \"ri\" } },\n-\n- { INDEX_op_ext8s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext8u_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext16s_i32, { \"r\", \"r\" } },\n- { INDEX_op_ext16u_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_bswap16_i32, { \"r\", \"r\" } },\n- { INDEX_op_bswap32_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_add2_i32, { \"r\", \"r\", \"0\", \"1\", \"rA\", \"r\" } },\n- { INDEX_op_sub2_i32, { \"r\", \"r\", \"0\", \"1\", \"rA\", \"r\" } },\n-\n- { INDEX_op_brcond_i32, { \"r\", \"rC\" } },\n- { INDEX_op_setcond_i32, { \"r\", \"r\", \"rC\" } },\n- { INDEX_op_movcond_i32, { \"r\", \"r\", \"rC\", \"r\", \"0\" } },\n- { INDEX_op_deposit_i32, { \"r\", \"rZ\", \"r\" } },\n- { INDEX_op_extract_i32, { \"r\", \"r\" } },\n-\n- { INDEX_op_qemu_ld_i32, { \"r\", \"L\" } },\n- { INDEX_op_qemu_ld_i64, { \"r\", \"L\" } },\n- { INDEX_op_qemu_st_i32, { \"L\", \"L\" } },\n- { INDEX_op_qemu_st_i64, { \"L\", \"L\" } },\n-\n- { INDEX_op_ld8u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld8s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld16u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld16s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld32u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld32s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ld_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_st8_i64, { \"r\", \"r\" } },\n- { INDEX_op_st16_i64, { \"r\", \"r\" } },\n- { INDEX_op_st32_i64, { \"r\", \"r\" } },\n- { INDEX_op_st_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_add_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_sub_i64, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_mul_i64, { \"r\", \"0\", \"rK\" } },\n-\n- { INDEX_op_div2_i64, { \"b\", \"a\", \"0\", \"1\", \"r\" } },\n- { INDEX_op_divu2_i64, { \"b\", \"a\", \"0\", \"1\", \"r\" } },\n- { INDEX_op_mulu2_i64, { \"b\", \"a\", \"0\", \"r\" } },\n-\n- { INDEX_op_and_i64, { \"r\", \"0\", \"ri\" } },\n- { INDEX_op_or_i64, { \"r\", \"0\", \"rO\" } },\n- { INDEX_op_xor_i64, { \"r\", \"0\", \"rX\" } },\n-\n- { INDEX_op_neg_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_shl_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_shr_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_sar_i64, { \"r\", \"r\", \"ri\" } },\n-\n- { INDEX_op_rotl_i64, { \"r\", \"r\", \"ri\" } },\n- { INDEX_op_rotr_i64, { \"r\", \"r\", \"ri\" } },\n-\n- { INDEX_op_ext8s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext8u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext16s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext16u_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext32s_i64, { \"r\", \"r\" } },\n- { INDEX_op_ext32u_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_ext_i32_i64, { \"r\", \"r\" } },\n- { INDEX_op_extu_i32_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_bswap16_i64, { \"r\", \"r\" } },\n- { INDEX_op_bswap32_i64, { \"r\", \"r\" } },\n- { INDEX_op_bswap64_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_clz_i64, { \"r\", \"r\", \"ri\" } },\n-\n- { INDEX_op_add2_i64, { \"r\", \"r\", \"0\", \"1\", \"rA\", \"r\" } },\n- { INDEX_op_sub2_i64, { \"r\", \"r\", \"0\", \"1\", \"rA\", \"r\" } },\n-\n- { INDEX_op_brcond_i64, { \"r\", \"rC\" } },\n- { INDEX_op_setcond_i64, { \"r\", \"r\", \"rC\" } },\n- { INDEX_op_movcond_i64, { \"r\", \"r\", \"rC\", \"r\", \"0\" } },\n- { INDEX_op_deposit_i64, { \"r\", \"0\", \"r\" } },\n- { INDEX_op_extract_i64, { \"r\", \"r\" } },\n-\n- { INDEX_op_mb, { } },\n- { -1 },\n-};\n-\n static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n {\n- int i, n = ARRAY_SIZE(s390_op_defs);\n+ static const TCGTargetOpDef r = { .args_ct_str = { \"r\" } };\n+ static const TCGTargetOpDef r_r = { .args_ct_str = { \"r\", \"r\" } };\n+ static const TCGTargetOpDef r_L = { .args_ct_str = { \"r\", \"L\" } };\n+ static const TCGTargetOpDef L_L = { .args_ct_str = { \"L\", \"L\" } };\n+ static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n+ static const TCGTargetOpDef r_0_rK = { .args_ct_str = { \"r\", \"0\", \"rK\" } };\n+ static const TCGTargetOpDef r_0_rO = { .args_ct_str = { \"r\", \"0\", \"rO\" } };\n+ static const TCGTargetOpDef r_0_rX = { .args_ct_str = { \"r\", \"0\", \"rX\" } };\n+\n+ switch (op) {\n+ case INDEX_op_goto_ptr:\n+ return &r;\n+\n+ case INDEX_op_ld8u_i32:\n+ case INDEX_op_ld8u_i64:\n+ case INDEX_op_ld8s_i32:\n+ case INDEX_op_ld8s_i64:\n+ case INDEX_op_ld16u_i32:\n+ case INDEX_op_ld16u_i64:\n+ case INDEX_op_ld16s_i32:\n+ case INDEX_op_ld16s_i64:\n+ case INDEX_op_ld_i32:\n+ case INDEX_op_ld32u_i64:\n+ case INDEX_op_ld32s_i64:\n+ case INDEX_op_ld_i64:\n+ case INDEX_op_st8_i32:\n+ case INDEX_op_st8_i64:\n+ case INDEX_op_st16_i32:\n+ case INDEX_op_st16_i64:\n+ case INDEX_op_st_i32:\n+ case INDEX_op_st32_i64:\n+ case INDEX_op_st_i64:\n+ return &r_r;\n+\n+ case INDEX_op_add_i32:\n+ case INDEX_op_add_i64:\n+ return &r_r_ri;\n+ case INDEX_op_sub_i32:\n+ case INDEX_op_sub_i64:\n+ return &r_0_ri;\n+ case INDEX_op_mul_i32:\n+ case INDEX_op_mul_i64:\n+ return &r_0_rK;\n+ case INDEX_op_or_i32:\n+ case INDEX_op_or_i64:\n+ return &r_0_rO;\n+ case INDEX_op_xor_i32:\n+ case INDEX_op_xor_i64:\n+ return &r_0_rX;\n+ case INDEX_op_and_i32:\n+ case INDEX_op_and_i64:\n+ return &r_0_ri;\n+\n+ case INDEX_op_shl_i32:\n+ case INDEX_op_shr_i32:\n+ case INDEX_op_sar_i32:\n+ return &r_0_ri;\n+\n+ case INDEX_op_shl_i64:\n+ case INDEX_op_shr_i64:\n+ case INDEX_op_sar_i64:\n+ return &r_r_ri;\n+\n+ case INDEX_op_rotl_i32:\n+ case INDEX_op_rotl_i64:\n+ case INDEX_op_rotr_i32:\n+ case INDEX_op_rotr_i64:\n+ return &r_r_ri;\n+\n+ case INDEX_op_brcond_i32:\n+ case INDEX_op_brcond_i64:\n+ return &r_rC;\n+\n+ case INDEX_op_bswap16_i32:\n+ case INDEX_op_bswap16_i64:\n+ case INDEX_op_bswap32_i32:\n+ case INDEX_op_bswap32_i64:\n+ case INDEX_op_bswap64_i64:\n+ case INDEX_op_neg_i32:\n+ case INDEX_op_neg_i64:\n+ case INDEX_op_ext8s_i32:\n+ case INDEX_op_ext8s_i64:\n+ case INDEX_op_ext8u_i32:\n+ case INDEX_op_ext8u_i64:\n+ case INDEX_op_ext16s_i32:\n+ case INDEX_op_ext16s_i64:\n+ case INDEX_op_ext16u_i32:\n+ case INDEX_op_ext16u_i64:\n+ case INDEX_op_ext32s_i64:\n+ case INDEX_op_ext32u_i64:\n+ case INDEX_op_ext_i32_i64:\n+ case INDEX_op_extu_i32_i64:\n+ case INDEX_op_extract_i32:\n+ case INDEX_op_extract_i64:\n+ return &r_r;\n+\n+ case INDEX_op_clz_i64:\n+ return &r_r_ri;\n+\n+ case INDEX_op_qemu_ld_i32:\n+ case INDEX_op_qemu_ld_i64:\n+ return &r_L;\n+ case INDEX_op_qemu_st_i64:\n+ case INDEX_op_qemu_st_i32:\n+ return &L_L;\n \n- for (i = 0; i < n; ++i) {\n- if (s390_op_defs[i].op == op) {\n- return &s390_op_defs[i];\n+ case INDEX_op_deposit_i32:\n+ case INDEX_op_deposit_i64:\n+ {\n+ static const TCGTargetOpDef dep\n+ = { .args_ct_str = { \"r\", \"rZ\", \"r\" } };\n+ return &dep;\n }\n+ case INDEX_op_setcond_i32:\n+ case INDEX_op_setcond_i64:\n+ {\n+ static const TCGTargetOpDef setc\n+ = { .args_ct_str = { \"r\", \"r\", \"rC\" } };\n+ return &setc;\n+ }\n+ case INDEX_op_movcond_i32:\n+ case INDEX_op_movcond_i64:\n+ {\n+ static const TCGTargetOpDef movc\n+ = { .args_ct_str = { \"r\", \"r\", \"rC\", \"r\", \"0\" } };\n+ return &movc;\n+ }\n+ case INDEX_op_div2_i32:\n+ case INDEX_op_div2_i64:\n+ case INDEX_op_divu2_i32:\n+ case INDEX_op_divu2_i64:\n+ {\n+ static const TCGTargetOpDef div2\n+ = { .args_ct_str = { \"b\", \"a\", \"0\", \"1\", \"r\" } };\n+ return &div2;\n+ }\n+ case INDEX_op_mulu2_i64:\n+ {\n+ static const TCGTargetOpDef mul2\n+ = { .args_ct_str = { \"b\", \"a\", \"0\", \"r\" } };\n+ return &mul2;\n+ }\n+ case INDEX_op_add2_i32:\n+ case INDEX_op_add2_i64:\n+ case INDEX_op_sub2_i32:\n+ case INDEX_op_sub2_i64:\n+ {\n+ static const TCGTargetOpDef arith2\n+ = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"rA\", \"r\" } };\n+ return &arith2;\n+ }\n+\n+ default:\n+ break;\n }\n return NULL;\n }\n", "prefixes": [ "PULL", "07/14" ] }