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GET /api/patches/810656/?format=api
{ "id": 810656, "url": "http://patchwork.ozlabs.org/api/patches/810656/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-10-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906144940.30880-10-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T14:49:35", "name": "[PULL,09/14] tcg/s390: Merge muli facilities check to tcg_target_op_def", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ae756a145016ba1421b06d026eaaefa5e4e3715c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-10-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1829, "url": "http://patchwork.ozlabs.org/api/series/1829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829", "date": "2017-09-06T14:49:28", "name": "[PULL,01/14] tcg: Remove support for ia64 as host", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810656/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810656/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"YnP+gHwd\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRV31ghMz9s7C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 00:55:55 +1000 (AEST)", "from localhost ([::1]:36549 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpbk9-0001gn-C7\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 10:55:53 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:40006)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeP-0005Ui-IS\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:58 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeO-0000K9-37\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:57 -0400", "from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:35656)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpbeN-0000It-TV\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:56 -0400", "by mail-pf0-x22b.google.com with SMTP id g13so13161392pfm.2\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 07:49:55 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th1sm3467646pfg.153.2017.09.06.07.49.53\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 07:49:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=TPNLGTYZB1aa87DpJlaOptzVcaG33WfqkGwLP8atXCU=;\n\tb=YnP+gHwdzJU0RZD7TVfHdjFp7UEcqixgDlzClf+xQZG5Iy0Wjv42k1xuObDhyptz2I\n\tFKWa9lxWvnjpDocqHWGIvkVqCDeA33VQ7+EuoS9ugh+RkerugLGTMTA++Lw0zXvP1aQC\n\tZkO9Q9Dwkc5qZq4g48LjdDFFvEF7TS63wBh88=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=TPNLGTYZB1aa87DpJlaOptzVcaG33WfqkGwLP8atXCU=;\n\tb=SUtKBgiyLCkl9zkiNbYdppHunVPs2oMhJKA5D+ShojP7iIY0UyVSJxnAY4I59PjdSh\n\ts7j3oJlEugL06xEVUW5PZbsKvRBK6dRiekalucNsQv89CWLKCZhQH0RmHu4OQjazbe24\n\ts8zvTvzrqkD9hyIK6aRUhQt0eca+VeVAW0cMUG2KpmSH+ESgHSCbc1P+KtX5sXftF2m/\n\t0aXnQGXUuP9I1S8e8k/keHBGbpBy5hUW49kCRDVoOO8XwEJjaoZqnJ/oh5RlKNMAu42D\n\tR7gciW0vxuySKjvmYI7kWilzzMZM4F/V0fi3k40aZ4Z4zoNHKtnsbIAUkGOXIKWdkBWZ\n\tkKFw==", "X-Gm-Message-State": "AHPjjUhyzTK4wG2uk1GBC6ssA3F8mZ2uRMqxqyUI/+sfkiiWSwxb7yv3\n\tnNZyiAFOx4H/wO6/qFuJsg==", "X-Google-Smtp-Source": "ADKCNb4mr4fSPwdUxv/2tlIh0+emi4NzVyKkibUSj/ZXpBUsBgssX/JkDPWkoSVW/fPNJBSIqeCJJA==", "X-Received": "by 10.98.209.66 with SMTP id t2mr7274142pfl.237.1504709394555;\n\tWed, 06 Sep 2017 07:49:54 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 07:49:35 -0700", "Message-Id": "<20170906144940.30880-10-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906144940.30880-1-richard.henderson@linaro.org>", "References": "<20170906144940.30880-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22b", "Subject": "[Qemu-devel] [PULL 09/14] tcg/s390: Merge muli facilities check to\n\ttcg_target_op_def", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nAcked-by: Cornelia Huck <cohuck@redhat.com>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++++++++++--------------------\n 1 file changed, 25 insertions(+), 20 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex e075b4844a..ff3f644f8e 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -38,12 +38,13 @@\n a 32-bit displacement here Just In Case. */\n #define USE_LONG_BRANCHES 0\n \n-#define TCG_CT_CONST_MULI 0x100\n-#define TCG_CT_CONST_ORI 0x200\n-#define TCG_CT_CONST_XORI 0x400\n-#define TCG_CT_CONST_U31 0x800\n-#define TCG_CT_CONST_ADLI 0x1000\n-#define TCG_CT_CONST_ZERO 0x2000\n+#define TCG_CT_CONST_S16 0x100\n+#define TCG_CT_CONST_S32 0x200\n+#define TCG_CT_CONST_ORI 0x400\n+#define TCG_CT_CONST_XORI 0x800\n+#define TCG_CT_CONST_U31 0x1000\n+#define TCG_CT_CONST_ADLI 0x2000\n+#define TCG_CT_CONST_ZERO 0x4000\n \n /* Several places within the instruction set 0 means \"no register\"\n rather than TCG_REG_R0. */\n@@ -388,8 +389,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'A':\n ct->ct |= TCG_CT_CONST_ADLI;\n break;\n- case 'K':\n- ct->ct |= TCG_CT_CONST_MULI;\n+ case 'I':\n+ ct->ct |= TCG_CT_CONST_S16;\n+ break;\n+ case 'J':\n+ ct->ct |= TCG_CT_CONST_S32;\n break;\n case 'O':\n ct->ct |= TCG_CT_CONST_ORI;\n@@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n }\n \n /* The following are mutually exclusive. */\n- if (ct & TCG_CT_CONST_MULI) {\n- /* Immediates that may be used with multiply. If we have the\n- general-instruction-extensions, then we have MULTIPLY SINGLE\n- IMMEDIATE with a signed 32-bit, otherwise we have only\n- MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */\n- if (s390_facilities & FACILITY_GEN_INST_EXT) {\n- return val == (int32_t)val;\n- } else {\n- return val == (int16_t)val;\n- }\n+ if (ct & TCG_CT_CONST_S16) {\n+ return val == (int16_t)val;\n+ } else if (ct & TCG_CT_CONST_S32) {\n+ return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_ADLI) {\n return tcg_match_add2i(type, val);\n } else if (ct & TCG_CT_CONST_ORI) {\n@@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n- static const TCGTargetOpDef r_0_rK = { .args_ct_str = { \"r\", \"0\", \"rK\" } };\n+ static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n+ static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n static const TCGTargetOpDef r_0_rO = { .args_ct_str = { \"r\", \"0\", \"rO\" } };\n static const TCGTargetOpDef r_0_rX = { .args_ct_str = { \"r\", \"0\", \"rX\" } };\n \n@@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_sub_i32:\n case INDEX_op_sub_i64:\n return &r_0_ri;\n+\n case INDEX_op_mul_i32:\n+ /* If we have the general-instruction-extensions, then we have\n+ MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we\n+ have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */\n+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);\n case INDEX_op_mul_i64:\n- return &r_0_rK;\n+ return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n+\n case INDEX_op_or_i32:\n case INDEX_op_or_i64:\n return &r_0_rO;\n", "prefixes": [ "PULL", "09/14" ] }