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GET /api/patches/810651/?format=api
{ "id": 810651, "url": "http://patchwork.ozlabs.org/api/patches/810651/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-12-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906144940.30880-12-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T14:49:37", "name": "[PULL,11/14] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0e48d1c51170b62afe66921b27f1e6a636feda00", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-12-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1829, "url": "http://patchwork.ozlabs.org/api/series/1829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829", "date": "2017-09-06T14:49:28", "name": "[PULL,01/14] tcg: Remove support for ia64 as host", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810651/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810651/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"I9uUcfxJ\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRR3515sz9t50\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 00:53:18 +1000 (AEST)", "from localhost ([::1]:36533 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpbhc-0007i4-VW\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 10:53:17 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:40027)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeR-0005X6-Kd\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:50:00 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeQ-0000Nk-Fa\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:59 -0400", "from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:34049)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpbeQ-0000NT-80\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:58 -0400", "by mail-pf0-x235.google.com with SMTP id m1so13164678pfk.1\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 07:49:58 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th1sm3467646pfg.153.2017.09.06.07.49.55\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 07:49:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=2WZZZTMLwUl3SfN7A3Lt68OYaqUGCTUc3gsUYrJAz24=;\n\tb=I9uUcfxJBY0PznyInvEIbokDxbHdeucY1r9dJK0gQzeS4U7N1NG5jssX1ScYPSeEdZ\n\tS4DBdWglVPGJrWJQFD2hcqtb6QQW5jYgdDXrVvtsW5ZrWtlckfFveTODLkoGfsHQWIjX\n\th5gWXO0ri7MmvsLsat2kelzmjHKBwh82gauGM=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=2WZZZTMLwUl3SfN7A3Lt68OYaqUGCTUc3gsUYrJAz24=;\n\tb=aU8ppx3QN5+8hE8SfA2KoNG8SALakGTFzRnHyNWK+jNVNcdlQtvallauFVVOGDqM0N\n\tNM7vxbJfqZgyyKwFAsdwTKrPwGT+qRRMyFooOyDcEmsVILpVjDXVWtPvV+9KmSuq6lFM\n\tjz9Ix0QMtDoR1LexJlODu/4pZCN2ubLGlRg/4RQJ82roy3gRP5qWde55XWB0It131wXv\n\tn2E1OnvVJ+zidk2r1ppSwgQbhomtkFHi8KelKJGXMU89jZ4dQMGCHkoF8Av6qut/vc5c\n\t6CpK8hOjvGUOttuHdGg9cYcFsTYasn/e19R+9Jn3bvwVIZZPvmq1P4QLyw8bSTUL+e+E\n\tc7Eg==", "X-Gm-Message-State": "AHPjjUibSb3KM9es6SL/eiN2znufmFA9aI02GKI9eVpdixncGYvZAa8m\n\tX10K+Ql2DKDEyyuTjJY1qQ==", "X-Google-Smtp-Source": "ADKCNb7TvskGMLPLjOJ/6CmjPkj5ZQsL5UF4H8jhRkNIjRfAR0+g+2ClkY6yBed8mJEuosH2AeNpDg==", "X-Received": "by 10.84.232.76 with SMTP id f12mr8240446pln.297.1504709396944; \n\tWed, 06 Sep 2017 07:49:56 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 07:49:37 -0700", "Message-Id": "<20170906144940.30880-12-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906144940.30880-1-richard.henderson@linaro.org>", "References": "<20170906144940.30880-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::235", "Subject": "[Qemu-devel] [PULL 11/14] tcg/s390: Merge ori+xori facilities check\n\tto tcg_target_op_def", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nAcked-by: Cornelia Huck <cohuck@redhat.com>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 101 +++++++++++++++-------------------------------\n 1 file changed, 33 insertions(+), 68 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex 6b08ccea6d..5414c9d879 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -40,8 +40,8 @@\n \n #define TCG_CT_CONST_S16 0x100\n #define TCG_CT_CONST_S32 0x200\n-#define TCG_CT_CONST_ORI 0x400\n-#define TCG_CT_CONST_XORI 0x800\n+#define TCG_CT_CONST_NN16 0x400\n+#define TCG_CT_CONST_NN32 0x800\n #define TCG_CT_CONST_U31 0x1000\n #define TCG_CT_CONST_S33 0x2000\n #define TCG_CT_CONST_ZERO 0x4000\n@@ -395,11 +395,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'J':\n ct->ct |= TCG_CT_CONST_S32;\n break;\n- case 'O':\n- ct->ct |= TCG_CT_CONST_ORI;\n+ case 'N':\n+ ct->ct |= TCG_CT_CONST_NN16;\n break;\n- case 'X':\n- ct->ct |= TCG_CT_CONST_XORI;\n+ case 'M':\n+ ct->ct |= TCG_CT_CONST_NN32;\n break;\n case 'C':\n /* ??? We have no insight here into whether the comparison is\n@@ -424,60 +424,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n return ct_str;\n }\n \n-/* Immediates to be used with logical OR. This is an optimization only,\n- since a full 64-bit immediate OR can always be performed with 4 sequential\n- OI[LH][LH] instructions. What we're looking for is immediates that we\n- can load efficiently, and the immediate load plus the reg-reg OR is\n- smaller than the sequential OI's. */\n-\n-static int tcg_match_ori(TCGType type, tcg_target_long val)\n-{\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- if (type == TCG_TYPE_I32) {\n- /* All 32-bit ORs can be performed with 1 48-bit insn. */\n- return 1;\n- }\n- }\n-\n- /* Look for negative values. These are best to load with LGHI. */\n- if (val < 0) {\n- if (val == (int16_t)val) {\n- return 0;\n- }\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- if (val == (int32_t)val) {\n- return 0;\n- }\n- }\n- }\n-\n- return 1;\n-}\n-\n-/* Immediates to be used with logical XOR. This is almost, but not quite,\n- only an optimization. XOR with immediate is only supported with the\n- extended-immediate facility. That said, there are a few patterns for\n- which it is better to load the value into a register first. */\n-\n-static int tcg_match_xori(TCGType type, tcg_target_long val)\n-{\n- if ((s390_facilities & FACILITY_EXT_IMM) == 0) {\n- return 0;\n- }\n-\n- if (type == TCG_TYPE_I32) {\n- /* All 32-bit XORs can be performed with 1 48-bit insn. */\n- return 1;\n- }\n-\n- /* Look for negative values. These are best to load with LGHI. */\n- if (val < 0 && val == (int32_t)val) {\n- return 0;\n- }\n-\n- return 1;\n-}\n-\n /* Test if a constant matches the constraint. */\n static int tcg_target_const_match(tcg_target_long val, TCGType type,\n const TCGArgConstraint *arg_ct)\n@@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_S33) {\n return val >= -0xffffffffll && val <= 0xffffffffll;\n- } else if (ct & TCG_CT_CONST_ORI) {\n- return tcg_match_ori(type, val);\n- } else if (ct & TCG_CT_CONST_XORI) {\n- return tcg_match_xori(type, val);\n+ } else if (ct & TCG_CT_CONST_NN16) {\n+ return !(val < 0 && val == (int16_t)val);\n+ } else if (ct & TCG_CT_CONST_NN32) {\n+ return !(val < 0 && val == (int32_t)val);\n } else if (ct & TCG_CT_CONST_U31) {\n return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n@@ -2222,11 +2168,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { \"r\", \"0\", \"r\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n- static const TCGTargetOpDef r_0_rO = { .args_ct_str = { \"r\", \"0\", \"rO\" } };\n- static const TCGTargetOpDef r_0_rX = { .args_ct_str = { \"r\", \"0\", \"rX\" } };\n+ static const TCGTargetOpDef r_0_rN = { .args_ct_str = { \"r\", \"0\", \"rN\" } };\n+ static const TCGTargetOpDef r_0_rM = { .args_ct_str = { \"r\", \"0\", \"rM\" } };\n static const TCGTargetOpDef a2_r\n = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"r\", \"r\" } };\n static const TCGTargetOpDef a2_ri\n@@ -2275,11 +2222,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n \n case INDEX_op_or_i32:\n+ /* The use of [iNM] constraints are optimization only, since a full\n+ 64-bit immediate OR can always be performed with 4 sequential\n+ OI[LH][LH] instructions. By rejecting certain negative ranges,\n+ the immediate load plus the reg-reg OR is smaller. */\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_ri\n+ : &r_0_rN);\n case INDEX_op_or_i64:\n- return &r_0_rO;\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_rM\n+ : &r_0_rN);\n+\n case INDEX_op_xor_i32:\n+ /* Without EXT_IMM, no immediates are supported. Otherwise,\n+ rejecting certain negative ranges leads to smaller code. */\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_ri\n+ : &r_0_r);\n case INDEX_op_xor_i64:\n- return &r_0_rX;\n+ return (s390_facilities & FACILITY_EXT_IMM\n+ ? &r_0_rM\n+ : &r_0_r);\n+\n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n return &r_0_ri;\n", "prefixes": [ "PULL", "11/14" ] }