Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/810648/?format=api
{ "id": 810648, "url": "http://patchwork.ozlabs.org/api/patches/810648/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-4-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906144940.30880-4-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T14:49:29", "name": "[PULL,03/14] tcg: Implement implicit ordering semantics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d7cc15bd3edaccdc9274836327ed48b3930ddb1e", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906144940.30880-4-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1829, "url": "http://patchwork.ozlabs.org/api/series/1829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1829", "date": "2017-09-06T14:49:28", "name": "[PULL,01/14] tcg: Remove support for ia64 as host", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1829/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810648/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810648/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"atvvmcMz\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnRMw6Jd8z9t50\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 00:50:36 +1000 (AEST)", "from localhost ([::1]:36523 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpbf0-0005PM-W5\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 10:50:35 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:39907)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeH-0005Nx-M8\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpbeG-0000AL-IP\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:49 -0400", "from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:33430)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpbeG-00009w-Ca\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:48 -0400", "by mail-pf0-x22d.google.com with SMTP id y68so13174869pfd.0\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 07:49:48 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\th1sm3467646pfg.153.2017.09.06.07.49.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 07:49:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=RK/3SaYDnTtoPHuQstqpOcx+UbVMkRmtrESkuekKT5w=;\n\tb=atvvmcMz2LAhNeuCrDFxOB/ZrYcYojkaIDWDaYpybGoHm8wRwOPV4ralVAWaXtWe+5\n\tgitlPDXLfQF7zE7D/eTPpAfvH+kX+FNhPDbfUHffSQB3wt6ubi9T7NxoxgVQcczph6/m\n\t4fW9OhdjEwmuGHjaZiTDNobnhT9HEGftk6vVw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=RK/3SaYDnTtoPHuQstqpOcx+UbVMkRmtrESkuekKT5w=;\n\tb=dpKrdpz4zoQ8CIpaDH6TOr97hcx6aiPYt1w1xS8U+Nv9dSY6POWXgj+zeT7vkxk7ie\n\tAA1Yw2R4DilVXGf/IxISJOiYGmOjWYah542xFjUNWJ1ucphXCdFgnvoxF/Ka11TQplIU\n\tXHWXC/IbcrAHi0JmdFrPKWnRTGDhIhaQC/J5GQCmCm8FCuxBR8/1ZfxO9A3C949tgff8\n\tlxVfZAn8ZspTneZvob/vkLzkK1o70wsB2nTgDWcXDRGFWlkJZNg3wqbz+tVPtciWom16\n\tRD/ihHaMchultB1zAlWTSCkoH2oQPc+FDFkXMCTtGp2cV5BnsiCg2xxprqVnWLOH+Vy8\n\tc4Rg==", "X-Gm-Message-State": "AHPjjUhAYGAYvomAmYNqMm53FK4fFIabpXTpy3p/bygyp3KoRh86kDPP\n\tX3hT/kJKNO4H4oSejY2nhg==", "X-Google-Smtp-Source": "ADKCNb7Ng5tqETixcAYxa9yKG23vqhjlgyp5/cn1ior8iRCMr7dxPcImKiBSsFBudQxdL1NKhlLKxQ==", "X-Received": "by 10.98.27.73 with SMTP id b70mr7390084pfb.21.1504709386982;\n\tWed, 06 Sep 2017 07:49:46 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 07:49:29 -0700", "Message-Id": "<20170906144940.30880-4-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906144940.30880-1-richard.henderson@linaro.org>", "References": "<20170906144940.30880-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::22d", "Subject": "[Qemu-devel] [PULL 03/14] tcg: Implement implicit ordering semantics", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Pranith Kumar <bobby.prani@gmail.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Pranith Kumar <bobby.prani@gmail.com>\n\nCurrently, we cannot use mttcg for running strong memory model guests\non weak memory model hosts due to missing ordering semantics.\n\nWe implicitly generate fence instructions for stronger guests if an\nordering mismatch is detected. We generate fences only for the orders\nfor which fence instructions are necessary, for example a fence is not\nnecessary between a store and a subsequent load on x86 since its\nabsence in the guest binary tells that ordering need not be\nensured. Also note that if we find multiple subsequent fence\ninstructions in the generated IR, we combine them in the TCG\noptimization pass.\n\nThis patch allows us to boot an x86 guest on ARM64 hosts using mttcg.\n\nSigned-off-by: Pranith Kumar <bobby.prani@gmail.com>\nMessage-Id: <20170829063313.10237-4-bobby.prani@gmail.com>\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n tcg/tcg-op.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)", "diff": "diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 87f673ef49..688d91755b 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -28,6 +28,7 @@\n #include \"exec/exec-all.h\"\n #include \"tcg.h\"\n #include \"tcg-op.h\"\n+#include \"tcg-mo.h\"\n #include \"trace-tcg.h\"\n #include \"trace/mem.h\"\n \n@@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,\n #endif\n }\n \n+static void tcg_gen_req_mo(TCGBar type)\n+{\n+#ifdef TCG_GUEST_DEFAULT_MO\n+ type &= TCG_GUEST_DEFAULT_MO;\n+#endif\n+ type &= ~TCG_TARGET_DEFAULT_MO;\n+ if (type) {\n+ tcg_gen_mb(type | TCG_BAR_SC);\n+ }\n+}\n+\n void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);\n memop = tcg_canonicalize_memop(memop, 0, 0);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 0));\n@@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);\n memop = tcg_canonicalize_memop(memop, 0, 1);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 1));\n@@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);\n if (memop & MO_SIGN) {\n@@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);\n return;\n", "prefixes": [ "PULL", "03/14" ] }